1 //*-----------------------------------------------------------------------------
2 //* ATMEL Microcontroller Software Support - ROUSSET -
3 //*-----------------------------------------------------------------------------
4 //* The software is delivered "AS IS" without warranty or condition of any
5 //* kind, either express, implied or statutory. This includes without
6 //* limitation any warranty or condition with respect to merchantability or
7 //* fitness for any particular purpose, or against the infringements of
8 //* intellectual property rights of others.
9 //*-----------------------------------------------------------------------------
11 //* Object : External Bus Interface Definition File
12 //* Translator : ARM Software Development Toolkit V2.11a
14 //* 1.0 03/11/97 JCZ : Creation
15 //* 2.0 21/10/98 JCZ : Clean up
16 //*-----------------------------------------------------------------------------
21 /*----------------------------------------*/
22 /* Memory Controller Interface Definition */
23 /*----------------------------------------*/
27 at91_reg EBI_CSR[8] ; /* Chip Select Register */
28 at91_reg EBI_RCR ; /* Remap Control Register */
29 at91_reg EBI_MCR ; /* Memory Control Register */
32 /*-----------------------*/
33 /* Chip Select Registers */
34 /*-----------------------*/
37 #define DataBus16 (1<<0)
38 #define DataBus8 (2<<0)
41 /* Number of Wait States */
43 #define WaitState1 (0<<B_NWS)
44 #define WaitState2 (1<<B_NWS)
45 #define WaitState3 (2<<B_NWS)
46 #define WaitState4 (3<<B_NWS)
47 #define WaitState5 (4<<B_NWS)
48 #define WaitState6 (5<<B_NWS)
49 #define WaitState7 (6<<B_NWS)
50 #define WaitState8 (7<<B_NWS)
51 #define NWS (7<<B_NWS)
53 /* Wait State Enable */
54 #define WaitStateDisable (0<<5)
55 #define WaitStateEnable (1<<5)
59 #define PageSize1M (0<<7)
60 #define PageSize4M (1<<7)
61 #define PageSize16M (2<<7)
62 #define PageSize64M (3<<7)
65 /* Number of Data Float Output Time Clock Cycle */
67 #define tDF_0cycle (0<<B_TDF)
68 #define tDF_1cycle (1<<B_TDF)
69 #define tDF_2cycle (2<<B_TDF)
70 #define tDF_3cycle (3<<B_TDF)
71 #define tDF_4cycle (4<<B_TDF)
72 #define tDF_5cycle (5<<B_TDF)
73 #define tDF_6cycle (6<<B_TDF)
74 #define tDF_7cycle (7<<B_TDF)
75 #define TDF (7<<B_TDF)
77 /* Byte Access Type */
78 #define ByteWriteAccessType (0<<12)
79 #define ByteSelectAccessType (1<<12)
82 /* Chip Select Enable */
83 #define CSEnable (1<<13)
84 #define CSDisable (0<<13)
87 #define BA ((u_int)(0xFFF)<<20)
89 /*-------------------------*/
90 /* Memory Control Register */
91 /*-------------------------*/
93 /* Address Line Enable */
95 #define BankSize16M (0<<0)
96 #define BankSize8M (4<<0)
97 #define BankSize4M (5<<0)
98 #define BankSize2M (6<<0)
99 #define BankSize1M (7<<0)
101 /* Data Read Protocol */
102 #define StandardReadProtocol (0<<4)
103 #define EarlyReadProtocol (1<<4)
106 /*------------------------*/
107 /* Remap Control Register */
108 /*------------------------*/
112 /*--------------------------------*/
113 /* Device Dependancies Definition */
114 /*--------------------------------*/
117 /* External Bus Interface User Interface BAse Address */
118 #define EBI_BASE ((StructEBI *) 0xFFE00000)