1 //*-----------------------------------------------------------------------------
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2 //* ATMEL Microcontroller Software Support - ROUSSET -
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3 //*-----------------------------------------------------------------------------
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4 //* The software is delivered "AS IS" without warranty or condition of any
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5 //* kind, either express, implied or statutory. This includes without
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6 //* limitation any warranty or condition with respect to merchantability or
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7 //* fitness for any particular purpose, or against the infringements of
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8 //* intellectual property rights of others.
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9 //*-----------------------------------------------------------------------------
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10 //* File Name : ebi.h
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11 //* Object : External Bus Interface Definition File
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12 //* Translator : ARM Software Development Toolkit V2.11a
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14 //* 1.0 03/11/97 JCZ : Creation
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15 //* 2.0 21/10/98 JCZ : Clean up
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16 //*-----------------------------------------------------------------------------
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21 /*----------------------------------------*/
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22 /* Memory Controller Interface Definition */
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23 /*----------------------------------------*/
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27 at91_reg EBI_CSR[8] ; /* Chip Select Register */
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28 at91_reg EBI_RCR ; /* Remap Control Register */
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29 at91_reg EBI_MCR ; /* Memory Control Register */
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32 /*-----------------------*/
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33 /* Chip Select Registers */
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34 /*-----------------------*/
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36 /* Data Bus Width */
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37 #define DataBus16 (1<<0)
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38 #define DataBus8 (2<<0)
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41 /* Number of Wait States */
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43 #define WaitState1 (0<<B_NWS)
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44 #define WaitState2 (1<<B_NWS)
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45 #define WaitState3 (2<<B_NWS)
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46 #define WaitState4 (3<<B_NWS)
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47 #define WaitState5 (4<<B_NWS)
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48 #define WaitState6 (5<<B_NWS)
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49 #define WaitState7 (6<<B_NWS)
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50 #define WaitState8 (7<<B_NWS)
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51 #define NWS (7<<B_NWS)
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53 /* Wait State Enable */
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54 #define WaitStateDisable (0<<5)
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55 #define WaitStateEnable (1<<5)
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59 #define PageSize1M (0<<7)
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60 #define PageSize4M (1<<7)
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61 #define PageSize16M (2<<7)
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62 #define PageSize64M (3<<7)
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63 #define PAGES (3<<7)
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65 /* Number of Data Float Output Time Clock Cycle */
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67 #define tDF_0cycle (0<<B_TDF)
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68 #define tDF_1cycle (1<<B_TDF)
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69 #define tDF_2cycle (2<<B_TDF)
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70 #define tDF_3cycle (3<<B_TDF)
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71 #define tDF_4cycle (4<<B_TDF)
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72 #define tDF_5cycle (5<<B_TDF)
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73 #define tDF_6cycle (6<<B_TDF)
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74 #define tDF_7cycle (7<<B_TDF)
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75 #define TDF (7<<B_TDF)
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77 /* Byte Access Type */
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78 #define ByteWriteAccessType (0<<12)
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79 #define ByteSelectAccessType (1<<12)
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82 /* Chip Select Enable */
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83 #define CSEnable (1<<13)
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84 #define CSDisable (0<<13)
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87 #define BA ((u_int)(0xFFF)<<20)
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89 /*-------------------------*/
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90 /* Memory Control Register */
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91 /*-------------------------*/
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93 /* Address Line Enable */
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95 #define BankSize16M (0<<0)
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96 #define BankSize8M (4<<0)
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97 #define BankSize4M (5<<0)
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98 #define BankSize2M (6<<0)
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99 #define BankSize1M (7<<0)
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101 /* Data Read Protocol */
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102 #define StandardReadProtocol (0<<4)
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103 #define EarlyReadProtocol (1<<4)
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106 /*------------------------*/
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107 /* Remap Control Register */
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108 /*------------------------*/
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112 /*--------------------------------*/
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113 /* Device Dependancies Definition */
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114 /*--------------------------------*/
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117 /* External Bus Interface User Interface BAse Address */
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118 #define EBI_BASE ((StructEBI *) 0xFFE00000)
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