1 //*----------------------------------------------------------------------------
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2 //* ATMEL Microcontroller Software Support - ROUSSET -
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3 //*----------------------------------------------------------------------------
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4 //* The software is delivered "AS IS" without warranty or condition of any
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5 //* kind, either express, implied or statutory. This includes without
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6 //* limitation any warranty or condition with respect to merchantability or
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7 //* fitness for any particular purpose, or against the infringements of
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8 //* intellectual property rights of others.
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9 //*-----------------------------------------------------------------------------
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10 //* File Name : tc.h
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11 //* Object : Timer Counter Header File
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13 //* 1.0 01/04/00 JCZ : Creation
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14 //* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT,
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15 //* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT
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16 //*-----------------------------------------------------------------------------
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21 //#include "periph/stdc/std_c.h"
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22 //#include "periph/pio/lib_pio.h"
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24 /*-------------------------------------------*/
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25 /* Timer User Interface Structure Definition */
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26 /*-------------------------------------------*/
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30 at91_reg TC_CCR ; /* Control Register */
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31 at91_reg TC_CMR ; /* Mode Register */
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32 at91_reg Reserved0 ;
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33 at91_reg Reserved1 ;
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34 at91_reg TC_CV ; /* Counter value */
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35 at91_reg TC_RA ; /* Register A */
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36 at91_reg TC_RB ; /* Register B */
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37 at91_reg TC_RC ; /* Register C */
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38 at91_reg TC_SR ; /* Status Register */
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39 at91_reg TC_IER ; /* Interrupt Enable Register */
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40 at91_reg TC_IDR ; /* Interrupt Disable Register */
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41 at91_reg TC_IMR ; /* Interrupt Mask Register */
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42 at91_reg Reserved2 ;
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43 at91_reg Reserved3 ;
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44 at91_reg Reserved4 ;
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45 at91_reg Reserved5 ;
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48 #define NB_TC_CHANNEL 3
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52 StructTC TC[NB_TC_CHANNEL] ;
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53 at91_reg TC_BCR ; /* Block Control Register */
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54 at91_reg TC_BMR ; /* Block Mode Register */
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57 /*--------------------------------------------------------*/
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58 /* TC_CCR: Timer Counter Control Register Bits Definition */
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59 /*--------------------------------------------------------*/
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60 #define TC_CLKEN 0x1
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61 #define TC_CLKDIS 0x2
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62 #define TC_SWTRG 0x4
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64 /*---------------------------------------------------------------*/
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65 /* TC_CMR: Timer Counter Channel Mode Register Bits Definition */
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66 /*---------------------------------------------------------------*/
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68 /*-----------------*/
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69 /* Clock Selection */
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70 /*-----------------*/
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72 #define TC_CLKS_MCK2 0x0
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73 #define TC_CLKS_MCK8 0x1
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74 #define TC_CLKS_MCK32 0x2
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75 #define TC_CLKS_MCK128 0x3
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76 #define TC_CLKS_MCK1024 0x4
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78 #define TC_CLKS_SLCK 0x4
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80 #define TC_CLKS_XC0 0x5
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81 #define TC_CLKS_XC1 0x6
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82 #define TC_CLKS_XC2 0x7
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85 /*-----------------*/
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86 /* Clock Inversion */
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87 /*-----------------*/
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90 /*------------------------*/
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91 /* Burst Signal Selection */
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92 /*------------------------*/
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93 #define TC_BURST 0x30
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94 #define TC_BURST_NONE 0x0
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95 #define TC_BUSRT_XC0 0x10
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96 #define TC_BURST_XC1 0x20
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97 #define TC_BURST_XC2 0x30
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99 /*------------------------------------------------------*/
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100 /* Capture Mode : Counter Clock Stopped with RB Loading */
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101 /*------------------------------------------------------*/
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102 #define TC_LDBSTOP 0x40
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104 /*-------------------------------------------------------*/
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105 /* Waveform Mode : Counter Clock Stopped with RC Compare */
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106 /*-------------------------------------------------------*/
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107 #define TC_CPCSTOP 0x40
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109 /*-------------------------------------------------------*/
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110 /* Capture Mode : Counter Clock Disabled with RB Loading */
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111 /*--------------------------------------------------------*/
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112 #define TC_LDBDIS 0x80
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114 /*--------------------------------------------------------*/
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115 /* Waveform Mode : Counter Clock Disabled with RC Compare */
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116 /*--------------------------------------------------------*/
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117 #define TC_CPCDIS 0x80
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119 /*------------------------------------------------*/
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120 /* Capture Mode : External Trigger Edge Selection */
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121 /*------------------------------------------------*/
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122 #define TC_ETRGEDG 0x300
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123 #define TC_ETRGEDG_EDGE_NONE 0x0
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124 #define TC_ETRGEDG_RISING_EDGE 0x100
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125 #define TC_ETRGEDG_FALLING_EDGE 0x200
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126 #define TC_ETRGEDG_BOTH_EDGE 0x300
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128 /*-----------------------------------------------*/
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129 /* Waveform Mode : External Event Edge Selection */
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130 /*-----------------------------------------------*/
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131 #define TC_EEVTEDG 0x300
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132 #define TC_EEVTEDG_EDGE_NONE 0x0
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133 #define TC_EEVTEDG_RISING_EDGE 0x100
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134 #define TC_EEVTEDG_FALLING_EDGE 0x200
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135 #define TC_EEVTEDG_BOTH_EDGE 0x300
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137 /*--------------------------------------------------------*/
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138 /* Capture Mode : TIOA or TIOB External Trigger Selection */
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139 /*--------------------------------------------------------*/
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140 #define TC_ABETRG 0x400
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141 #define TC_ABETRG_TIOB 0x0
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142 #define TC_ABETRG_TIOA 0x400
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144 /*------------------------------------------*/
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145 /* Waveform Mode : External Event Selection */
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146 /*------------------------------------------*/
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147 #define TC_EEVT 0xC00
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148 #define TC_EEVT_TIOB 0x0
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149 #define TC_EEVT_XC0 0x400
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150 #define TC_EEVT_XC1 0x800
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151 #define TC_EEVT_XC2 0xC00
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153 /*--------------------------------------------------*/
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154 /* Waveform Mode : Enable Trigger on External Event */
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155 /*--------------------------------------------------*/
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156 #define TC_ENETRG 0x1000
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158 /*----------------------------------*/
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159 /* RC Compare Enable Trigger Enable */
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160 /*----------------------------------*/
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161 #define TC_CPCTRG 0x4000
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163 /*----------------*/
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164 /* Mode Selection */
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165 /*----------------*/
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166 #define TC_WAVE 0x8000
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167 #define TC_CAPT 0x0
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169 /*-------------------------------------*/
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170 /* Capture Mode : RA Loading Selection */
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171 /*-------------------------------------*/
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172 #define TC_LDRA 0x30000
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173 #define TC_LDRA_EDGE_NONE 0x0
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174 #define TC_LDRA_RISING_EDGE 0x10000
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175 #define TC_LDRA_FALLING_EDGE 0x20000
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176 #define TC_LDRA_BOTH_EDGE 0x30000
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178 /*-------------------------------------------*/
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179 /* Waveform Mode : RA Compare Effect on TIOA */
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180 /*-------------------------------------------*/
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181 #define TC_ACPA 0x30000
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182 #define TC_ACPA_OUTPUT_NONE 0x0
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183 #define TC_ACPA_SET_OUTPUT 0x10000
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184 #define TC_ACPA_CLEAR_OUTPUT 0x20000
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185 #define TC_ACPA_TOGGLE_OUTPUT 0x30000
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187 /*-------------------------------------*/
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188 /* Capture Mode : RB Loading Selection */
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189 /*-------------------------------------*/
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190 #define TC_LDRB 0xC0000
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191 #define TC_LDRB_EDGE_NONE 0x0
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192 #define TC_LDRB_RISING_EDGE 0x40000
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193 #define TC_LDRB_FALLING_EDGE 0x80000
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194 #define TC_LDRB_BOTH_EDGE 0xC0000
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196 /*-------------------------------------------*/
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197 /* Waveform Mode : RC Compare Effect on TIOA */
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198 /*-------------------------------------------*/
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199 #define TC_ACPC 0xC0000
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200 #define TC_ACPC_OUTPUT_NONE 0x0
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201 #define TC_ACPC_SET_OUTPUT 0x40000
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202 #define TC_ACPC_CLEAR_OUTPUT 0x80000
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203 #define TC_ACPC_TOGGLE_OUTPUT 0xC0000
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205 /*-----------------------------------------------*/
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206 /* Waveform Mode : External Event Effect on TIOA */
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207 /*-----------------------------------------------*/
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208 #define TC_AEEVT 0x300000
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209 #define TC_AEEVT_OUTPUT_NONE 0x0
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210 #define TC_AEEVT_SET_OUTPUT 0x100000
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211 #define TC_AEEVT_CLEAR_OUTPUT 0x200000
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212 #define TC_AEEVT_TOGGLE_OUTPUT 0x300000
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214 /*-------------------------------------------------*/
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215 /* Waveform Mode : Software Trigger Effect on TIOA */
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216 /*-------------------------------------------------*/
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217 #define TC_ASWTRG 0xC00000
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218 #define TC_ASWTRG_OUTPUT_NONE 0x0
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219 #define TC_ASWTRG_SET_OUTPUT 0x400000
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220 #define TC_ASWTRG_CLEAR_OUTPUT 0x800000
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221 #define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000
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223 /*-------------------------------------------*/
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224 /* Waveform Mode : RB Compare Effect on TIOB */
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225 /*-------------------------------------------*/
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226 #define TC_BCPB 0x1000000
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227 #define TC_BCPB_OUTPUT_NONE 0x0
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228 #define TC_BCPB_SET_OUTPUT 0x1000000
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229 #define TC_BCPB_CLEAR_OUTPUT 0x2000000
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230 #define TC_BCPB_TOGGLE_OUTPUT 0x3000000
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232 /*-------------------------------------------*/
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233 /* Waveform Mode : RC Compare Effect on TIOB */
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234 /*-------------------------------------------*/
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235 #define TC_BCPC 0xC000000
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236 #define TC_BCPC_OUTPUT_NONE 0x0
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237 #define TC_BCPC_SET_OUTPUT 0x4000000
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238 #define TC_BCPC_CLEAR_OUTPUT 0x8000000
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239 #define TC_BCPC_TOGGLE_OUTPUT 0xC000000
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241 /*-----------------------------------------------*/
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242 /* Waveform Mode : External Event Effect on TIOB */
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243 /*-----------------------------------------------*/
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244 #define TC_BEEVT 0x30000000 //* bit 29-28
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245 #define TC_BEEVT_OUTPUT_NONE 0x0
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246 #define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01
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247 #define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10
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248 #define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11
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250 /*- -----------------------------------------------*/
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251 /* Waveform Mode : Software Trigger Effect on TIOB */
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252 /*-------------------------------------------------*/
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253 #define TC_BSWTRG 0xC0000000
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254 #define TC_BSWTRG_OUTPUT_NONE 0x0
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255 #define TC_BSWTRG_SET_OUTPUT 0x40000000
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256 #define TC_BSWTRG_CLEAR_OUTPUT 0x80000000
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257 #define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000
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259 /*------------------------------------------------------*/
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260 /* TC_SR: Timer Counter Status Register Bits Definition */
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261 /*------------------------------------------------------*/
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262 #define TC_COVFS 0x1 /* Counter Overflow Status */
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263 #define TC_LOVRS 0x2 /* Load Overrun Status */
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264 #define TC_CPAS 0x4 /* RA Compare Status */
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265 #define TC_CPBS 0x8 /* RB Compare Status */
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266 #define TC_CPCS 0x10 /* RC Compare Status */
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267 #define TC_LDRAS 0x20 /* RA Loading Status */
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268 #define TC_LDRBS 0x40 /* RB Loading Status */
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269 #define TC_ETRGS 0x80 /* External Trigger Status */
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270 #define TC_CLKSTA 0x10000 /* Clock Status */
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271 #define TC_MTIOA 0x20000 /* TIOA Mirror */
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272 #define TC_MTIOB 0x40000 /* TIOB Status */
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274 /*--------------------------------------------------------------*/
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275 /* TC_BCR: Timer Counter Block Control Register Bits Definition */
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276 /*--------------------------------------------------------------*/
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277 #define TC_SYNC 0x1 /* Synchronisation Trigger */
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279 /*------------------------------------------------------------*/
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280 /* TC_BMR: Timer Counter Block Mode Register Bits Definition */
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281 /*------------------------------------------------------------*/
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282 #define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */
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283 #define TC_TCLK0XC0 0x0
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284 #define TC_NONEXC0 0x1
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285 #define TC_TIOA1XC0 0x2
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286 #define TC_TIOA2XC0 0x3
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288 #define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */
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289 #define TC_TCLK1XC1 0x0
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290 #define TC_NONEXC1 0x4
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291 #define TC_TIOA0XC1 0x8
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292 #define TC_TIOA2XC1 0xC
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294 #define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */
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295 #define TC_TCLK2XC2 0x0
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296 #define TC_NONEXC2 0x10
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297 #define TC_TIOA0XC2 0x20
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298 #define TC_TIOA1XC2 0x30
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