1 //*----------------------------------------------------------------------------
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2 //* ATMEL Microcontroller Software Support - ROUSSET -
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3 //*----------------------------------------------------------------------------
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4 //* The software is delivered "AS IS" without warranty or condition of any
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5 //* kind, either express, implied or statutory. This includes without
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6 //* limitation any warranty or condition with respect to merchantability or
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7 //* fitness for any particular purpose, or against the infringements of
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8 //* intellectual property rights of others.
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9 //*-----------------------------------------------------------------------------
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10 //* File Name : usart.h
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11 //* Object : USART Header File.
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13 //* 1.0 01/04/00 JCZ : Creation
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14 //*----------------------------------------------------------------------------
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19 //#include "periph/stdc/std_c.h"
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20 //#include "periph/pio/lib_pio.h"
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22 /*-------------------------------------------*/
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23 /* USART User Interface Structure Definition */
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24 /*-------------------------------------------*/
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28 at91_reg US_CR ; /* Control Register */
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29 at91_reg US_MR ; /* Mode Register */
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30 at91_reg US_IER ; /* Interrupt Enable Register */
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31 at91_reg US_IDR ; /* Interrupt Disable Register */
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32 at91_reg US_IMR ; /* Interrupt Mask Register */
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33 at91_reg US_CSR ; /* Channel Status Register */
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34 at91_reg US_RHR ; /* Receive Holding Register */
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35 at91_reg US_THR ; /* Transmit Holding Register */
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36 at91_reg US_BRGR ; /* Baud Rate Generator Register */
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37 at91_reg US_RTOR ; /* Receiver Timeout Register */
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38 at91_reg US_TTGR ; /* Transmitter Time-guard Register */
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40 at91_reg US_RPR ; /* Receiver Pointer Register */
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41 at91_reg US_RCR ; /* Receiver Counter Register */
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42 at91_reg US_TPR ; /* Transmitter Pointer Register */
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43 at91_reg US_TCR ; /* Transmitter Counter Register */
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46 /*--------------------------*/
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47 /* US_CR : Control Register */
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48 /*--------------------------*/
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50 #define US_RSTRX 0x0004 /* Reset Receiver */
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51 #define US_RSTTX 0x0008 /* Reset Transmitter */
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52 #define US_RXEN 0x0010 /* Receiver Enable */
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53 #define US_RXDIS 0x0020 /* Receiver Disable */
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54 #define US_TXEN 0x0040 /* Transmitter Enable */
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55 #define US_TXDIS 0x0080 /* Transmitter Disable */
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56 #define US_RSTSTA 0x0100 /* Reset Status Bits */
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57 #define US_STTBRK 0x0200 /* Start Break */
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58 #define US_STPBRK 0x0400 /* Stop Break */
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59 #define US_STTTO 0x0800 /* Start Time-out */
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60 #define US_SENDA 0x1000 /* Send Address */
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62 /*-----------------------*/
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63 /* US_MR : Mode Register */
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64 /*-----------------------*/
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66 #define US_CLKS 0x0030 /* Clock Selection */
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67 #define US_CLKS_MCK 0x00 /* Master Clock */
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68 #define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */
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69 #define US_CLKS_SCK 0x20 /* External Clock */
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70 #define US_CLKS_SLCK 0x30 /* Slow Clock */
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72 #define US_CHRL 0x00C0 /* Byte Length */
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73 #define US_CHRL_5 0x00 /* 5 bits */
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74 #define US_CHRL_6 0x40 /* 6 bits */
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75 #define US_CHRL_7 0x80 /* 7 bits */
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76 #define US_CHRL_8 0xC0 /* 8 bits */
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78 #define US_SYNC 0x0100 /* Synchronous Mode Enable */
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80 #define US_PAR 0x0E00 /* Parity Mode */
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81 #define US_PAR_EVEN 0x00 /* Even Parity */
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82 #define US_PAR_ODD 0x200 /* Odd Parity */
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83 #define US_PAR_SPACE 0x400 /* Space Parity to 0 */
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84 #define US_PAR_MARK 0x600 /* Marked Parity to 1 */
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85 #define US_PAR_NO 0x800 /* No Parity */
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86 #define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */
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88 #define US_NBSTOP 0x3000 /* Stop Bit Number */
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89 #define US_NBSTOP_1 0x0000 /* 1 Stop Bit */
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90 #define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */
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91 #define US_NBSTOP_2 0x2000 /* 2 Stop Bits */
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93 #define US_CHMODE 0xC000 /* Channel Mode */
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94 #define US_CHMODE_NORMAL 0x0000 /* Normal Mode */
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95 #define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */
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96 #define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */
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97 #define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */
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99 #define US_MODE9 0x20000 /* 9 Bit Mode */
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101 #define US_CLKO 0x40000 /* Baud Rate Output Enable */
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103 /* Mode Register model */
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105 /* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
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106 #define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
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112 /* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
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113 #define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \
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119 /* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
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120 #define US_SYNC_MODE ( US_SYNC + \
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121 US_CHMODE_NORMAL + \
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127 /* SCK used Label */
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128 #define SCK_USED (US_CLKO | US_CLKS_SCK)
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130 /*---------------------------------------------------------------*/
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131 /* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */
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132 /*---------------------------------------------------------------*/
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134 #define US_RXRDY 0x1 /* Receiver Ready */
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135 #define US_TXRDY 0x2 /* Transmitter Ready */
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136 #define US_RXBRK 0x4 /* Receiver Break */
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137 #define US_ENDRX 0x8 /* End of Receiver PDC Transfer */
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138 #define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */
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139 #define US_OVRE 0x20 /* Overrun Error */
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140 #define US_FRAME 0x40 /* Framing Error */
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141 #define US_PARE 0x80 /* Parity Error */
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142 #define US_TIMEOUT 0x100 /* Receiver Timeout */
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143 #define US_TXEMPTY 0x200 /* Transmitter Empty */
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145 #define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)
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146 #define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)
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147 #define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
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151 #endif /* usart_h */
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