1 ;* ----------------------------------------------------------------------------
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2 ;* ATMEL Microcontroller Software Support - ROUSSET -
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3 ;* ----------------------------------------------------------------------------
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4 ;* Copyright (c) 2006, Atmel Corporation
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6 ;* All rights reserved.
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8 ;* Redistribution and use in source and binary forms, with or without
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9 ;* modification, are permitted provided that the following conditions are met:
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11 ;* - Redistributions of source code must retain the above copyright notice,
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12 ;* this list of conditions and the disclaimer below.
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14 ;* - Redistributions in binary form must reproduce the above copyright notice,
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15 ;* this list of conditions and the disclaimer below in the documentation and/or
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16 ;* other materials provided with the distribution.
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18 ;* Atmel's name may not be used to endorse or promote products derived from
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19 ;* this software without specific prior written permission.
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21 ;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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22 ;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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23 ;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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24 ;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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25 ;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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26 ;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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27 ;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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28 ;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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29 ;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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30 ;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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31 ;* ----------------------------------------------------------------------------
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33 ;------------------------------------------------------------------------------
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34 ; Include your AT91 Library files
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35 ;------------------------------------------------------------------------------
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36 #include "AT91SAM7X256_inc.h"
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37 ;------------------------------------------------------------------------------
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39 #define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE)
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40 #define IRQ_STACK_SIZE 200
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41 ; 3 words to be saved per interrupt priority level
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43 ; Mode, correspords to bits 0-5 in CPSR
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44 MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
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45 USR_MODE DEFINE 0x10 ; User mode
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46 FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
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47 IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
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48 SVC_MODE DEFINE 0x13 ; Supervisor mode
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49 ABT_MODE DEFINE 0x17 ; Abort mode
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50 UND_MODE DEFINE 0x1B ; Undefined Instruction mode
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51 SYS_MODE DEFINE 0x1F ; System mode
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56 ;------------------------------------------------------------------------------
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59 ; Normally, segment INTVEC is linked at address 0.
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60 ; For debugging purposes, INTVEC may be placed at other addresses.
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61 ; A debugger that honors the entry point will start the
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62 ; program in a normal way even if INTVEC is not at address 0.
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63 ;------------------------------------------------------------------------------
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64 SECTION .intvec:CODE:NOROOT(2)
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66 PUBLIC __iar_program_start
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67 EXTERN vPortYieldProcessor
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71 ldr pc,[pc,#+24] ;; Reset
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73 ldr pc,[pc,#+24] ;; Undefined instructions
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75 ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)
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77 ldr pc,[pc,#+24] ;; Prefetch abort
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79 ldr pc,[pc,#+24] ;; Data abort
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80 DC32 0xFFFFFFFF ;; RESERVED
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82 LDR PC, [PC, #-0xF20]
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84 ldr pc,[pc,#+24] ;; FIQ
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86 DC32 __iar_program_start
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88 DC32 vPortYieldProcessor
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89 DC32 __prefetch_handler
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92 DC32 IRQ_Handler_Entry
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93 DC32 FIQ_Handler_Entry
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95 ;------------------------------------------------------------------------------
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96 ;- Manage exception: The exception must be ensure in ARM mode
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97 ;------------------------------------------------------------------------------
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98 SECTION text:CODE:NOROOT(2)
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100 ;------------------------------------------------------------------------------
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101 ;- Function : FIQ_Handler_Entry
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102 ;- Treatments : FIQ Controller Interrupt Handler.
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103 ;- R8 is initialize in Cstartup
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104 ;- Called Functions : None only by FIQ
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105 ;------------------------------------------------------------------------------
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108 ;- Switch in SVC/User Mode to allow User Stack access for C code
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109 ; because the FIQ is not yet acknowledged
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111 ;- Save and r0 in FIQ_Register
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113 ldr r0 , [r8, #AIC_FVR]
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114 msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
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115 ;- Save scratch/used registers and LR in User Stack
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116 stmfd sp!, { r1-r3, r12, lr}
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118 ;- Branch to the routine pointed by the AIC_FVR
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122 ;- Restore scratch/used registers and LR from User Stack
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123 ldmia sp!, { r1-r3, r12, lr}
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125 ;- Leave Interrupts disabled and switch back in FIQ mode
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126 msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE
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128 ;- Restore the R0 ARM_MODE_SVC register
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131 ;- Restore the Program Counter using the LR_fiq directly in the PC
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133 ;------------------------------------------------------------------------------
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134 ;- Function : IRQ_Handler_Entry
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135 ;- Treatments : IRQ Controller Interrupt Handler.
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136 ;- Called Functions : AIC_IVR[interrupt]
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137 ;------------------------------------------------------------------------------
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139 ;-------------------------
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140 ;- Manage Exception Entry
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141 ;-------------------------
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142 ;- Adjust and save LR_irq in IRQ stack
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146 ;- Save r0 and SPSR (need to be saved for nested interrupt)
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148 stmfd sp!, {r0,r14}
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150 ;- Write in the IVR to support Protect Mode
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151 ;- No effect in Normal Mode
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152 ;- De-assert the NIRQ and clear the source in Protect Mode
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153 ldr r14, =AT91C_BASE_AIC
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154 ldr r0 , [r14, #AIC_IVR]
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155 str r14, [r14, #AIC_IVR]
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157 ;- Enable Interrupt and Switch in Supervisor Mode
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158 msr CPSR_c, #SVC_MODE
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160 ;- Save scratch/used registers and LR in User Stack
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161 stmfd sp!, { r1-r3, r12, r14}
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163 ;----------------------------------------------
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164 ;- Branch to the routine pointed by the AIC_IVR
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165 ;----------------------------------------------
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169 ;----------------------------------------------
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170 ;- Manage Exception Exit
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171 ;----------------------------------------------
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172 ;- Restore scratch/used registers and LR from User Stack
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173 ldmia sp!, { r1-r3, r12, r14}
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175 ;- Disable Interrupt and switch back in IRQ mode
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176 msr CPSR_c, #I_BIT | IRQ_MODE
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178 ;- Mark the End of Interrupt on the AIC
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179 ldr r14, =AT91C_BASE_AIC
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180 str r14, [r14, #AIC_EOICR]
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182 ;- Restore SPSR_irq and r0 from IRQ stack
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183 ldmia sp!, {r0,r14}
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186 ;- Restore adjusted LR_irq from IRQ stack directly in the PC
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189 ;------------------------------------------------------------------------------
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190 ;- Exception Vectors
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191 ;------------------------------------------------------------------------------
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192 PUBLIC AT91F_Default_FIQ_handler
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193 PUBLIC AT91F_Default_IRQ_handler
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194 PUBLIC AT91F_Spurious_handler
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196 ARM ; Always ARM mode after exeption
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198 AT91F_Default_FIQ_handler
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199 b AT91F_Default_FIQ_handler
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201 AT91F_Default_IRQ_handler
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202 b AT91F_Default_IRQ_handler
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204 AT91F_Spurious_handler
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205 b AT91F_Spurious_handler
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208 ;------------------------------------------------------------------------------
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211 ;------------------------------------------------------------------------------
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213 SECTION FIQ_STACK:DATA:NOROOT(3)
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214 SECTION IRQ_STACK:DATA:NOROOT(3)
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215 SECTION SVC_STACK:DATA:NOROOT(3)
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216 SECTION ABT_STACK:DATA:NOROOT(3)
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217 SECTION UND_STACK:DATA:NOROOT(3)
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218 SECTION CSTACK:DATA:NOROOT(3)
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219 SECTION text:CODE:NOROOT(2)
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222 PUBLIC __iar_program_start
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223 EXTERN AT91F_LowLevelInit
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226 __iar_program_start:
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228 ;------------------------------------------------------------------------------
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229 ;- Low level Init is performed in a C function: AT91F_LowLevelInit
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230 ;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
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231 ;------------------------------------------------------------------------------
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233 ;- Retrieve end of RAM address
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235 ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution
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236 ldr r0,=AT91F_LowLevelInit
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238 bx r0 ;- Branch on C function (with interworking)
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240 ; Initialize the stack pointers.
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241 ; The pattern below can be used for any of the exception stacks:
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242 ; FIQ, IRQ, SVC, ABT, UND, SYS.
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243 ; The USR mode uses the same stack as SYS.
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244 ; The stack segments must be defined in the linker command file,
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245 ; and be declared above.
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247 mrs r0,cpsr ; Original PSR value
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248 bic r0,r0,#MODE_BITS ; Clear the mode bits
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249 orr r0,r0,#SVC_MODE ; Set SVC mode bits
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250 msr cpsr_c,r0 ; Change the mode
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251 ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
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253 bic r0,r0,#MODE_BITS ; Clear the mode bits
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254 orr r0,r0,#UND_MODE ; Set UND mode bits
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255 msr cpsr_c,r0 ; Change the mode
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256 ldr sp,=SFE(UND_STACK) ; End of UND_STACK
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258 bic r0,r0,#MODE_BITS ; Clear the mode bits
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259 orr r0,r0,#ABT_MODE ; Set ABT mode bits
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260 msr cpsr_c,r0 ; Change the mode
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261 ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
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263 bic r0,r0,#MODE_BITS ; Clear the mode bits
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264 orr r0,r0,#FIQ_MODE ; Set FIQ mode bits
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265 msr cpsr_c,r0 ; Change the mode
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266 ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
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267 ;- Init the FIQ register
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268 ldr r8, =AT91C_BASE_AIC
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270 bic r0,r0,#MODE_BITS ; Clear the mode bits
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271 orr r0,r0,#IRQ_MODE ; Set IRQ mode bits
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272 msr cpsr_c,r0 ; Change the mode
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273 ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
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275 bic r0,r0,#MODE_BITS ; Clear the mode bits
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276 orr r0,r0,#SYS_MODE ; Set System mode bits
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277 msr cpsr_c,r0 ; Change the mode
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278 ldr sp,=SFE(CSTACK) ; End of CSTACK
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282 ; Enable the VFP coprocessor.
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283 mov r0, #0x40000000 ; Set EN bit in VFP
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284 fmxr fpexc, r0 ; FPEXC, clear others.
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286 ; Disable underflow exceptions by setting flush to zero mode.
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287 ; For full IEEE 754 underflow compliance this code should be removed
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288 ; and the appropriate exception handler installed.
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289 mov r0, #0x01000000 ; Set FZ bit in VFP
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290 fmxr fpscr, r0 ; FPSCR, clear others.
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293 ; Add more initialization here
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294 msr CPSR_c,#I_BIT | F_BIT | SVC_MODE
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297 ; Continue to ?main for more IAR specific system startup
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302 END ;- Terminates the assembly of the last module in a file
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