git.sur5r.net Git - freertos/blob - Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac

   1 // ---------------------------------------------------------\r
   2 //   ATMEL Microcontroller Software Support  -  ROUSSET  -\r
   3 // ---------------------------------------------------------\r
   4 // The software is delivered "AS IS" without warranty or \r
   5 // condition of any  kind, either express, implied or \r
   6 // statutory. This includes without limitation any warranty \r
   7 // or condition with respect to merchantability or fitness \r
   8 // for any particular purpose, or against the infringements of\r
   9 // intellectual property rights of others.\r
  10 // ---------------------------------------------------------\r
  11 //  File: SAM7.mac\r
  12 //\r
  13 //  User setup file for CSPY debugger to simulate interrupt\r
  14 //  driven Fibonacchi data input. \r
  15 //  1.1 16/Jun/04 JPP    : Creation\r
  16 //\r
  17 //  $Revision: 1.3 $\r
  18 //\r
  19 // ---------------------------------------------------------\r
  20 \r
  21 __var i;\r
  22 __var pt;\r
  23 \r
  24 execUserPreload()\r
  25 {\r
  26 //*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
  27      CheckRemap();\r
  28 //*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
  29     i=__readMemory32(0xFFFFF240,"Memory");\r
  30     __message " ---------------------------------------- Chip ID   0x",i:%X;  \r
  31     i=__readMemory32(0xFFFFF244,"Memory");\r
  32     __message " ---------------------------------------- Extention 0x",i:%X;  \r
  33 //* Get the chip status\r
  34 \r
  35 //* Init AIC\r
  36    AIC();\r
  37 //*  Watchdog Disable\r
  38    Watchdog();\r
  39 \r
  40 }\r
  41 \r
  42 \r
  43 //-----------------------------------------------------------------------------\r
  44 // Watchdog\r
  45 //-------------------------------\r
  46 // Normally, the Watchdog is enable at the reset for load it's preferable to\r
  47 // Disable.\r
  48 //-----------------------------------------------------------------------------\r
  49 Watchdog()\r
  50 {\r
  51 //* Watchdog Disable\r
  52 //      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;\r
  53    __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
  54    __message "------------------------------- Watchdog Disable ----------------------------------------";  \r
  55 }\r
  56 \r
  57 \r
  58 //-----------------------------------------------------------------------------\r
  59 // Check Remap\r
  60 //-------------\r
  61 //-----------------------------------------------------------------------------\r
  62 CheckRemap()\r
  63 {\r
  64 //* Read the value at 0x0\r
  65     i=__readMemory32(0x00000000,"Memory");\r
  66     i=i+1;\r
  67     __writeMemory32(i,0x00,"Memory");\r
  68     pt=__readMemory32(0x00000000,"Memory");\r
  69     \r
  70  if (i == pt)  \r
  71  {\r
  72    __message "------------------------------- The Remap is done ----------------------------------------";  \r
  73 //*   Toggel RESET The remap\r
  74     __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
  75    \r
  76  } else {  \r
  77    __message "------------------------------- The Remap is NOT -----------------------------------------";  \r
  78  }\r
  79 \r
  80 }\r
  81 \r
  82 \r
  83 execUserSetup()\r
  84 {\r
  85  ini();\r
  86      __message "-------------------------------Set PC ----------------------------------------";  \r
  87      __writeMemory32(0x00000000,0xB4,"Register");\r
  88 }\r
  89 \r
  90 \r
  91 \r
  92 //-----------------------------------------------------------------------------\r
  93 // Reset the Interrupt Controller\r
  94 //-------------------------------\r
  95 // Normally, the code is executed only if a reset has been actually performed.\r
  96 // So, the AIC initialization resumes at setting up the default vectors.\r
  97 //-----------------------------------------------------------------------------\r
  98 AIC()\r
  99 {\r
 100 // Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
 101     __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");\r
 102 \r
 103     for (i=0;i < 8; i++)\r
 104     {\r
 105       // AT91C_BASE_AIC->AIC_EOICR\r
 106       pt =  __readMemory32(0xFFFFF130,"Memory");\r
 107     \r
 108     }\r
 109    __message "------------------------------- AIC INIT ---------------------------------------------";  \r
 110 }\r
 111 \r
 112 ini()\r
 113 {\r
 114 __writeMemory32(0x0,0x00,"Register");\r
 115 __writeMemory32(0x0,0x04,"Register");\r
 116 __writeMemory32(0x0,0x08,"Register");\r
 117 __writeMemory32(0x0,0x0C,"Register");\r
 118 __writeMemory32(0x0,0x10,"Register");\r
 119 __writeMemory32(0x0,0x14,"Register");\r
 120 __writeMemory32(0x0,0x18,"Register");\r
 121 __writeMemory32(0x0,0x1C,"Register");\r
 122 __writeMemory32(0x0,0x20,"Register");\r
 123 __writeMemory32(0x0,0x24,"Register");\r
 124 __writeMemory32(0x0,0x28,"Register");\r
 125 __writeMemory32(0x0,0x2C,"Register");\r
 126 __writeMemory32(0x0,0x30,"Register");\r
 127 __writeMemory32(0x0,0x34,"Register");\r
 128 __writeMemory32(0x0,0x38,"Register");\r
 129 \r
 130 // Set CPSR\r
 131 __writeMemory32(0x0D3,0x98,"Register");\r
 132 \r
 133 \r
 134 }\r
 135 \r
 136 RG()\r
 137 {\r
 138 \r
 139 i=__readMemory32(0x00,"Register");   __message "R00 0x",i:%X;  \r
 140 i=__readMemory32(0x04,"Register");   __message "R01 0x",i:%X;  \r
 141 i=__readMemory32(0x08,"Register");   __message "R02 0x",i:%X;  \r
 142 i=__readMemory32(0x0C,"Register");   __message "R03 0x",i:%X;  \r
 143 i=__readMemory32(0x10,"Register");   __message "R04 0x",i:%X;  \r
 144 i=__readMemory32(0x14,"Register");   __message "R05 0x",i:%X;  \r
 145 i=__readMemory32(0x18,"Register");   __message "R06 0x",i:%X;  \r
 146 i=__readMemory32(0x1C,"Register");   __message "R07 0x",i:%X;  \r
 147 i=__readMemory32(0x20,"Register");   __message "R08 0x",i:%X;  \r
 148 i=__readMemory32(0x24,"Register");   __message "R09 0x",i:%X;  \r
 149 i=__readMemory32(0x28,"Register");   __message "R10 0x",i:%X;  \r
 150 i=__readMemory32(0x2C,"Register");   __message "R11 0x",i:%X;  \r
 151 i=__readMemory32(0x30,"Register");   __message "R12 0x",i:%X;  \r
 152 i=__readMemory32(0x34,"Register");   __message "R13 0x",i:%X;  \r
 153 i=__readMemory32(0x38,"Register");   __message "R14 0x",i:%X;  \r
 154 i=__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",i:%X;  \r
 155 i=__readMemory32(0x40,"Register");   __message "R14 SVC 0x",i:%X;  \r
 156 i=__readMemory32(0x44,"Register");   __message "R13 ABT 0x",i:%X;  \r
 157 i=__readMemory32(0x48,"Register");   __message "R14 ABT 0x",i:%X;  \r
 158 i=__readMemory32(0x4C,"Register");   __message "R13 UND 0x",i:%X;  \r
 159 i=__readMemory32(0x50,"Register");   __message "R14 UND 0x",i:%X;  \r
 160 i=__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",i:%X;  \r
 161 i=__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",i:%X;  \r
 162 i=__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",i:%X;  \r
 163 i=__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",i:%X;  \r
 164 i=__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",i:%X;  \r
 165 i=__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",i:%X;  \r
 166 i=__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",i:%X;  \r
 167 i=__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",i:%X;  \r
 168 i=__readMemory32(0x74,"Register");   __message "R14 FIQ0x",i:%X; \r
 169 i=__readMemory32(0x98,"Register");   __message "CPSR     ",i:%X; \r
 170 i=__readMemory32(0x94,"Register");   __message "SPSR     ",i:%X; \r
 171 i=__readMemory32(0x9C,"Register");   __message "SPSR ABT ",i:%X; \r
 172 i=__readMemory32(0xA0,"Register");   __message "SPSR ABT ",i:%X; \r
 173 i=__readMemory32(0xA4,"Register");   __message "SPSR UND ",i:%X; \r
 174 i=__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",i:%X; \r
 175 i=__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",i:%X; \r
 176 \r
 177 i=__readMemory32(0xB4,"Register");   __message "PC 0x",i:%X;  \r
 178 \r
 179 }\r
 180 \r