git.sur5r.net Git - freertos/blob - Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac

   1 // ---------------------------------------------------------\r
   2 //   ATMEL Microcontroller Software Support  -  ROUSSET  -\r
   3 // ---------------------------------------------------------\r
   4 // The software is delivered "AS IS" without warranty or \r
   5 // condition of any  kind, either express, implied or \r
   6 // statutory. This includes without limitation any warranty \r
   7 // or condition with respect to merchantability or fitness \r
   8 // for any particular purpose, or against the infringements of\r
   9 // intellectual property rights of others.\r
  10 // ---------------------------------------------------------\r
  11 //  File: SAM7_RAM.mac\r
  12 //\r
  13 //  User setup file for CSPY debugger to simulate interrupt\r
  14 //  driven Fibonacchi data input. \r
  15 //  1.1 16/Jun/04 JPP    : Creation\r
  16 //  1.2 27/Aug/04 JPP    : PLL setting\r
  17 //\r
  18 //  $Revision: 1.3 $\r
  19 //\r
  20 // ---------------------------------------------------------\r
  21 \r
  22 __var i;\r
  23 __var pt;\r
  24 \r
  25 execUserPreload()\r
  26 {\r
  27 //*  \r
  28      PllSetting();\r
  29 //*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
  30      CheckNoRemap();\r
  31 //*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
  32     i=__readMemory32(0xFFFFF240,"Memory");\r
  33     __message " ---------------------------------------- Chip ID   0x",i:%X;  \r
  34     i=__readMemory32(0xFFFFF244,"Memory");\r
  35     __message " ---------------------------------------- Extention 0x",i:%X;  \r
  36     i=__readMemory32(0xFFFFFF6C,"Memory");\r
  37     __message " ---------------------------------------- Flash Version 0x",i:%X;  \r
  38 //* Get the chip status\r
  39 \r
  40 //* Init AIC\r
  41    AIC();\r
  42 //*  Watchdog Disable\r
  43    Watchdog();\r
  44 }\r
  45 //-----------------------------------------------------------------------------\r
  46 // PllSetting\r
  47 //-------------------------------\r
  48 // Set PLL\r
  49 //-----------------------------------------------------------------------------\r
  50 PllSetting()\r
  51 {\r
  52 // -1- Enabling the Main Oscillator:\r
  53 //*#define AT91C_PMC_MOR   ((AT91_REG *)        0xFFFFFC20) // (PMC) Main Oscillator Register\r
  54 //*#define AT91C_PMC_PLLR  ((AT91_REG *)        0xFFFFFC2C) // (PMC) PLL Register\r
  55 //*#define AT91C_PMC_MCKR  ((AT91_REG *)        0xFFFFFC30) // (PMC) Master Clock Register\r
  56 \r
  57 //*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) |    //0x0000 0600\r
  58 //                          AT91C_CKGR_MOSCEN ));          //0x0000 0001 \r
  59 __writeMemory32(0x00000601,0xFFFFFC20,"Memory");\r
  60 \r
  61 // -2- Wait\r
  62 // -3- Setting PLL and divider:\r
  63 // - div by 5 Fin = 3,6864 =(18,432 / 5)\r
  64 // - Mul 25+1: Fout =   95,8464 =(3,6864 *26)\r
  65 // for 96 MHz the erroe is 0.16%\r
  66 // Field out NOT USED = 0\r
  67 // PLLCOUNT pll startup time esrtimate at : 0.844 ms\r
  68 // PLLCOUNT 28 = 0.000844 /(1/32768)\r
  69 //       pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |       //0x0000 0005\r
  70 //                         (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00\r
  71 //                         (AT91C_CKGR_MUL & (25<<16)));   //0x0019 0000 \r
  72 __writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");\r
  73 // -2- Wait\r
  74 // -5- Selection of Master Clock and Processor Clock\r
  75 // select the PLL clock divided by 2\r
  76 //          pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK |     //0x0000 0003\r
  77 //                           AT91C_PMC_PRES_CLK_2 ;      //0x0000 0004\r
  78 __writeMemory32(0x00000007,0xFFFFFC30,"Memory");        \r
  79 \r
  80    __message "------------------------------- PLL  Enable ----------------------------------------";  \r
  81 }\r
  82 \r
  83 //-----------------------------------------------------------------------------\r
  84 // Watchdog\r
  85 //-------------------------------\r
  86 // Normally, the Watchdog is enable at the reset for load it's preferable to\r
  87 // Disable.\r
  88 //-----------------------------------------------------------------------------\r
  89 Watchdog()\r
  90 {\r
  91 //* Watchdog Disable\r
  92 //      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;\r
  93    __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
  94    __message "------------------------------- Watchdog Disable ----------------------------------------";  \r
  95 }\r
  96 \r
  97 CheckNoRemap()\r
  98 {\r
  99 //* Read the value at 0x0\r
 100     i=__readMemory32(0x00000000,"Memory");\r
 101     i=i+1;\r
 102     __writeMemory32(i,0x00,"Memory");\r
 103     pt=__readMemory32(0x00000000,"Memory");\r
 104     \r
 105  if (i == pt)  \r
 106  {\r
 107    __message "------------------------------- The Remap is done ----------------------------------------";  \r
 108    \r
 109  } else {  \r
 110    __message "------------------------------- The Remap is NOT -----------------------------------------";  \r
 111 //*   Toggel RESET The remap\r
 112     __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
 113  }\r
 114 \r
 115 }\r
 116 \r
 117 execUserSetup()\r
 118 {\r
 119  ini();\r
 120      __message "-------------------------------Set PC ----------------------------------------";  \r
 121      __writeMemory32(0x00000000,0xB4,"Register");\r
 122 }\r
 123 \r
 124 //-----------------------------------------------------------------------------\r
 125 // Reset the Interrupt Controller\r
 126 //-------------------------------\r
 127 // Normally, the code is executed only if a reset has been actually performed.\r
 128 // So, the AIC initialization resumes at setting up the default vectors.\r
 129 //-----------------------------------------------------------------------------\r
 130 AIC()\r
 131 {\r
 132 // Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
 133     __writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");\r
 134 \r
 135     for (i=0;i < 8; i++)\r
 136     {\r
 137       // AT91C_BASE_AIC->AIC_EOICR\r
 138       pt =  __readMemory32(0xFFFFF130,"Memory");\r
 139     \r
 140     }\r
 141    __message "------------------------------- AIC INIT ---------------------------------------------";  \r
 142 }\r
 143 \r
 144 ini()\r
 145 {\r
 146 __writeMemory32(0x0,0x00,"Register");\r
 147 __writeMemory32(0x0,0x04,"Register");\r
 148 __writeMemory32(0x0,0x08,"Register");\r
 149 __writeMemory32(0x0,0x0C,"Register");\r
 150 __writeMemory32(0x0,0x10,"Register");\r
 151 __writeMemory32(0x0,0x14,"Register");\r
 152 __writeMemory32(0x0,0x18,"Register");\r
 153 __writeMemory32(0x0,0x1C,"Register");\r
 154 __writeMemory32(0x0,0x20,"Register");\r
 155 __writeMemory32(0x0,0x24,"Register");\r
 156 __writeMemory32(0x0,0x28,"Register");\r
 157 __writeMemory32(0x0,0x2C,"Register");\r
 158 __writeMemory32(0x0,0x30,"Register");\r
 159 __writeMemory32(0x0,0x34,"Register");\r
 160 __writeMemory32(0x0,0x38,"Register");\r
 161 \r
 162 // Set CPSR\r
 163 __writeMemory32(0x0D3,0x98,"Register");\r
 164 \r
 165 }\r
 166 \r
 167 RG()\r
 168 {\r
 169 \r
 170 i=__readMemory32(0x00,"Register");   __message "R00 0x",i:%X;  \r
 171 i=__readMemory32(0x04,"Register");   __message "R01 0x",i:%X;  \r
 172 i=__readMemory32(0x08,"Register");   __message "R02 0x",i:%X;  \r
 173 i=__readMemory32(0x0C,"Register");   __message "R03 0x",i:%X;  \r
 174 i=__readMemory32(0x10,"Register");   __message "R04 0x",i:%X;  \r
 175 i=__readMemory32(0x14,"Register");   __message "R05 0x",i:%X;  \r
 176 i=__readMemory32(0x18,"Register");   __message "R06 0x",i:%X;  \r
 177 i=__readMemory32(0x1C,"Register");   __message "R07 0x",i:%X;  \r
 178 i=__readMemory32(0x20,"Register");   __message "R08 0x",i:%X;  \r
 179 i=__readMemory32(0x24,"Register");   __message "R09 0x",i:%X;  \r
 180 i=__readMemory32(0x28,"Register");   __message "R10 0x",i:%X;  \r
 181 i=__readMemory32(0x2C,"Register");   __message "R11 0x",i:%X;  \r
 182 i=__readMemory32(0x30,"Register");   __message "R12 0x",i:%X;  \r
 183 i=__readMemory32(0x34,"Register");   __message "R13 0x",i:%X;  \r
 184 i=__readMemory32(0x38,"Register");   __message "R14 0x",i:%X;  \r
 185 i=__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",i:%X;  \r
 186 i=__readMemory32(0x40,"Register");   __message "R14 SVC 0x",i:%X;  \r
 187 i=__readMemory32(0x44,"Register");   __message "R13 ABT 0x",i:%X;  \r
 188 i=__readMemory32(0x48,"Register");   __message "R14 ABT 0x",i:%X;  \r
 189 i=__readMemory32(0x4C,"Register");   __message "R13 UND 0x",i:%X;  \r
 190 i=__readMemory32(0x50,"Register");   __message "R14 UND 0x",i:%X;  \r
 191 i=__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",i:%X;  \r
 192 i=__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",i:%X;  \r
 193 i=__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",i:%X;  \r
 194 i=__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",i:%X;  \r
 195 i=__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",i:%X;  \r
 196 i=__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",i:%X;  \r
 197 i=__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",i:%X;  \r
 198 i=__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",i:%X;  \r
 199 i=__readMemory32(0x74,"Register");   __message "R14 FIQ0x",i:%X; \r
 200 i=__readMemory32(0x98,"Register");   __message "CPSR     ",i:%X; \r
 201 i=__readMemory32(0x94,"Register");   __message "SPSR     ",i:%X; \r
 202 i=__readMemory32(0x9C,"Register");   __message "SPSR ABT ",i:%X; \r
 203 i=__readMemory32(0xA0,"Register");   __message "SPSR ABT ",i:%X; \r
 204 i=__readMemory32(0xA4,"Register");   __message "SPSR UND ",i:%X; \r
 205 i=__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",i:%X; \r
 206 i=__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",i:%X; \r
 207 \r
 208 i=__readMemory32(0xB4,"Register");   __message "PC 0x",i:%X;  \r
 209 \r
 210 }\r
 211 \r