2 FreeRTOS V5.4.2 - Copyright (C) 2009 Real Time Engineers Ltd.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License (version 2) as published by the
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8 Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS without being obliged to provide the
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11 source code for proprietary components outside of the FreeRTOS kernel.
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12 Alternative commercial license and support terms are also available upon
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13 request. See the licensing section of http://www.FreeRTOS.org for full
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16 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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21 You should have received a copy of the GNU General Public License along
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22 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
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23 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 ***************************************************************************
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28 * Looking for a quick start? Then check out the FreeRTOS eBook! *
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29 * See http://www.FreeRTOS.org/Documentation for details *
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31 ***************************************************************************
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35 Please ensure to read the configuration and relevant port sections of the
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36 online documentation.
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38 http://www.FreeRTOS.org - Documentation, latest information, license and
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41 http://www.SafeRTOS.com - A version that is certified for use in safety
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44 http://www.OpenRTOS.com - Commercial support, development, porting,
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45 licensing and training services.
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48 /* Scheduler includes. */
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49 #include "FreeRTOS.h"
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53 /* Demo app includes. */
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54 #include "USBSample.h"
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56 #define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
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58 #define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \
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60 /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \
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61 /* STALLSENT and RX_DATA_BK1 to 1 so the */ \
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62 /* write has no effect. */ \
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63 ( * ( ( unsigned portLONG * ) pulValueNow ) ) |= ( unsigned portLONG ) 0x4f; \
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65 /* Clear the FORCE_STALL and TXPKTRDY bits */ \
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66 /* so the write has no effect. */ \
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67 ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( unsigned portLONG ) 0xffffffcf; \
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69 /* Clear whichever bit we want clear. */ \
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70 ( * ( ( unsigned portLONG * ) pulValueNow ) ) &= ( ~ulBit ); \
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74 /*-----------------------------------------------------------*/
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80 void vUSB_ISR_Wrapper( void ) __attribute__((naked));
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83 * Actual ISR handler. This must be separate from the entry point as the stack
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86 void vUSB_ISR_Handler( void ) __attribute__((noinline));
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88 /*-----------------------------------------------------------*/
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90 /* Array in which the USB interrupt status is passed between the ISR and task. */
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91 static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
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93 /* Queue used to pass messages between the ISR and the task. */
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94 extern xQueueHandle xUSBInterruptQueue;
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96 /*-----------------------------------------------------------*/
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98 void vUSB_ISR_Handler( void )
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100 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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101 static volatile unsigned portLONG ulNextMessage = 0;
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102 xISRStatus *pxMessage;
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103 unsigned portLONG ulTemp, ulRxBytes;
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105 /* To reduce the amount of time spent in this interrupt it would be
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106 possible to defer the majority of this processing to an 'interrupt task',
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107 that is a task that runs at a higher priority than any of the application
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110 /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must*
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111 be all 1's, as in 0x01, 0x03, 0x07, etc. */
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112 pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
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115 /* Take a snapshot of the current USB state for processing at the task
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117 pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
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118 pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
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120 /* Clear the interrupts from the ICR register. The bus end interrupt is
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121 cleared separately as it does not appear in the mask register. */
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122 AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
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124 /* If there are bytes in the FIFO then we have to retrieve them here.
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125 Ideally this would be done at the task level. However we need to clear the
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126 RXSETUP interrupt before leaving the ISR, and this may cause the data in
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127 the FIFO to be overwritten. Also the DIR bit has to be changed before the
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128 RXSETUP bit is cleared (as per the SAM7 manual). */
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129 ulTemp = pxMessage->ulCSR0;
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131 /* Are there any bytes in the FIFO? */
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132 ulRxBytes = ulTemp >> 16;
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133 ulRxBytes &= usbRX_COUNT_MASK;
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135 /* With this minimal implementation we are only interested in receiving
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136 setup bytes on the control end point. */
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137 if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) )
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139 /* Take off 1 for a zero based index. */
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140 while( ulRxBytes > 0 )
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143 pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
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146 /* The direction must be changed first. */
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147 usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) );
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148 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
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151 /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA
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152 registers to clear the interrupts in the CSR register. */
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153 usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );
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154 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
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156 /* Also clear the interrupts in the CSR1 register. */
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157 ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];
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158 usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );
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159 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;
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161 /* The message now contains the entire state and optional data from
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162 the USB interrupt. This can now be posted on the Rx queue ready for
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163 processing at the task level. */
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164 xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, &xHigherPriorityTaskWoken );
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166 /* We may want to switch to the USB task, if this message has made
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167 it the highest priority task that is ready to execute. */
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168 if( xHigherPriorityTaskWoken )
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170 portYIELD_FROM_ISR();
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173 /* Clear the AIC ready for the next interrupt. */
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174 AT91C_BASE_AIC->AIC_EOICR = 0;
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176 /*-----------------------------------------------------------*/
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178 void vUSB_ISR_Wrapper( void )
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180 /* Save the context of the interrupted task. */
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181 portSAVE_CONTEXT();
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183 /* Call the handler itself. This must be a separate function as it uses
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185 __asm volatile ("bl vUSB_ISR_Handler");
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187 /* Restore the context of the task that is going to
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188 execute next. This might not be the same as the originally
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189 interrupted task.*/
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190 portRESTORE_CONTEXT();
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