2 FreeRTOS.org V5.3.0 - Copyright (C) 2003-2009 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify it
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7 under the terms of the GNU General Public License (version 2) as published
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8 by the Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS.org without being obliged to provide
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11 the source code for any proprietary components. Alternative commercial
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12 license and support terms are also available upon request. See the
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13 licensing section of http://www.FreeRTOS.org for full details.
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15 FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
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16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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20 You should have received a copy of the GNU General Public License along
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21 with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
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22 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 ***************************************************************************
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27 * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
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29 * This is a concise, step by step, 'hands on' guide that describes both *
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30 * general multitasking concepts and FreeRTOS specifics. It presents and *
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31 * explains numerous examples that are written using the FreeRTOS API. *
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32 * Full source code for all the examples is provided in an accompanying *
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35 ***************************************************************************
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39 Please ensure to read the configuration and relevant port sections of the
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40 online documentation.
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42 http://www.FreeRTOS.org - Documentation, latest information, license and
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45 http://www.SafeRTOS.com - A version that is certified for use in safety
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48 http://www.OpenRTOS.com - Commercial support, development, porting,
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49 licensing and training services.
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52 /* Standard includes. */
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55 /* Scheduler includes. */
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56 #include "FreeRTOS.h"
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60 /* Demo application includes. */
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61 #include "SAM7_EMAC.h"
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66 /* Hardware specific includes. */
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69 #include "AT91SAM7X256.h"
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72 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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73 to use an MII interface. */
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74 #define USE_RMII_INTERFACE 0
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76 /* The buffer addresses written into the descriptors must be aligned so the
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77 last few bits are zero. These bits have special meaning for the EMAC
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78 peripheral and cannot be used as part of the address. */
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79 #define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )
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81 /* Bit used within the address stored in the descriptor to mark the last
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82 descriptor in the array. */
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83 #define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )
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85 /* Bit used within the Tx descriptor status to indicate whether the
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86 descriptor is under the control of the EMAC or the software. */
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87 #define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )
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89 /* A short delay is used to wait for a buffer to become available, should
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90 one not be immediately available when trying to transmit a frame. */
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91 #define emacBUFFER_WAIT_DELAY ( 2 )
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92 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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95 #define emacINTERRUPT_LEVEL ( 5 )
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96 #define emacNO_DELAY ( 0 )
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97 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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98 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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99 #define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )
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100 #define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )
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102 /* The Atmel header file only defines the TX frame length mask. */
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103 #define emacRX_LENGTH_FRAME ( 0xfff )
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105 /* Peripheral setup for the EMAC. */
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106 #define emacPERIPHERAL_A_SETUP ( ( unsigned portLONG ) AT91C_PB2_ETX0 ) | \
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107 ( ( unsigned portLONG ) AT91C_PB12_ETXER ) | \
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108 ( ( unsigned portLONG ) AT91C_PB16_ECOL ) | \
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109 ( ( unsigned portLONG ) AT91C_PB11_ETX3 ) | \
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110 ( ( unsigned portLONG ) AT91C_PB6_ERX1 ) | \
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111 ( ( unsigned portLONG ) AT91C_PB15_ERXDV ) | \
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112 ( ( unsigned portLONG ) AT91C_PB13_ERX2 ) | \
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113 ( ( unsigned portLONG ) AT91C_PB3_ETX1 ) | \
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114 ( ( unsigned portLONG ) AT91C_PB8_EMDC ) | \
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115 ( ( unsigned portLONG ) AT91C_PB5_ERX0 ) | \
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116 ( ( unsigned portLONG ) AT91C_PB14_ERX3 ) | \
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117 ( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV ) | \
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118 ( ( unsigned portLONG ) AT91C_PB1_ETXEN ) | \
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119 ( ( unsigned portLONG ) AT91C_PB10_ETX2 ) | \
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120 ( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK ) | \
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121 ( ( unsigned portLONG ) AT91C_PB9_EMDIO ) | \
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122 ( ( unsigned portLONG ) AT91C_PB7_ERXER ) | \
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123 ( ( unsigned portLONG ) AT91C_PB17_ERXCK );
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125 /*-----------------------------------------------------------*/
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128 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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130 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
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133 * Initialise both the Tx and Rx descriptors used by the EMAC.
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135 static void prvSetupDescriptors(void);
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138 * Write our MAC address into the EMAC. The MAC address is set as one of the
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141 static void prvSetupMACAddress( void );
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144 * Configure the EMAC and AIC for EMAC interrupts.
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146 static void prvSetupEMACInterrupt( void );
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149 * Some initialisation functions taken from the Atmel EMAC sample code.
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151 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
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152 #if USE_RMII_INTERFACE != 1
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153 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
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155 static portBASE_TYPE xGetLinkSpeed( void );
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156 static portBASE_TYPE prvProbePHY( void );
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158 /*-----------------------------------------------------------*/
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160 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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161 comment above the emacADDRESS_MASK definition. */
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162 #pragma data_alignment=8
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163 static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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165 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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166 above the emacADDRESS_MASK definition. */
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167 #pragma data_alignment=8
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168 static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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170 /* Descriptors used to communicate between the program and the EMAC peripheral.
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171 These descriptors hold the locations and state of the Rx and Tx buffers. */
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172 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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173 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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175 /* The IP and Ethernet addresses are read from the uIP setup. */
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176 const portCHAR cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
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177 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
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179 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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180 static xSemaphoreHandle xSemaphore = NULL;
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182 /*-----------------------------------------------------------*/
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184 xSemaphoreHandle xEMACInit( void )
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186 /* Code supplied by Atmel -------------------------------*/
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188 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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189 PHY has internal pull down. */
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190 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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192 #if USE_RMII_INTERFACE != 1
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193 /* PHY has internal pull down : set MII mode. */
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194 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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197 /* Clear PB18 <=> PHY powerdown. */
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198 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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199 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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200 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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202 /* After PHY power up, hardware reset. */
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203 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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204 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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206 /* Wait for hardware reset end. */
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207 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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209 __asm volatile ( "NOP" );
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211 __asm volatile ( "NOP" );
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213 /* Setup the pins. */
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214 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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215 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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217 /* Enable com between EMAC PHY.
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219 Enable management port. */
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220 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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222 /* MDC = MCK/32. */
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223 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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225 /* Wait for PHY auto init end (rather crude delay!). */
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226 vTaskDelay( emacPHY_INIT_DELAY );
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228 /* PHY configuration. */
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229 #if USE_RMII_INTERFACE != 1
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231 unsigned portLONG ulControl;
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233 /* PHY has internal pull down : disable MII isolate. */
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234 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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235 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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236 ulControl &= ~BMCR_ISOLATE;
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237 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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241 /* Disable management port again. */
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242 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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244 #if USE_RMII_INTERFACE != 1
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245 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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246 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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248 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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250 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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253 /* End of code supplied by Atmel ------------------------*/
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255 /* Setup the buffers and descriptors. */
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256 prvSetupDescriptors();
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258 /* Load our MAC address into the EMAC. */
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259 prvSetupMACAddress();
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261 /* Are we connected? */
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262 if( prvProbePHY() )
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264 /* Enable the interrupt! */
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265 portENTER_CRITICAL();
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267 prvSetupEMACInterrupt();
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268 vPassEMACSemaphore( xSemaphore );
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270 portEXIT_CRITICAL();
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275 /*-----------------------------------------------------------*/
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277 portLONG lEMACSend( void )
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279 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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280 portBASE_TYPE xWaitCycles = 0;
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281 portLONG lReturn = pdPASS;
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282 portCHAR *pcBuffer;
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284 /* Is a buffer available? */
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285 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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287 /* There is no room to write the Tx data to the Tx buffer. Wait a
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288 short while, then try again. */
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290 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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298 vTaskDelay( emacBUFFER_WAIT_DELAY );
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302 /* lReturn will only be pdPASS if a buffer is available. */
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303 if( lReturn == pdPASS )
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305 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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306 pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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307 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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309 /* If there is room, also copy in the application data if any. */
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310 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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312 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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316 portENTER_CRITICAL();
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318 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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320 /* Fill out the necessary in the descriptor to get the data sent. */
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321 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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322 | AT91C_LAST_BUFFER
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323 | AT91C_TRANSMIT_WRAP;
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324 uxTxBufferIndex = 0;
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328 /* Fill out the necessary in the descriptor to get the data sent. */
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329 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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330 | AT91C_LAST_BUFFER;
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334 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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336 portEXIT_CRITICAL();
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341 /*-----------------------------------------------------------*/
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343 unsigned portLONG ulEMACPoll( void )
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345 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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346 unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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347 portCHAR *pcSource;
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349 /* Skip any fragments. */
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350 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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352 /* Mark the buffer as free again. */
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353 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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355 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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357 ulNextRxBuffer = 0;
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361 /* Is there a packet ready? */
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363 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
\r
365 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
366 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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368 if( ulSectionLength == 0 )
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370 /* The frame is longer than the buffer pointed to by this
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371 descriptor so copy the entire buffer to uIP - then move onto
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372 the next descriptor to get the rest of the frame. */
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373 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
\r
375 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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376 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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381 /* This is the last section of the frame. Copy the section to
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383 if( ulSectionLength < UIP_BUFSIZE )
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385 /* The section length holds the length of the entire frame.
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386 ulLengthSoFar holds the length of the frame sections already
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387 copied to uIP, so the length of the final section is
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388 ulSectionLength - ulLengthSoFar; */
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389 if( ulSectionLength > ulLengthSoFar )
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391 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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395 /* Is this the last buffer for the frame? If not why? */
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396 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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399 /* Mark the buffer as free again. */
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400 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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402 /* Increment to the next buffer, wrapping if necessary. */
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404 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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406 ulNextRxBuffer = 0;
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410 /* If we obtained data but for some reason did not find the end of the
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411 frame then discard the data as it must contain an error. */
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414 ulSectionLength = 0;
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417 return ulSectionLength;
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419 /*-----------------------------------------------------------*/
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421 static void prvSetupDescriptors(void)
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423 unsigned portBASE_TYPE xIndex;
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424 unsigned portLONG ulAddress;
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426 /* Initialise xRxDescriptors descriptor. */
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427 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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429 /* Calculate the address of the nth buffer within the array. */
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430 ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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432 /* Write the buffer address into the descriptor. The DMA will place
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433 the data at this address when this descriptor is being used. Mask off
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434 the bottom bits of the address as these have special meaning. */
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435 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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438 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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439 to the first buffer. */
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440 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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442 /* Initialise xTxDescriptors. */
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443 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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445 /* Calculate the address of the nth buffer within the array. */
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446 ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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448 /* Write the buffer address into the descriptor. The DMA will read
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449 data from here when the descriptor is being used. */
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450 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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451 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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454 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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455 to the first buffer. */
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456 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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458 /* Tell the EMAC where to find the descriptors. */
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459 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
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460 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
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462 /* Clear all the bits in the receive status register. */
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463 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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465 /* Enable the copy of data into the buffers, ignore broadcasts,
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466 and don't copy FCS. */
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467 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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469 /* Enable Rx and Tx, plus the stats register. */
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470 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
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472 /*-----------------------------------------------------------*/
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474 static void prvSetupMACAddress( void )
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476 /* Must be written SA1L then SA1H. */
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477 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
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478 ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
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479 ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |
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482 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
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485 /*-----------------------------------------------------------*/
\r
487 static void prvSetupEMACInterrupt( void )
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489 /* Create the semaphore used to trigger the EMAC task. */
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490 vSemaphoreCreateBinary( xSemaphore );
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493 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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494 first interrupt occurs. */
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495 xSemaphoreTake( xSemaphore, emacNO_DELAY );
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496 portENTER_CRITICAL();
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498 /* We want to interrupt on Rx events. */
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499 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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501 /* Enable the interrupts in the AIC. */
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502 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
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503 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
505 portEXIT_CRITICAL();
\r
508 /*-----------------------------------------------------------*/
\r
514 * The following functions are initialisation functions taken from the Atmel
\r
515 * EMAC sample code.
\r
518 static portBASE_TYPE prvProbePHY( void )
\r
520 unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
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521 portBASE_TYPE xReturn = pdPASS;
\r
523 /* Code supplied by Atmel (reformatted) -----------------*/
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525 /* Enable management port */
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526 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
527 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
529 /* Read the PHY ID. */
\r
530 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
531 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
536 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
537 0001 stands for Rev. A, etc.
\r
539 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
541 /* Did not expect this ID. */
\r
546 ulStatus = xGetLinkSpeed();
\r
548 if( ulStatus != pdPASS )
\r
554 /* Disable management port */
\r
555 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
557 /* End of code supplied by Atmel ------------------------*/
\r
561 /*-----------------------------------------------------------*/
\r
563 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
\r
565 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
567 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
568 | (2 << 16) | (2 << 28)
\r
569 | ((ucPHYAddress & 0x1f) << 23)
\r
570 | (ucAddress << 18);
\r
572 /* Wait until IDLE bit in Network Status register is cleared. */
\r
573 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
578 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
580 /* End of code supplied by Atmel ------------------------*/
\r
582 /*-----------------------------------------------------------*/
\r
584 #if USE_RMII_INTERFACE != 1
\r
585 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
\r
587 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
589 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
590 | (2 << 16) | (1 << 28)
\r
591 | ((ucPHYAddress & 0x1f) << 23)
\r
592 | (ucAddress << 18))
\r
593 | (ulValue & 0xffff);
\r
595 /* Wait until IDLE bit in Network Status register is cleared */
\r
596 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
601 /* End of code supplied by Atmel ------------------------*/
\r
604 /*-----------------------------------------------------------*/
\r
606 static portBASE_TYPE xGetLinkSpeed( void )
\r
608 unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
610 /* Code supplied by Atmel (reformatted) -----------------*/
\r
612 /* Link status is latched, so read twice to get current value */
\r
613 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
614 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
616 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
622 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
623 if (ulBMCR & BMCR_ANENABLE)
\r
625 /* AutoNegotiation is enabled. */
\r
626 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
628 /* Auto-negotiation in progress. */
\r
632 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
633 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
635 ulSpeed = SPEED_100;
\r
639 ulSpeed = SPEED_10;
\r
642 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
644 ulDuplex = DUPLEX_FULL;
\r
648 ulDuplex = DUPLEX_HALF;
\r
653 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
654 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
657 /* Update the MAC */
\r
658 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
659 if( ulSpeed == SPEED_100 )
\r
661 if( ulDuplex == DUPLEX_FULL )
\r
663 /* 100 Full Duplex */
\r
664 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
668 /* 100 Half Duplex */
\r
669 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
674 if (ulDuplex == DUPLEX_FULL)
\r
676 /* 10 Full Duplex */
\r
677 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
681 /* 10 Half Duplex */
\r
682 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
686 /* End of code supplied by Atmel ------------------------*/
\r