2 FreeRTOS.org V4.7.2 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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28 Please ensure to read the configuration and relevant port sections of the
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29 online documentation.
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31 +++ http://www.FreeRTOS.org +++
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32 Documentation, latest information, license and contact details.
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34 +++ http://www.SafeRTOS.com +++
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35 A version that is certified for use in safety critical systems.
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37 +++ http://www.OpenRTOS.com +++
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38 Commercial support, development, porting, licensing and training services.
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40 ***************************************************************************
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43 /* Standard includes. */
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46 /* Scheduler includes. */
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47 #include "FreeRTOS.h"
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51 /* Demo application includes. */
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52 #include "SAM7_EMAC.h"
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57 /* Hardware specific includes. */
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60 #include "AT91SAM7X256.h"
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63 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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64 to use an MII interface. */
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65 #define USE_RMII_INTERFACE 0
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67 /* The buffer addresses written into the descriptors must be aligned so the
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68 last few bits are zero. These bits have special meaning for the EMAC
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69 peripheral and cannot be used as part of the address. */
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70 #define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )
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72 /* Bit used within the address stored in the descriptor to mark the last
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73 descriptor in the array. */
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74 #define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )
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76 /* Bit used within the Tx descriptor status to indicate whether the
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77 descriptor is under the control of the EMAC or the software. */
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78 #define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )
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80 /* A short delay is used to wait for a buffer to become available, should
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81 one not be immediately available when trying to transmit a frame. */
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82 #define emacBUFFER_WAIT_DELAY ( 2 )
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83 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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86 #define emacINTERRUPT_LEVEL ( 5 )
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87 #define emacNO_DELAY ( 0 )
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88 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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89 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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90 #define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )
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91 #define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )
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93 /* The Atmel header file only defines the TX frame length mask. */
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94 #define emacRX_LENGTH_FRAME ( 0xfff )
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96 /* Peripheral setup for the EMAC. */
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97 #define emacPERIPHERAL_A_SETUP ( ( unsigned portLONG ) AT91C_PB2_ETX0 ) | \
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98 ( ( unsigned portLONG ) AT91C_PB12_ETXER ) | \
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99 ( ( unsigned portLONG ) AT91C_PB16_ECOL ) | \
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100 ( ( unsigned portLONG ) AT91C_PB11_ETX3 ) | \
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101 ( ( unsigned portLONG ) AT91C_PB6_ERX1 ) | \
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102 ( ( unsigned portLONG ) AT91C_PB15_ERXDV ) | \
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103 ( ( unsigned portLONG ) AT91C_PB13_ERX2 ) | \
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104 ( ( unsigned portLONG ) AT91C_PB3_ETX1 ) | \
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105 ( ( unsigned portLONG ) AT91C_PB8_EMDC ) | \
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106 ( ( unsigned portLONG ) AT91C_PB5_ERX0 ) | \
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107 ( ( unsigned portLONG ) AT91C_PB14_ERX3 ) | \
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108 ( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV ) | \
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109 ( ( unsigned portLONG ) AT91C_PB1_ETXEN ) | \
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110 ( ( unsigned portLONG ) AT91C_PB10_ETX2 ) | \
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111 ( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK ) | \
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112 ( ( unsigned portLONG ) AT91C_PB9_EMDIO ) | \
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113 ( ( unsigned portLONG ) AT91C_PB7_ERXER ) | \
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114 ( ( unsigned portLONG ) AT91C_PB17_ERXCK );
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116 /*-----------------------------------------------------------*/
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119 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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121 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
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124 * Initialise both the Tx and Rx descriptors used by the EMAC.
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126 static void prvSetupDescriptors(void);
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129 * Write our MAC address into the EMAC. The MAC address is set as one of the
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132 static void prvSetupMACAddress( void );
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135 * Configure the EMAC and AIC for EMAC interrupts.
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137 static void prvSetupEMACInterrupt( void );
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140 * Some initialisation functions taken from the Atmel EMAC sample code.
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142 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
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143 #if USE_RMII_INTERFACE != 1
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144 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
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146 static portBASE_TYPE xGetLinkSpeed( void );
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147 static portBASE_TYPE prvProbePHY( void );
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149 /*-----------------------------------------------------------*/
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151 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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152 comment above the emacADDRESS_MASK definition. */
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153 #pragma data_alignment=8
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154 static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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156 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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157 above the emacADDRESS_MASK definition. */
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158 #pragma data_alignment=8
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159 static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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161 /* Descriptors used to communicate between the program and the EMAC peripheral.
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162 These descriptors hold the locations and state of the Rx and Tx buffers. */
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163 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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164 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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166 /* The IP and Ethernet addresses are read from the uIP setup. */
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167 const portCHAR cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
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168 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
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170 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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171 static xSemaphoreHandle xSemaphore = NULL;
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173 /*-----------------------------------------------------------*/
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175 xSemaphoreHandle xEMACInit( void )
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177 /* Code supplied by Atmel -------------------------------*/
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179 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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180 PHY has internal pull down. */
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181 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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183 #if USE_RMII_INTERFACE != 1
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184 /* PHY has internal pull down : set MII mode. */
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185 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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188 /* Clear PB18 <=> PHY powerdown. */
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189 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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190 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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191 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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193 /* After PHY power up, hardware reset. */
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194 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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195 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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197 /* Wait for hardware reset end. */
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198 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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200 __asm volatile ( "NOP" );
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202 __asm volatile ( "NOP" );
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204 /* Setup the pins. */
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205 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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206 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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208 /* Enable com between EMAC PHY.
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210 Enable management port. */
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211 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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213 /* MDC = MCK/32. */
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214 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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216 /* Wait for PHY auto init end (rather crude delay!). */
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217 vTaskDelay( emacPHY_INIT_DELAY );
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219 /* PHY configuration. */
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220 #if USE_RMII_INTERFACE != 1
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222 unsigned portLONG ulControl;
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224 /* PHY has internal pull down : disable MII isolate. */
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225 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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226 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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227 ulControl &= ~BMCR_ISOLATE;
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228 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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232 /* Disable management port again. */
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233 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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235 #if USE_RMII_INTERFACE != 1
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236 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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237 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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239 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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241 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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244 /* End of code supplied by Atmel ------------------------*/
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246 /* Setup the buffers and descriptors. */
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247 prvSetupDescriptors();
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249 /* Load our MAC address into the EMAC. */
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250 prvSetupMACAddress();
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252 /* Are we connected? */
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253 if( prvProbePHY() )
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255 /* Enable the interrupt! */
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256 portENTER_CRITICAL();
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258 prvSetupEMACInterrupt();
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259 vPassEMACSemaphore( xSemaphore );
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261 portEXIT_CRITICAL();
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266 /*-----------------------------------------------------------*/
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268 portLONG lEMACSend( void )
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270 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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271 portBASE_TYPE xWaitCycles = 0;
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272 portLONG lReturn = pdPASS;
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273 portCHAR *pcBuffer;
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275 /* Is a buffer available? */
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276 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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278 /* There is no room to write the Tx data to the Tx buffer. Wait a
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279 short while, then try again. */
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281 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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289 vTaskDelay( emacBUFFER_WAIT_DELAY );
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293 /* lReturn will only be pdPASS if a buffer is available. */
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294 if( lReturn == pdPASS )
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296 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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297 pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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298 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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300 /* If there is room, also copy in the application data if any. */
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301 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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303 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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307 portENTER_CRITICAL();
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309 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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311 /* Fill out the necessary in the descriptor to get the data sent. */
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312 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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313 | AT91C_LAST_BUFFER
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314 | AT91C_TRANSMIT_WRAP;
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315 uxTxBufferIndex = 0;
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319 /* Fill out the necessary in the descriptor to get the data sent. */
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320 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
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321 | AT91C_LAST_BUFFER;
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325 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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327 portEXIT_CRITICAL();
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332 /*-----------------------------------------------------------*/
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334 unsigned portLONG ulEMACPoll( void )
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336 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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337 unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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338 portCHAR *pcSource;
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340 /* Skip any fragments. */
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341 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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343 /* Mark the buffer as free again. */
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344 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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346 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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348 ulNextRxBuffer = 0;
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352 /* Is there a packet ready? */
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354 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
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356 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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357 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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359 if( ulSectionLength == 0 )
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361 /* The frame is longer than the buffer pointed to by this
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362 descriptor so copy the entire buffer to uIP - then move onto
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363 the next descriptor to get the rest of the frame. */
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364 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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366 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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367 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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372 /* This is the last section of the frame. Copy the section to
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374 if( ulSectionLength < UIP_BUFSIZE )
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376 /* The section length holds the length of the entire frame.
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377 ulLengthSoFar holds the length of the frame sections already
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378 copied to uIP, so the length of the final section is
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379 ulSectionLength - ulLengthSoFar; */
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380 if( ulSectionLength > ulLengthSoFar )
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382 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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386 /* Is this the last buffer for the frame? If not why? */
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387 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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390 /* Mark the buffer as free again. */
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391 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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393 /* Increment to the next buffer, wrapping if necessary. */
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395 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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397 ulNextRxBuffer = 0;
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401 /* If we obtained data but for some reason did not find the end of the
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402 frame then discard the data as it must contain an error. */
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405 ulSectionLength = 0;
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408 return ulSectionLength;
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410 /*-----------------------------------------------------------*/
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412 static void prvSetupDescriptors(void)
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414 unsigned portBASE_TYPE xIndex;
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415 unsigned portLONG ulAddress;
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417 /* Initialise xRxDescriptors descriptor. */
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418 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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420 /* Calculate the address of the nth buffer within the array. */
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421 ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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423 /* Write the buffer address into the descriptor. The DMA will place
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424 the data at this address when this descriptor is being used. Mask off
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425 the bottom bits of the address as these have special meaning. */
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426 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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429 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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430 to the first buffer. */
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431 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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433 /* Initialise xTxDescriptors. */
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434 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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436 /* Calculate the address of the nth buffer within the array. */
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437 ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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439 /* Write the buffer address into the descriptor. The DMA will read
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440 data from here when the descriptor is being used. */
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441 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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442 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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445 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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446 to the first buffer. */
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447 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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449 /* Tell the EMAC where to find the descriptors. */
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450 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
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451 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
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453 /* Clear all the bits in the receive status register. */
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454 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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456 /* Enable the copy of data into the buffers, ignore broadcasts,
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457 and don't copy FCS. */
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458 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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460 /* Enable Rx and Tx, plus the stats register. */
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461 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
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463 /*-----------------------------------------------------------*/
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465 static void prvSetupMACAddress( void )
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467 /* Must be written SA1L then SA1H. */
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468 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
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469 ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
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470 ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |
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473 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
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476 /*-----------------------------------------------------------*/
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478 static void prvSetupEMACInterrupt( void )
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480 /* Create the semaphore used to trigger the EMAC task. */
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481 vSemaphoreCreateBinary( xSemaphore );
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484 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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485 first interrupt occurs. */
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486 xSemaphoreTake( xSemaphore, emacNO_DELAY );
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487 portENTER_CRITICAL();
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489 /* We want to interrupt on Rx events. */
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490 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
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492 /* Enable the interrupts in the AIC. */
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493 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
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494 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
496 portEXIT_CRITICAL();
\r
499 /*-----------------------------------------------------------*/
\r
505 * The following functions are initialisation functions taken from the Atmel
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506 * EMAC sample code.
\r
509 static portBASE_TYPE prvProbePHY( void )
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511 unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
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512 portBASE_TYPE xReturn = pdPASS;
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514 /* Code supplied by Atmel (reformatted) -----------------*/
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516 /* Enable management port */
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517 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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518 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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520 /* Read the PHY ID. */
\r
521 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
522 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
527 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
528 0001 stands for Rev. A, etc.
\r
530 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
532 /* Did not expect this ID. */
\r
537 ulStatus = xGetLinkSpeed();
\r
539 if( ulStatus != pdPASS )
\r
545 /* Disable management port */
\r
546 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
548 /* End of code supplied by Atmel ------------------------*/
\r
552 /*-----------------------------------------------------------*/
\r
554 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
\r
556 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
558 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
559 | (2 << 16) | (2 << 28)
\r
560 | ((ucPHYAddress & 0x1f) << 23)
\r
561 | (ucAddress << 18);
\r
563 /* Wait until IDLE bit in Network Status register is cleared. */
\r
564 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
569 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
571 /* End of code supplied by Atmel ------------------------*/
\r
573 /*-----------------------------------------------------------*/
\r
575 #if USE_RMII_INTERFACE != 1
\r
576 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
\r
578 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
580 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
581 | (2 << 16) | (1 << 28)
\r
582 | ((ucPHYAddress & 0x1f) << 23)
\r
583 | (ucAddress << 18))
\r
584 | (ulValue & 0xffff);
\r
586 /* Wait until IDLE bit in Network Status register is cleared */
\r
587 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
592 /* End of code supplied by Atmel ------------------------*/
\r
595 /*-----------------------------------------------------------*/
\r
597 static portBASE_TYPE xGetLinkSpeed( void )
\r
599 unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
601 /* Code supplied by Atmel (reformatted) -----------------*/
\r
603 /* Link status is latched, so read twice to get current value */
\r
604 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
605 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
607 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
613 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
614 if (ulBMCR & BMCR_ANENABLE)
\r
616 /* AutoNegotiation is enabled. */
\r
617 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
619 /* Auto-negotiation in progress. */
\r
623 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
624 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
626 ulSpeed = SPEED_100;
\r
630 ulSpeed = SPEED_10;
\r
633 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
635 ulDuplex = DUPLEX_FULL;
\r
639 ulDuplex = DUPLEX_HALF;
\r
644 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
645 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
648 /* Update the MAC */
\r
649 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
650 if( ulSpeed == SPEED_100 )
\r
652 if( ulDuplex == DUPLEX_FULL )
\r
654 /* 100 Full Duplex */
\r
655 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
659 /* 100 Half Duplex */
\r
660 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
665 if (ulDuplex == DUPLEX_FULL)
\r
667 /* 10 Full Duplex */
\r
668 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
672 /* 10 Half Duplex */
\r
673 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
677 /* End of code supplied by Atmel ------------------------*/
\r