2 FreeRTOS.org V5.1.2 - Copyright (C) 2003-2009 Richard Barry.
\r
4 This file is part of the FreeRTOS.org distribution.
\r
6 FreeRTOS.org is free software; you can redistribute it and/or modify
\r
7 it under the terms of the GNU General Public License as published by
\r
8 the Free Software Foundation; either version 2 of the License, or
\r
9 (at your option) any later version.
\r
11 FreeRTOS.org is distributed in the hope that it will be useful,
\r
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 GNU General Public License for more details.
\r
16 You should have received a copy of the GNU General Public License
\r
17 along with FreeRTOS.org; if not, write to the Free Software
\r
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
20 A special exception to the GPL can be applied should you wish to distribute
\r
21 a combined work that includes FreeRTOS.org, without being obliged to provide
\r
22 the source code for any proprietary components. See the licensing section
\r
23 of http://www.FreeRTOS.org for full details of how and when the exception
\r
26 ***************************************************************************
\r
27 ***************************************************************************
\r
29 * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
\r
31 * This is a concise, step by step, 'hands on' guide that describes both *
\r
32 * general multitasking concepts and FreeRTOS specifics. It presents and *
\r
33 * explains numerous examples that are written using the FreeRTOS API. *
\r
34 * Full source code for all the examples is provided in an accompanying *
\r
37 ***************************************************************************
\r
38 ***************************************************************************
\r
40 Please ensure to read the configuration and relevant port sections of the
\r
41 online documentation.
\r
43 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
46 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
49 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
50 licensing and training services.
\r
53 /* Standard includes. */
\r
56 /* Scheduler includes. */
\r
57 #include "FreeRTOS.h"
\r
61 /* Demo application includes. */
\r
62 #include "SAM7_EMAC.h"
\r
67 /* Hardware specific includes. */
\r
70 #include "AT91SAM7X256.h"
\r
73 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
\r
74 to use an MII interface. */
\r
75 #define USE_RMII_INTERFACE 0
\r
77 /* The buffer addresses written into the descriptors must be aligned so the
\r
78 last few bits are zero. These bits have special meaning for the EMAC
\r
79 peripheral and cannot be used as part of the address. */
\r
80 #define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )
\r
82 /* Bit used within the address stored in the descriptor to mark the last
\r
83 descriptor in the array. */
\r
84 #define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )
\r
86 /* Bit used within the Tx descriptor status to indicate whether the
\r
87 descriptor is under the control of the EMAC or the software. */
\r
88 #define emacTX_BUF_USED ( ( unsigned portLONG ) 0x80000000 )
\r
90 /* A short delay is used to wait for a buffer to become available, should
\r
91 one not be immediately available when trying to transmit a frame. */
\r
92 #define emacBUFFER_WAIT_DELAY ( 2 )
\r
93 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
\r
96 #define emacINTERRUPT_LEVEL ( 5 )
\r
97 #define emacNO_DELAY ( 0 )
\r
98 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
\r
99 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
\r
100 #define emacRESET_KEY ( ( unsigned portLONG ) 0xA5000000 )
\r
101 #define emacRESET_LENGTH ( ( unsigned portLONG ) ( 0x01 << 8 ) )
\r
103 /* The Atmel header file only defines the TX frame length mask. */
\r
104 #define emacRX_LENGTH_FRAME ( 0xfff )
\r
106 /* Peripheral setup for the EMAC. */
\r
107 #define emacPERIPHERAL_A_SETUP ( ( unsigned portLONG ) AT91C_PB2_ETX0 ) | \
\r
108 ( ( unsigned portLONG ) AT91C_PB12_ETXER ) | \
\r
109 ( ( unsigned portLONG ) AT91C_PB16_ECOL ) | \
\r
110 ( ( unsigned portLONG ) AT91C_PB11_ETX3 ) | \
\r
111 ( ( unsigned portLONG ) AT91C_PB6_ERX1 ) | \
\r
112 ( ( unsigned portLONG ) AT91C_PB15_ERXDV ) | \
\r
113 ( ( unsigned portLONG ) AT91C_PB13_ERX2 ) | \
\r
114 ( ( unsigned portLONG ) AT91C_PB3_ETX1 ) | \
\r
115 ( ( unsigned portLONG ) AT91C_PB8_EMDC ) | \
\r
116 ( ( unsigned portLONG ) AT91C_PB5_ERX0 ) | \
\r
117 ( ( unsigned portLONG ) AT91C_PB14_ERX3 ) | \
\r
118 ( ( unsigned portLONG ) AT91C_PB4_ECRS_ECRSDV ) | \
\r
119 ( ( unsigned portLONG ) AT91C_PB1_ETXEN ) | \
\r
120 ( ( unsigned portLONG ) AT91C_PB10_ETX2 ) | \
\r
121 ( ( unsigned portLONG ) AT91C_PB0_ETXCK_EREFCK ) | \
\r
122 ( ( unsigned portLONG ) AT91C_PB9_EMDIO ) | \
\r
123 ( ( unsigned portLONG ) AT91C_PB7_ERXER ) | \
\r
124 ( ( unsigned portLONG ) AT91C_PB17_ERXCK );
\r
126 /*-----------------------------------------------------------*/
\r
129 * Prototype for the EMAC interrupt function - called by the asm wrapper.
\r
131 extern void vEMACISR_Wrapper( void ) __attribute__((naked));
\r
134 * Initialise both the Tx and Rx descriptors used by the EMAC.
\r
136 static void prvSetupDescriptors(void);
\r
139 * Write our MAC address into the EMAC. The MAC address is set as one of the
\r
142 static void prvSetupMACAddress( void );
\r
145 * Configure the EMAC and AIC for EMAC interrupts.
\r
147 static void prvSetupEMACInterrupt( void );
\r
150 * Some initialisation functions taken from the Atmel EMAC sample code.
\r
152 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue );
\r
153 #if USE_RMII_INTERFACE != 1
\r
154 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue);
\r
156 static portBASE_TYPE xGetLinkSpeed( void );
\r
157 static portBASE_TYPE prvProbePHY( void );
\r
159 /*-----------------------------------------------------------*/
\r
161 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
\r
162 comment above the emacADDRESS_MASK definition. */
\r
163 #pragma data_alignment=8
\r
164 static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
\r
166 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
\r
167 above the emacADDRESS_MASK definition. */
\r
168 #pragma data_alignment=8
\r
169 static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
\r
171 /* Descriptors used to communicate between the program and the EMAC peripheral.
\r
172 These descriptors hold the locations and state of the Rx and Tx buffers. */
\r
173 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
\r
174 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
\r
176 /* The IP and Ethernet addresses are read from the uIP setup. */
\r
177 const portCHAR cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
\r
178 const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
\r
180 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
\r
181 static xSemaphoreHandle xSemaphore = NULL;
\r
183 /*-----------------------------------------------------------*/
\r
185 xSemaphoreHandle xEMACInit( void )
\r
187 /* Code supplied by Atmel -------------------------------*/
\r
189 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
\r
190 PHY has internal pull down. */
\r
191 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
\r
193 #if USE_RMII_INTERFACE != 1
\r
194 /* PHY has internal pull down : set MII mode. */
\r
195 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
\r
198 /* Clear PB18 <=> PHY powerdown. */
\r
199 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
\r
200 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
\r
201 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
\r
203 /* After PHY power up, hardware reset. */
\r
204 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
\r
205 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
\r
207 /* Wait for hardware reset end. */
\r
208 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
\r
210 __asm volatile ( "NOP" );
\r
212 __asm volatile ( "NOP" );
\r
214 /* Setup the pins. */
\r
215 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
\r
216 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
\r
218 /* Enable com between EMAC PHY.
\r
220 Enable management port. */
\r
221 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
223 /* MDC = MCK/32. */
\r
224 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
226 /* Wait for PHY auto init end (rather crude delay!). */
\r
227 vTaskDelay( emacPHY_INIT_DELAY );
\r
229 /* PHY configuration. */
\r
230 #if USE_RMII_INTERFACE != 1
\r
232 unsigned portLONG ulControl;
\r
234 /* PHY has internal pull down : disable MII isolate. */
\r
235 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
\r
236 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
\r
237 ulControl &= ~BMCR_ISOLATE;
\r
238 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
\r
242 /* Disable management port again. */
\r
243 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
245 #if USE_RMII_INTERFACE != 1
\r
246 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
\r
247 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
\r
249 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
\r
251 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
\r
254 /* End of code supplied by Atmel ------------------------*/
\r
256 /* Setup the buffers and descriptors. */
\r
257 prvSetupDescriptors();
\r
259 /* Load our MAC address into the EMAC. */
\r
260 prvSetupMACAddress();
\r
262 /* Are we connected? */
\r
263 if( prvProbePHY() )
\r
265 /* Enable the interrupt! */
\r
266 portENTER_CRITICAL();
\r
268 prvSetupEMACInterrupt();
\r
269 vPassEMACSemaphore( xSemaphore );
\r
271 portEXIT_CRITICAL();
\r
276 /*-----------------------------------------------------------*/
\r
278 portLONG lEMACSend( void )
\r
280 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
\r
281 portBASE_TYPE xWaitCycles = 0;
\r
282 portLONG lReturn = pdPASS;
\r
283 portCHAR *pcBuffer;
\r
285 /* Is a buffer available? */
\r
286 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
\r
288 /* There is no room to write the Tx data to the Tx buffer. Wait a
\r
289 short while, then try again. */
\r
291 if( xWaitCycles > emacMAX_WAIT_CYCLES )
\r
299 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
303 /* lReturn will only be pdPASS if a buffer is available. */
\r
304 if( lReturn == pdPASS )
\r
306 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
\r
307 pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
\r
308 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
\r
310 /* If there is room, also copy in the application data if any. */
\r
311 if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
\r
313 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
\r
317 portENTER_CRITICAL();
\r
319 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
\r
321 /* Fill out the necessary in the descriptor to get the data sent. */
\r
322 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
\r
323 | AT91C_LAST_BUFFER
\r
324 | AT91C_TRANSMIT_WRAP;
\r
325 uxTxBufferIndex = 0;
\r
329 /* Fill out the necessary in the descriptor to get the data sent. */
\r
330 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned portLONG ) AT91C_LENGTH_FRAME )
\r
331 | AT91C_LAST_BUFFER;
\r
335 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
\r
337 portEXIT_CRITICAL();
\r
342 /*-----------------------------------------------------------*/
\r
344 unsigned portLONG ulEMACPoll( void )
\r
346 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
\r
347 unsigned portLONG ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
\r
348 portCHAR *pcSource;
\r
350 /* Skip any fragments. */
\r
351 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
\r
353 /* Mark the buffer as free again. */
\r
354 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
356 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
358 ulNextRxBuffer = 0;
\r
362 /* Is there a packet ready? */
\r
364 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
\r
366 pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
\r
367 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
\r
369 if( ulSectionLength == 0 )
\r
371 /* The frame is longer than the buffer pointed to by this
\r
372 descriptor so copy the entire buffer to uIP - then move onto
\r
373 the next descriptor to get the rest of the frame. */
\r
374 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
\r
376 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
\r
377 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
\r
382 /* This is the last section of the frame. Copy the section to
\r
384 if( ulSectionLength < UIP_BUFSIZE )
\r
386 /* The section length holds the length of the entire frame.
\r
387 ulLengthSoFar holds the length of the frame sections already
\r
388 copied to uIP, so the length of the final section is
\r
389 ulSectionLength - ulLengthSoFar; */
\r
390 if( ulSectionLength > ulLengthSoFar )
\r
392 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
\r
396 /* Is this the last buffer for the frame? If not why? */
\r
397 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
\r
400 /* Mark the buffer as free again. */
\r
401 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
\r
403 /* Increment to the next buffer, wrapping if necessary. */
\r
405 if( ulNextRxBuffer >= NB_RX_BUFFERS )
\r
407 ulNextRxBuffer = 0;
\r
411 /* If we obtained data but for some reason did not find the end of the
\r
412 frame then discard the data as it must contain an error. */
\r
415 ulSectionLength = 0;
\r
418 return ulSectionLength;
\r
420 /*-----------------------------------------------------------*/
\r
422 static void prvSetupDescriptors(void)
\r
424 unsigned portBASE_TYPE xIndex;
\r
425 unsigned portLONG ulAddress;
\r
427 /* Initialise xRxDescriptors descriptor. */
\r
428 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
\r
430 /* Calculate the address of the nth buffer within the array. */
\r
431 ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
\r
433 /* Write the buffer address into the descriptor. The DMA will place
\r
434 the data at this address when this descriptor is being used. Mask off
\r
435 the bottom bits of the address as these have special meaning. */
\r
436 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
439 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
440 to the first buffer. */
\r
441 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
\r
443 /* Initialise xTxDescriptors. */
\r
444 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
446 /* Calculate the address of the nth buffer within the array. */
\r
447 ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
449 /* Write the buffer address into the descriptor. The DMA will read
\r
450 data from here when the descriptor is being used. */
\r
451 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
452 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
455 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
456 to the first buffer. */
\r
457 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
459 /* Tell the EMAC where to find the descriptors. */
\r
460 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned portLONG ) xRxDescriptors;
\r
461 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned portLONG ) xTxDescriptors;
\r
463 /* Clear all the bits in the receive status register. */
\r
464 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
466 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
467 and don't copy FCS. */
\r
468 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
470 /* Enable Rx and Tx, plus the stats register. */
\r
471 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
473 /*-----------------------------------------------------------*/
\r
475 static void prvSetupMACAddress( void )
\r
477 /* Must be written SA1L then SA1H. */
\r
478 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
\r
479 ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
\r
480 ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |
\r
483 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
\r
486 /*-----------------------------------------------------------*/
\r
488 static void prvSetupEMACInterrupt( void )
\r
490 /* Create the semaphore used to trigger the EMAC task. */
\r
491 vSemaphoreCreateBinary( xSemaphore );
\r
494 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
495 first interrupt occurs. */
\r
496 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
497 portENTER_CRITICAL();
\r
499 /* We want to interrupt on Rx events. */
\r
500 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
\r
502 /* Enable the interrupts in the AIC. */
\r
503 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
504 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
506 portEXIT_CRITICAL();
\r
509 /*-----------------------------------------------------------*/
\r
515 * The following functions are initialisation functions taken from the Atmel
\r
516 * EMAC sample code.
\r
519 static portBASE_TYPE prvProbePHY( void )
\r
521 unsigned portLONG ulPHYId1, ulPHYId2, ulStatus;
\r
522 portBASE_TYPE xReturn = pdPASS;
\r
524 /* Code supplied by Atmel (reformatted) -----------------*/
\r
526 /* Enable management port */
\r
527 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
528 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
530 /* Read the PHY ID. */
\r
531 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
532 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
537 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
538 0001 stands for Rev. A, etc.
\r
540 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
542 /* Did not expect this ID. */
\r
547 ulStatus = xGetLinkSpeed();
\r
549 if( ulStatus != pdPASS )
\r
555 /* Disable management port */
\r
556 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
558 /* End of code supplied by Atmel ------------------------*/
\r
562 /*-----------------------------------------------------------*/
\r
564 static void vReadPHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG *pulValue )
\r
566 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
568 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
569 | (2 << 16) | (2 << 28)
\r
570 | ((ucPHYAddress & 0x1f) << 23)
\r
571 | (ucAddress << 18);
\r
573 /* Wait until IDLE bit in Network Status register is cleared. */
\r
574 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
579 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
581 /* End of code supplied by Atmel ------------------------*/
\r
583 /*-----------------------------------------------------------*/
\r
585 #if USE_RMII_INTERFACE != 1
\r
586 static void vWritePHY( unsigned portCHAR ucPHYAddress, unsigned portCHAR ucAddress, unsigned portLONG ulValue )
\r
588 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
590 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
591 | (2 << 16) | (1 << 28)
\r
592 | ((ucPHYAddress & 0x1f) << 23)
\r
593 | (ucAddress << 18))
\r
594 | (ulValue & 0xffff);
\r
596 /* Wait until IDLE bit in Network Status register is cleared */
\r
597 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
602 /* End of code supplied by Atmel ------------------------*/
\r
605 /*-----------------------------------------------------------*/
\r
607 static portBASE_TYPE xGetLinkSpeed( void )
\r
609 unsigned portLONG ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
611 /* Code supplied by Atmel (reformatted) -----------------*/
\r
613 /* Link status is latched, so read twice to get current value */
\r
614 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
615 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
617 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
623 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
624 if (ulBMCR & BMCR_ANENABLE)
\r
626 /* AutoNegotiation is enabled. */
\r
627 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
629 /* Auto-negotiation in progress. */
\r
633 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
634 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
636 ulSpeed = SPEED_100;
\r
640 ulSpeed = SPEED_10;
\r
643 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
645 ulDuplex = DUPLEX_FULL;
\r
649 ulDuplex = DUPLEX_HALF;
\r
654 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
655 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
658 /* Update the MAC */
\r
659 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
660 if( ulSpeed == SPEED_100 )
\r
662 if( ulDuplex == DUPLEX_FULL )
\r
664 /* 100 Full Duplex */
\r
665 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
669 /* 100 Half Duplex */
\r
670 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
675 if (ulDuplex == DUPLEX_FULL)
\r
677 /* 10 Full Duplex */
\r
678 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
682 /* 10 Half Duplex */
\r
683 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
687 /* End of code supplied by Atmel ------------------------*/
\r