2 FreeRTOS V5.4.0 - Copyright (C) 2003-2009 Richard Barry.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License (version 2) as published by the
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8 Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS without being obliged to provide the
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11 source code for proprietary components outside of the FreeRTOS kernel.
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12 Alternative commercial license and support terms are also available upon
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13 request. See the licensing section of http://www.FreeRTOS.org for full
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16 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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21 You should have received a copy of the GNU General Public License along
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22 with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
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23 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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26 ***************************************************************************
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28 * Looking for a quick start? Then check out the FreeRTOS eBook! *
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29 * See http://www.FreeRTOS.org/Documentation for details *
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31 ***************************************************************************
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35 Please ensure to read the configuration and relevant port sections of the
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36 online documentation.
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38 http://www.FreeRTOS.org - Documentation, latest information, license and
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41 http://www.SafeRTOS.com - A version that is certified for use in safety
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44 http://www.OpenRTOS.com - Commercial support, development, porting,
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45 licensing and training services.
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50 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
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53 /* Standard includes. */
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56 /* Scheduler includes. */
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57 #include "FreeRTOS.h"
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61 /* Demo application includes. */
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64 /*-----------------------------------------------------------*/
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66 /* Constants to setup and access the UART. */
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67 #define serDLAB ( ( unsigned portCHAR ) 0x80 )
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68 #define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )
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69 #define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )
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70 #define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )
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71 #define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )
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72 #define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )
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73 #define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )
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74 #define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )
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76 /* Constants to setup and access the VIC. */
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77 #define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )
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78 #define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )
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79 #define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
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80 #define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
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82 /* Constants to determine the ISR source. */
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83 #define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
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84 #define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
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85 #define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
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86 #define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
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87 #define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )
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90 #define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
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91 #define serHANDLE ( ( xComPortHandle ) 1 )
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92 #define serNO_BLOCK ( ( portTickType ) 0 )
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94 /*-----------------------------------------------------------*/
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96 /* Queues used to hold received characters, and characters waiting to be
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98 static xQueueHandle xRxedChars;
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99 static xQueueHandle xCharsForTx;
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100 static volatile portLONG lTHREEmpty = pdFALSE;
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102 /*-----------------------------------------------------------*/
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104 /* The ISR. Note that this is called by a wrapper written in the file
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105 SerialISR.s79. See the WEB documentation for this port for further
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107 __arm void vSerialISR( void );
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109 /*-----------------------------------------------------------*/
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111 xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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113 unsigned portLONG ulDivisor, ulWantedClock;
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114 xComPortHandle xReturn = serHANDLE;
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115 extern void ( vSerialISREntry) ( void );
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117 /* Create the queues used to hold Rx and Tx characters. */
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118 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
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119 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
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121 /* Initialise the THRE empty flag. */
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122 lTHREEmpty = pdTRUE;
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125 ( xRxedChars != serINVALID_QUEUE ) &&
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126 ( xCharsForTx != serINVALID_QUEUE ) &&
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127 ( ulWantedBaud != ( unsigned portLONG ) 0 )
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130 portENTER_CRITICAL();
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132 /* Setup the baud rate: Calculate the divisor value. */
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133 ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
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134 ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
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136 /* Set the DLAB bit so we can access the divisor. */
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139 /* Setup the divisor. */
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140 U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
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142 U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
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144 /* Turn on the FIFO's and clear the buffers. */
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145 U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
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147 /* Setup transmission format. */
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148 U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
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150 /* Setup the VIC for the UART. */
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151 VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
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152 VICIntEnable |= serU0VIC_CHANNEL_BIT;
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153 VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry;
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154 VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
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156 /* Enable UART0 interrupts. */
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157 U0IER |= serENABLE_INTERRUPTS;
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159 portEXIT_CRITICAL();
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161 xReturn = ( xComPortHandle ) 1;
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165 xReturn = ( xComPortHandle ) 0;
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170 /*-----------------------------------------------------------*/
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172 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
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174 /* The port handle is not required as this driver only supports UART0. */
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177 /* Get the next character from the buffer. Return false if no characters
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178 are available, or arrive before xBlockTime expires. */
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179 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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188 /*-----------------------------------------------------------*/
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190 void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
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192 signed portCHAR *pxNext;
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194 /* NOTE: This implementation does not handle the queue being full as no
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195 block time is used! */
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197 /* The port handle is not required as this driver only supports UART0. */
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199 ( void ) usStringLength;
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201 /* Send each character in the string, one at a time. */
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202 pxNext = ( signed portCHAR * ) pcString;
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205 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
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209 /*-----------------------------------------------------------*/
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211 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
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213 signed portBASE_TYPE xReturn;
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215 /* The port handle is not required as this driver only supports UART0. */
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218 portENTER_CRITICAL();
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220 /* Is there space to write directly to the UART? */
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221 if( lTHREEmpty == ( portLONG ) pdTRUE )
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223 /* We wrote the character directly to the UART, so was
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225 lTHREEmpty = pdFALSE;
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231 /* We cannot write directly to the UART, so queue the character.
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232 Block for a maximum of xBlockTime if there is no space in the
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233 queue. It is ok to block within a critical section as each
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234 task has it's own critical section management. */
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235 xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
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237 /* Depending on queue sizing and task prioritisation: While we
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238 were blocked waiting to post interrupts were not disabled. It is
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239 possible that the serial ISR has emptied the Tx queue, in which
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240 case we need to start the Tx off again. */
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241 if( lTHREEmpty == ( portLONG ) pdTRUE )
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243 xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
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244 lTHREEmpty = pdFALSE;
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249 portEXIT_CRITICAL();
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253 /*-----------------------------------------------------------*/
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255 __arm void vSerialISR( void )
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257 signed portCHAR cChar;
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258 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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260 /* What caused the interrupt? */
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261 switch( U0IIR & serINTERRUPT_SOURCE_MASK )
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263 case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
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267 case serSOURCE_THRE : /* The THRE is empty. If there is another
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268 character in the Tx queue, send it now. */
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269 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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275 /* There are no further characters
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276 queued to send so we can indicate
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277 that the THRE is available. */
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278 lTHREEmpty = pdTRUE;
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282 case serSOURCE_RX_TIMEOUT :
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283 case serSOURCE_RX : /* A character was received. Place it in
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284 the queue of received characters. */
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286 xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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289 default : /* There is nothing to do, leave the ISR. */
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293 /* Exit the ISR. If a task was woken by either a character being received
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294 or transmitted then a context switch will occur. */
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295 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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297 /* Clear the ISR in the VIC. */
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298 VICVectAddr = serCLEAR_VIC_INTERRUPT;
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300 /*-----------------------------------------------------------*/
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