2 FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
\r
4 This file is part of the FreeRTOS.org distribution.
\r
6 FreeRTOS.org is free software; you can redistribute it and/or modify
\r
7 it under the terms of the GNU General Public License as published by
\r
8 the Free Software Foundation; either version 2 of the License, or
\r
9 (at your option) any later version.
\r
11 FreeRTOS.org is distributed in the hope that it will be useful,
\r
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 GNU General Public License for more details.
\r
16 You should have received a copy of the GNU General Public License
\r
17 along with FreeRTOS.org; if not, write to the Free Software
\r
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
20 A special exception to the GPL can be applied should you wish to distribute
\r
21 a combined work that includes FreeRTOS.org, without being obliged to provide
\r
22 the source code for any proprietary components. See the licensing section
\r
23 of http://www.FreeRTOS.org for full details of how and when the exception
\r
26 ***************************************************************************
\r
27 See http://www.FreeRTOS.org for documentation, latest information, license
\r
28 and contact details. Please ensure to read the configuration and relevant
\r
29 port sections of the online documentation.
\r
31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
\r
32 with commercial development and support options.
\r
33 ***************************************************************************
\r
38 BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
\r
41 /* Standard includes. */
\r
44 /* Scheduler includes. */
\r
45 #include "FreeRTOS.h"
\r
49 /* Demo application includes. */
\r
52 /*-----------------------------------------------------------*/
\r
54 /* Constants to setup and access the UART. */
\r
55 #define serDLAB ( ( unsigned portCHAR ) 0x80 )
\r
56 #define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )
\r
57 #define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )
\r
58 #define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )
\r
59 #define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )
\r
60 #define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )
\r
61 #define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )
\r
62 #define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )
\r
64 /* Constants to setup and access the VIC. */
\r
65 #define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )
\r
66 #define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )
\r
67 #define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
\r
68 #define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
\r
70 /* Constants to determine the ISR source. */
\r
71 #define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
\r
72 #define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
\r
73 #define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
\r
74 #define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
\r
75 #define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )
\r
78 #define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
\r
79 #define serHANDLE ( ( xComPortHandle ) 1 )
\r
80 #define serNO_BLOCK ( ( portTickType ) 0 )
\r
82 /*-----------------------------------------------------------*/
\r
84 /* Queues used to hold received characters, and characters waiting to be
\r
86 static xQueueHandle xRxedChars;
\r
87 static xQueueHandle xCharsForTx;
\r
88 static volatile portLONG lTHREEmpty = pdFALSE;
\r
90 /*-----------------------------------------------------------*/
\r
92 /* The ISR. Note that this is called by a wrapper written in the file
\r
93 SerialISR.s79. See the WEB documentation for this port for further
\r
95 __arm void vSerialISR( void );
\r
97 /*-----------------------------------------------------------*/
\r
99 xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
\r
101 unsigned portLONG ulDivisor, ulWantedClock;
\r
102 xComPortHandle xReturn = serHANDLE;
\r
103 extern void ( vSerialISREntry) ( void );
\r
105 /* Create the queues used to hold Rx and Tx characters. */
\r
106 xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
\r
107 xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
\r
109 /* Initialise the THRE empty flag. */
\r
110 lTHREEmpty = pdTRUE;
\r
113 ( xRxedChars != serINVALID_QUEUE ) &&
\r
114 ( xCharsForTx != serINVALID_QUEUE ) &&
\r
115 ( ulWantedBaud != ( unsigned portLONG ) 0 )
\r
118 portENTER_CRITICAL();
\r
120 /* Setup the baud rate: Calculate the divisor value. */
\r
121 ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
\r
122 ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
\r
124 /* Set the DLAB bit so we can access the divisor. */
\r
127 /* Setup the divisor. */
\r
128 U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
\r
130 U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
\r
132 /* Turn on the FIFO's and clear the buffers. */
\r
133 U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
\r
135 /* Setup transmission format. */
\r
136 U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
\r
138 /* Setup the VIC for the UART. */
\r
139 VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
\r
140 VICIntEnable |= serU0VIC_CHANNEL_BIT;
\r
141 VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry;
\r
142 VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
\r
144 /* Enable UART0 interrupts. */
\r
145 U0IER |= serENABLE_INTERRUPTS;
\r
147 portEXIT_CRITICAL();
\r
149 xReturn = ( xComPortHandle ) 1;
\r
153 xReturn = ( xComPortHandle ) 0;
\r
158 /*-----------------------------------------------------------*/
\r
160 signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
\r
162 /* The port handle is not required as this driver only supports UART0. */
\r
165 /* Get the next character from the buffer. Return false if no characters
\r
166 are available, or arrive before xBlockTime expires. */
\r
167 if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
\r
176 /*-----------------------------------------------------------*/
\r
178 void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
\r
180 signed portCHAR *pxNext;
\r
182 /* NOTE: This implementation does not handle the queue being full as no
\r
183 block time is used! */
\r
185 /* The port handle is not required as this driver only supports UART0. */
\r
187 ( void ) usStringLength;
\r
189 /* Send each character in the string, one at a time. */
\r
190 pxNext = ( signed portCHAR * ) pcString;
\r
193 xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
\r
197 /*-----------------------------------------------------------*/
\r
199 signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
\r
201 signed portBASE_TYPE xReturn;
\r
203 /* The port handle is not required as this driver only supports UART0. */
\r
206 portENTER_CRITICAL();
\r
208 /* Is there space to write directly to the UART? */
\r
209 if( lTHREEmpty == ( portLONG ) pdTRUE )
\r
211 /* We wrote the character directly to the UART, so was
\r
213 lTHREEmpty = pdFALSE;
\r
219 /* We cannot write directly to the UART, so queue the character.
\r
220 Block for a maximum of xBlockTime if there is no space in the
\r
221 queue. It is ok to block within a critical section as each
\r
222 task has it's own critical section management. */
\r
223 xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
\r
225 /* Depending on queue sizing and task prioritisation: While we
\r
226 were blocked waiting to post interrupts were not disabled. It is
\r
227 possible that the serial ISR has emptied the Tx queue, in which
\r
228 case we need to start the Tx off again. */
\r
229 if( lTHREEmpty == ( portLONG ) pdTRUE )
\r
231 xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
\r
232 lTHREEmpty = pdFALSE;
\r
237 portEXIT_CRITICAL();
\r
241 /*-----------------------------------------------------------*/
\r
243 __arm void vSerialISR( void )
\r
245 signed portCHAR cChar;
\r
246 portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE;
\r
248 /* What caused the interrupt? */
\r
249 switch( U0IIR & serINTERRUPT_SOURCE_MASK )
\r
251 case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
\r
255 case serSOURCE_THRE : /* The THRE is empty. If there is another
\r
256 character in the Tx queue, send it now. */
\r
257 if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
\r
263 /* There are no further characters
\r
264 queued to send so we can indicate
\r
265 that the THRE is available. */
\r
266 lTHREEmpty = pdTRUE;
\r
270 case serSOURCE_RX_TIMEOUT :
\r
271 case serSOURCE_RX : /* A character was received. Place it in
\r
272 the queue of received characters. */
\r
274 if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
\r
276 xTaskWokenByRx = pdTRUE;
\r
280 default : /* There is nothing to do, leave the ISR. */
\r
284 /* Exit the ISR. If a task was woken by either a character being received
\r
285 or transmitted then a context switch will occur. */
\r
286 portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
\r
288 /* Clear the ISR in the VIC. */
\r
289 VICVectAddr = serCLEAR_VIC_INTERRUPT;
\r
291 /*-----------------------------------------------------------*/
\r