1 /***********************************************************************/
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2 /* This file is part of the uVision/ARM development tools */
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3 /* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
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4 /***********************************************************************/
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6 /* STARTUP.S: Startup file for Philips LPC2000 device series */
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8 /***********************************************************************/
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12 //*** <<< Use Configuration Wizard in Context Menu >>> ***
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16 // *** Startup Code (executed after Reset) ***
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19 // Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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29 I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */
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30 F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */
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34 // <h> Stack Configuration (Stack Sizes in Bytes)
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35 // <o0> Undefined Mode <0x0-0xFFFFFFFF>
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36 // <o1> Supervisor Mode <0x0-0xFFFFFFFF>
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37 // <o2> Abort Mode <0x0-0xFFFFFFFF>
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38 // <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>
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39 // <o4> Interrupt Mode <0x0-0xFFFFFFFF>
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40 // <o5> User/System Mode <0x0-0xFFFFFFFF>
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43 UND_Stack_Size EQU 0x00000004
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44 SVC_Stack_Size EQU 0x00000100
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45 ABT_Stack_Size EQU 0x00000004
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46 FIQ_Stack_Size EQU 0x00000004
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47 IRQ_Stack_Size EQU 0x00000300
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48 USR_Stack_Size EQU 0x00000200
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50 AREA STACK, DATA, READWRITE, ALIGN=2
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51 DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
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52 DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
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53 DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
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54 DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
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55 DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
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56 DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
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60 // Phase Locked Loop (PLL) definitions
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61 PLL_BASE EQU 0xE01FC080 /* PLL Base Address */
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62 PLLCON_OFS EQU 0x00 /* PLL Control Offset*/
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63 PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */
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64 PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */
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65 PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */
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66 PLLCON_PLLE EQU (1<<0) /* PLL Enable */
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67 PLLCON_PLLC EQU (1<<1) /* PLL Connect */
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68 PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */
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69 PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */
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70 PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */
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74 // <i> Phase Locked Loop
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75 // <o1.0..4> MSEL: PLL Multiplier Selection
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78 // <o1.5..6> PSEL: PLL Divider Selection
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79 // <0=> 1 <1=> 2 <2=> 4 <3=> 8
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84 PLLCFG_Val EQU 0x00000024
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87 // Memory Accelerator Module (MAM) definitions
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88 MAM_BASE EQU 0xE01FC000 /* MAM Base Address */
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89 MAMCR_OFS EQU 0x00 /* MAM Control Offset*/
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90 MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */
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94 // <i> Memory Accelerator Module
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95 // <o1.0..1> MAM Control
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97 // <1=> Partially Enabled
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98 // <2=> Fully Enabled
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100 // <o2.0..2> MAM Timing
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101 // <0=> Reserved <1=> 1 <2=> 2 <3=> 3
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102 // <4=> 4 <5=> 5 <6=> 6 <7=> 7
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103 // <i> Fetch Cycles
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107 MAMCR_Val EQU 0x00000002
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108 MAMTIM_Val EQU 0x00000003
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111 // External Memory Controller (EMC) definitions
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112 EMC_BASE EQU 0xFFE00000 /* EMC Base Address */
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113 BCFG0_OFS EQU 0x00 /* BCFG0 Offset */
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114 BCFG1_OFS EQU 0x04 /* BCFG1 Offset */
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115 BCFG2_OFS EQU 0x08 /* BCFG2 Offset */
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116 BCFG3_OFS EQU 0x0C /* BCFG3 Offset */
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119 // <e> External Memory Controller (EMC)
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124 // <e> Bank Configuration 0 (BCFG0)
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125 // <o1.0..3> IDCY: Idle Cycles <0-15>
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126 // <o1.5..9> WST1: Wait States 1 <0-31>
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127 // <o1.11..15> WST2: Wait States 2 <0-31>
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128 // <o1.10> RBLE: Read Byte Lane Enable
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129 // <o1.26> WP: Write Protect
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130 // <o1.27> BM: Burst ROM
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131 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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132 // <2=> 32-bit <3=> Reserved
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136 BCFG0_Val EQU 0x0000FBEF
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139 // <e> Bank Configuration 1 (BCFG1)
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140 // <o1.0..3> IDCY: Idle Cycles <0-15>
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141 // <o1.5..9> WST1: Wait States 1 <0-31>
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142 // <o1.11..15> WST2: Wait States 2 <0-31>
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143 // <o1.10> RBLE: Read Byte Lane Enable
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144 // <o1.26> WP: Write Protect
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145 // <o1.27> BM: Burst ROM
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146 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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147 // <2=> 32-bit <3=> Reserved
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151 BCFG1_Val EQU 0x0000FBEF
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154 // <e> Bank Configuration 0 (BCFG2)
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155 // <o1.0..3> IDCY: Idle Cycles <0-15>
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156 // <o1.5..9> WST1: Wait States 1 <0-31>
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157 // <o1.11..15> WST2: Wait States 2 <0-31>
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158 // <o1.10> RBLE: Read Byte Lane Enable
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159 // <o1.26> WP: Write Protect
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160 // <o1.27> BM: Burst ROM
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161 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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162 // <2=> 32-bit <3=> Reserved
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166 BCFG2_Val EQU 0x0000FBEF
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169 // <e> Bank Configuration 3 (BCFG3)
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170 // <o1.0..3> IDCY: Idle Cycles <0-15>
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171 // <o1.5..9> WST1: Wait States 1 <0-31>
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172 // <o1.11..15> WST2: Wait States 2 <0-31>
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173 // <o1.10> RBLE: Read Byte Lane Enable
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174 // <o1.26> WP: Write Protect
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175 // <o1.27> BM: Burst ROM
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176 // <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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177 // <2=> 32-bit <3=> Reserved
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181 BCFG3_Val EQU 0x0000FBEF
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188 // External Memory Pins definitions
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189 PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */
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190 PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3,
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191 D0..31, A2..23, JTAG Pins */
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194 // Starupt Code must be linked first at Address at which it expects to run.
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196 $IF (EXTERNAL_MODE)
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197 CODE_BASE EQU 0x80000000
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199 CODE_BASE EQU 0x00000000
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202 AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4
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205 EXTERN CODE32 (?C?INIT)
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207 __startup PROC CODE32
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209 // Pre-defined interrupt handlers that may be directly
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210 // overwritten by C interrupt functions
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211 EXTERN CODE32 (Undef_Handler?A)
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212 EXTERN CODE32 (vPortYieldProcessor?A)
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213 EXTERN CODE32 (PAbt_Handler?A)
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214 EXTERN CODE32 (DAbt_Handler?A)
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215 EXTERN CODE32 (IRQ_Handler?A)
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216 EXTERN CODE32 (FIQ_Handler?A)
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218 // Exception Vectors
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219 // Mapped to Address 0.
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220 // Absolute addressing mode must be used.
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222 Vectors: LDR PC,Reset_Addr
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227 NOP /* Reserved Vector */
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229 LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */
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232 Reset_Addr: DD Reset_Handler
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233 Undef_Addr: DD Undef_Handler?A
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234 SWI_Addr: DD vPortYieldProcessor?A
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235 PAbt_Addr: DD PAbt_Handler?A
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236 DAbt_Addr: DD DAbt_Handler?A
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237 DD 0 /* Reserved Address */
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238 IRQ_Addr: DD IRQ_Handler?A
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239 FIQ_Addr: DD FIQ_Handler?A
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247 $IF (EXTERNAL_MODE)
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249 LDR R1, =PINSEL2_Val
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254 IF (EMC_SETUP != 0)
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257 IF (BCFG0_SETUP != 0)
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259 STR R1, [R0, #BCFG0_OFS]
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262 IF (BCFG1_SETUP != 0)
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264 STR R1, [R0, #BCFG1_OFS]
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267 IF (BCFG2_SETUP != 0)
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269 STR R1, [R0, #BCFG2_OFS]
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272 IF (BCFG3_SETUP != 0)
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274 STR R1, [R0, #BCFG3_OFS]
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280 IF (PLL_SETUP != 0)
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285 // Configure and Enable PLL
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286 MOV R3, #PLLCFG_Val
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287 STR R3, [R0, #PLLCFG_OFS]
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288 MOV R3, #PLLCON_PLLE
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289 STR R3, [R0, #PLLCON_OFS]
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290 STR R1, [R0, #PLLFEED_OFS]
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291 STR R2, [R0, #PLLFEED_OFS]
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293 // Wait until PLL Locked
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294 PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
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295 ANDS R3, R3, #PLLSTAT_PLOCK
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298 // Switch to PLL Clock
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299 MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
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300 STR R3, [R0, #PLLCON_OFS]
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301 STR R1, [R0, #PLLFEED_OFS]
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302 STR R2, [R0, #PLLFEED_OFS]
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306 IF (MAM_SETUP != 0)
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308 MOV R1, #MAMTIM_Val
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309 STR R1, [R0, #MAMTIM_OFS]
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311 STR R1, [R0, #MAMCR_OFS]
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315 // Memory Mapping (when Interrupt Vectors are in RAM)
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316 MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */
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325 // Setup Stack for each mode
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328 // Enter Undefined Instruction Mode and set its Stack Pointer
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329 MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
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331 SUB R0, R0, #UND_Stack_Size
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333 // Enter Abort Mode and set its Stack Pointer
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334 MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
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336 SUB R0, R0, #ABT_Stack_Size
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338 // Enter FIQ Mode and set its Stack Pointer
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339 MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
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341 SUB R0, R0, #FIQ_Stack_Size
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343 // Enter IRQ Mode and set its Stack Pointer
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344 MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
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346 SUB R0, R0, #IRQ_Stack_Size
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348 // Enter Supervisor Mode and set its Stack Pointer
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349 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
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351 SUB R0, R0, #SVC_Stack_Size
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353 // Enter S Mode and set its Stack Pointer
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354 MSR CPSR_c, #Mode_SYS
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357 // Start in supervisor mode
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358 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
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360 // Enter the C code
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362 TST R0,#1 ; Bit-0 set: INIT is Thumb
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363 LDREQ LR,=exit?A ; ARM Mode
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364 LDRNE LR,=exit?T ; Thumb Mode
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