1 ;/*****************************************************************************/
\r
2 ;/* STARTUP.S: Startup file for Philips LPC2000 */
\r
3 ;/*****************************************************************************/
\r
4 ;/* <<< Use Configuration Wizard in Context Menu >>> */
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5 ;/*****************************************************************************/
\r
6 ;/* This file is part of the uVision/ARM development tools. */
\r
7 ;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */
\r
8 ;/* This software may only be used under the terms of a valid, current, */
\r
9 ;/* end user licence from KEIL for a compatible version of KEIL software */
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10 ;/* development tools. Nothing else gives you the right to use this software. */
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11 ;/*****************************************************************************/
\r
15 ; * The STARTUP.S code is executed after CPU Reset. This file may be
\r
16 ; * translated with the following SET symbols. In uVision these SET
\r
17 ; * symbols are entered under Options - ASM - Define.
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19 ; * REMAP: when set the startup code initializes the register MEMMAP
\r
20 ; * which overwrites the settings of the CPU configuration pins. The
\r
21 ; * startup and interrupt vectors are remapped from:
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22 ; * 0x00000000 default setting (not remapped)
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23 ; * 0x80000000 when EXTMEM_MODE is used
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24 ; * 0x40000000 when RAM_MODE is used
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26 ; * EXTMEM_MODE: when set the device is configured for code execution
\r
27 ; * from external memory starting at address 0x80000000.
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29 ; * RAM_MODE: when set the device is configured for code execution
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30 ; * from on-chip RAM starting at address 0x40000000.
\r
32 ; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
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33 ; * the external BUS at startup.
\r
37 ; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
\r
47 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
\r
48 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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51 ;// <h> Stack Configuration (Stack Sizes in Bytes)
\r
52 ;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
\r
53 ;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
\r
54 ;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
\r
55 ;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
\r
56 ;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
\r
57 ;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
\r
60 UND_Stack_Size EQU 0x00000008
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61 SVC_Stack_Size EQU 0x00000300
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62 ABT_Stack_Size EQU 0x00000008
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63 FIQ_Stack_Size EQU 0x00000008
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64 IRQ_Stack_Size EQU 0x00000300
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65 USR_Stack_Size EQU 0x00000008
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67 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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68 FIQ_Stack_Size + IRQ_Stack_Size)
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70 AREA STACK, NOINIT, READWRITE, ALIGN=3
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72 Stack_Mem SPACE USR_Stack_Size
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73 __initial_sp SPACE ISR_Stack_Size
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78 ;// <h> Heap Configuration
\r
79 ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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82 Heap_Size EQU 0x00000000
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84 AREA HEAP, NOINIT, READWRITE, ALIGN=3
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86 Heap_Mem SPACE Heap_Size
\r
90 ; VPBDIV definitions
\r
91 VPBDIV EQU 0xE01FC100 ; VPBDIV Address
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93 ;// <e> VPBDIV Setup
\r
94 ;// <i> Peripheral Bus Clock Rate
\r
95 ;// <o1.0..1> VPBDIV: VPB Clock
\r
96 ;// <0=> VPB Clock = CPU Clock / 4
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97 ;// <1=> VPB Clock = CPU Clock
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98 ;// <2=> VPB Clock = CPU Clock / 2
\r
99 ;// <o1.4..5> XCLKDIV: XCLK Pin
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100 ;// <0=> XCLK Pin = CPU Clock / 4
\r
101 ;// <1=> XCLK Pin = CPU Clock
\r
102 ;// <2=> XCLK Pin = CPU Clock / 2
\r
105 VPBDIV_Val EQU 0x00000000
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108 ; Phase Locked Loop (PLL) definitions
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109 PLL_BASE EQU 0xE01FC080 ; PLL Base Address
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110 PLLCON_OFS EQU 0x00 ; PLL Control Offset
\r
111 PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
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112 PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
\r
113 PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
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114 PLLCON_PLLE EQU (1<<0) ; PLL Enable
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115 PLLCON_PLLC EQU (1<<1) ; PLL Connect
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116 PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
\r
117 PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
\r
118 PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
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121 ;// <o1.0..4> MSEL: PLL Multiplier Selection
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124 ;// <o1.5..6> PSEL: PLL Divider Selection
\r
125 ;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
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129 PLLCFG_Val EQU 0x00000024
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132 ; Memory Accelerator Module (MAM) definitions
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133 MAM_BASE EQU 0xE01FC000 ; MAM Base Address
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134 MAMCR_OFS EQU 0x00 ; MAM Control Offset
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135 MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
\r
138 ;// <o1.0..1> MAM Control
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140 ;// <1=> Partially Enabled
\r
141 ;// <2=> Fully Enabled
\r
143 ;// <o2.0..2> MAM Timing
\r
144 ;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
\r
145 ;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
\r
146 ;// <i> Fetch Cycles
\r
149 MAMCR_Val EQU 0x00000002
\r
150 MAMTIM_Val EQU 0x00000004
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153 ; External Memory Controller (EMC) definitions
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154 EMC_BASE EQU 0xFFE00000 ; EMC Base Address
\r
155 BCFG0_OFS EQU 0x00 ; BCFG0 Offset
\r
156 BCFG1_OFS EQU 0x04 ; BCFG1 Offset
\r
157 BCFG2_OFS EQU 0x08 ; BCFG2 Offset
\r
158 BCFG3_OFS EQU 0x0C ; BCFG3 Offset
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160 ;// <e> External Memory Controller (EMC)
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163 ;// <e> Bank Configuration 0 (BCFG0)
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164 ;// <o1.0..3> IDCY: Idle Cycles <0-15>
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165 ;// <o1.5..9> WST1: Wait States 1 <0-31>
\r
166 ;// <o1.11..15> WST2: Wait States 2 <0-31>
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167 ;// <o1.10> RBLE: Read Byte Lane Enable
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168 ;// <o1.26> WP: Write Protect
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169 ;// <o1.27> BM: Burst ROM
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170 ;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
\r
171 ;// <2=> 32-bit <3=> Reserved
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174 BCFG0_Val EQU 0x0000FBEF
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176 ;// <e> Bank Configuration 1 (BCFG1)
\r
177 ;// <o1.0..3> IDCY: Idle Cycles <0-15>
\r
178 ;// <o1.5..9> WST1: Wait States 1 <0-31>
\r
179 ;// <o1.11..15> WST2: Wait States 2 <0-31>
\r
180 ;// <o1.10> RBLE: Read Byte Lane Enable
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181 ;// <o1.26> WP: Write Protect
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182 ;// <o1.27> BM: Burst ROM
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183 ;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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184 ;// <2=> 32-bit <3=> Reserved
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187 BCFG1_Val EQU 0x0000FBEF
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189 ;// <e> Bank Configuration 2 (BCFG2)
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190 ;// <o1.0..3> IDCY: Idle Cycles <0-15>
\r
191 ;// <o1.5..9> WST1: Wait States 1 <0-31>
\r
192 ;// <o1.11..15> WST2: Wait States 2 <0-31>
\r
193 ;// <o1.10> RBLE: Read Byte Lane Enable
\r
194 ;// <o1.26> WP: Write Protect
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195 ;// <o1.27> BM: Burst ROM
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196 ;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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197 ;// <2=> 32-bit <3=> Reserved
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200 BCFG2_Val EQU 0x0000FBEF
\r
202 ;// <e> Bank Configuration 3 (BCFG3)
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203 ;// <o1.0..3> IDCY: Idle Cycles <0-15>
\r
204 ;// <o1.5..9> WST1: Wait States 1 <0-31>
\r
205 ;// <o1.11..15> WST2: Wait States 2 <0-31>
\r
206 ;// <o1.10> RBLE: Read Byte Lane Enable
\r
207 ;// <o1.26> WP: Write Protect
\r
208 ;// <o1.27> BM: Burst ROM
\r
209 ;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
\r
210 ;// <2=> 32-bit <3=> Reserved
\r
213 BCFG3_Val EQU 0x0000FBEF
\r
215 ;// </e> End of EMC
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218 ; External Memory Pins definitions
\r
219 PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
\r
220 PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
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221 ; D0..31, A2..23, JTAG Pins
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227 ; Area Definition and Entry Point
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228 ; Startup Code must be linked first at Address at which it expects to run.
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230 AREA RESET, CODE, READONLY
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234 ; Exception Vectors
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235 ; Mapped to Address 0.
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236 ; Absolute addressing mode must be used.
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237 ; Dummy Handlers are implemented as infinite loops which can be modified.
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238 IMPORT vPortYieldProcessor
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240 Vectors LDR PC, Reset_Addr
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245 NOP ; Reserved Vector
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247 LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
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250 Reset_Addr DCD Reset_Handler
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251 Undef_Addr DCD Undef_Handler
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252 SWI_Addr DCD vPortYieldProcessor
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253 PAbt_Addr DCD PAbt_Handler
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254 DAbt_Addr DCD DAbt_Handler
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255 DCD 0 ; Reserved Address
\r
256 IRQ_Addr DCD IRQ_Handler
\r
257 FIQ_Addr DCD FIQ_Handler
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259 Undef_Handler B Undef_Handler
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260 SWI_Handler B SWI_Handler
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261 PAbt_Handler B PAbt_Handler
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262 DAbt_Handler B DAbt_Handler
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263 IRQ_Handler B IRQ_Handler
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264 FIQ_Handler B FIQ_Handler
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269 EXPORT Reset_Handler
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273 ; Setup External Memory Pins
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274 IF :DEF:EXTERNAL_MODE
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276 LDR R1, =PINSEL2_Val
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281 ; Setup External Memory Controller
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285 IF BCFG0_SETUP <> 0
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287 STR R1, [R0, #BCFG0_OFS]
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290 IF BCFG1_SETUP <> 0
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292 STR R1, [R0, #BCFG1_OFS]
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295 IF BCFG2_SETUP <> 0
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297 STR R1, [R0, #BCFG2_OFS]
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300 IF BCFG3_SETUP <> 0
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302 STR R1, [R0, #BCFG3_OFS]
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309 IF VPBDIV_SETUP <> 0
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311 LDR R1, =VPBDIV_Val
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322 ; Configure and Enable PLL
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323 MOV R3, #PLLCFG_Val
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324 STR R3, [R0, #PLLCFG_OFS]
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325 MOV R3, #PLLCON_PLLE
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326 STR R3, [R0, #PLLCON_OFS]
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327 STR R1, [R0, #PLLFEED_OFS]
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328 STR R2, [R0, #PLLFEED_OFS]
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330 ; Wait until PLL Locked
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331 PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
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332 ANDS R3, R3, #PLLSTAT_PLOCK
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335 ; Switch to PLL Clock
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336 MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
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337 STR R3, [R0, #PLLCON_OFS]
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338 STR R1, [R0, #PLLFEED_OFS]
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339 STR R2, [R0, #PLLFEED_OFS]
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346 MOV R1, #MAMTIM_Val
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347 STR R1, [R0, #MAMTIM_OFS]
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349 STR R1, [R0, #MAMCR_OFS]
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353 ; Memory Mapping (when Interrupt Vectors are in RAM)
\r
354 MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
\r
357 IF :DEF:EXTMEM_MODE
\r
368 ; Initialise Interrupt System
\r
372 ; Setup Stack for each mode
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376 ; Enter Undefined Instruction Mode and set its Stack Pointer
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377 MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
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379 SUB R0, R0, #UND_Stack_Size
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381 ; Enter Abort Mode and set its Stack Pointer
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382 MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
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384 SUB R0, R0, #ABT_Stack_Size
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386 ; Enter FIQ Mode and set its Stack Pointer
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387 MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
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389 SUB R0, R0, #FIQ_Stack_Size
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391 ; Enter IRQ Mode and set its Stack Pointer
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392 MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
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394 SUB R0, R0, #IRQ_Stack_Size
\r
396 ; Enter Supervisor Mode and set its Stack Pointer
\r
397 MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
\r
399 SUB R0, R0, #SVC_Stack_Size
\r
411 EXPORT __heap_limit
\r
414 ; User Initial Stack & Heap
\r
415 AREA |.text|, CODE, READONLY
\r
417 IMPORT __use_two_region_memory
\r
418 EXPORT __user_initial_stackheap
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419 __user_initial_stackheap
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422 LDR R1, =(Stack_Mem + USR_Stack_Size)
\r
423 LDR R2, = (Heap_Mem + Heap_Size)
\r
424 LDR R3, = Stack_Mem
\r