1 /*****************************************************************************
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6 * Function : register definitions
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7 * Designer : K. Sterckx
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8 * Creation date : 22/01/2007
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10 * Processor : LPC23xx
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15 *****************************************************************************
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17 * Hardware specific macro's and defines
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19 ****************************************************************************/
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24 /* Vectored Interrupt Controller (VIC) */
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25 #define VIC_BASE_ADDR 0xFFFFF000
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26 #define VICIRQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x000))
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27 #define VICFIQStatus (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x004))
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28 #define VICRawIntr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x008))
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29 #define VICIntSelect (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x00C))
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30 #define VICIntEnable (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x010))
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31 #define VICIntEnClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x014))
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32 #define VICSoftInt (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x018))
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33 #define VICSoftIntClr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x01C))
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34 #define VICProtection (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x020))
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35 #define VICSWPrioMask (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x024))
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37 #define VICVectAddr0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x100))
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38 #define VICVectAddr1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x104))
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39 #define VICVectAddr2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x108))
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40 #define VICVectAddr3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x10C))
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41 #define VICVectAddr4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x110))
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42 #define VICVectAddr5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x114))
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43 #define VICVectAddr6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x118))
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44 #define VICVectAddr7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x11C))
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45 #define VICVectAddr8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x120))
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46 #define VICVectAddr9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x124))
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47 #define VICVectAddr10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x128))
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48 #define VICVectAddr11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x12C))
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49 #define VICVectAddr12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x130))
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50 #define VICVectAddr13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x134))
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51 #define VICVectAddr14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x138))
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52 #define VICVectAddr15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x13C))
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53 #define VICVectAddr16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x140))
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54 #define VICVectAddr17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x144))
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55 #define VICVectAddr18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x148))
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56 #define VICVectAddr19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x14C))
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57 #define VICVectAddr20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x150))
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58 #define VICVectAddr21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x154))
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59 #define VICVectAddr22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x158))
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60 #define VICVectAddr23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x15C))
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61 #define VICVectAddr24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x160))
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62 #define VICVectAddr25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x164))
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63 #define VICVectAddr26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x168))
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64 #define VICVectAddr27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x16C))
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65 #define VICVectAddr28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x170))
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66 #define VICVectAddr29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x174))
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67 #define VICVectAddr30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x178))
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68 #define VICVectAddr31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x17C))
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70 /* The name convention below is from previous LPC2000 family MCUs, in LPC230x,
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71 these registers are known as "VICVectPriority(x)". */
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72 #define VICVectCntl0 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x200))
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73 #define VICVectCntl1 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x204))
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74 #define VICVectCntl2 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x208))
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75 #define VICVectCntl3 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x20C))
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76 #define VICVectCntl4 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x210))
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77 #define VICVectCntl5 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x214))
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78 #define VICVectCntl6 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x218))
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79 #define VICVectCntl7 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x21C))
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80 #define VICVectCntl8 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x220))
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81 #define VICVectCntl9 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x224))
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82 #define VICVectCntl10 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x228))
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83 #define VICVectCntl11 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x22C))
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84 #define VICVectCntl12 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x230))
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85 #define VICVectCntl13 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x234))
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86 #define VICVectCntl14 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x238))
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87 #define VICVectCntl15 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x23C))
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88 #define VICVectCntl16 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x240))
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89 #define VICVectCntl17 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x244))
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90 #define VICVectCntl18 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x248))
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91 #define VICVectCntl19 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x24C))
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92 #define VICVectCntl20 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x250))
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93 #define VICVectCntl21 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x254))
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94 #define VICVectCntl22 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x258))
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95 #define VICVectCntl23 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x25C))
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96 #define VICVectCntl24 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x260))
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97 #define VICVectCntl25 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x264))
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98 #define VICVectCntl26 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x268))
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99 #define VICVectCntl27 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x26C))
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100 #define VICVectCntl28 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x270))
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101 #define VICVectCntl29 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x274))
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102 #define VICVectCntl30 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x278))
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103 #define VICVectCntl31 (*(volatile unsigned int *)(VIC_BASE_ADDR + 0x27C))
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105 #define VICVectAddr (*(volatile unsigned int *)(VIC_BASE_ADDR + 0xF00))
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108 /* Pin Connect Block */
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109 #define PINSEL_BASE_ADDR 0xE002C000
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110 #define PINSEL0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x00))
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111 #define PINSEL1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x04))
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112 #define PINSEL2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x08))
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113 #define PINSEL3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x0C))
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114 #define PINSEL4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x10))
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115 #define PINSEL5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x14))
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116 #define PINSEL6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x18))
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117 #define PINSEL7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x1C))
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118 #define PINSEL8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x20))
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119 #define PINSEL9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x24))
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120 #define PINSEL10 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x28))
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122 #define PINMODE0 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x40))
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123 #define PINMODE1 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x44))
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124 #define PINMODE2 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x48))
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125 #define PINMODE3 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x4C))
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126 #define PINMODE4 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x50))
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127 #define PINMODE5 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x54))
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128 #define PINMODE6 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x58))
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129 #define PINMODE7 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x5C))
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130 #define PINMODE8 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x60))
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131 #define PINMODE9 (*(volatile unsigned int *)(PINSEL_BASE_ADDR + 0x64))
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133 /* General Purpose Input/Output (GPIO) */
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134 #define GPIO_BASE_ADDR 0xE0028000
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135 #define IOPIN0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x00))
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136 #define IOSET0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x04))
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137 #define IODIR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x08))
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138 #define IOCLR0 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x0C))
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139 #define IOPIN1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x10))
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140 #define IOSET1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x14))
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141 #define IODIR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x18))
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142 #define IOCLR1 (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x1C))
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144 /* GPIO Interrupt Registers */
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145 #define IO0_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x90))
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146 #define IO0_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x94))
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147 #define IO0_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x84))
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148 #define IO0_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x88))
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149 #define IO0_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x8C))
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151 #define IO2_INT_EN_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB0))
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152 #define IO2_INT_EN_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xB4))
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153 #define IO2_INT_STAT_R (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA4))
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154 #define IO2_INT_STAT_F (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xA8))
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155 #define IO2_INT_CLR (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0xAC))
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157 #define IO_INT_STAT (*(volatile unsigned int *)(GPIO_BASE_ADDR + 0x80))
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159 #define PARTCFG_BASE_ADDR 0x3FFF8000
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160 #define PARTCFG (*(volatile unsigned int *)(PARTCFG_BASE_ADDR + 0x00))
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162 /* Fast I/O setup */
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163 #define FIO_BASE_ADDR 0x3FFFC000
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164 #define FIO0DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x00))
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165 #define FIO0MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x10))
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166 #define FIO0PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x14))
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167 #define FIO0SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x18))
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168 #define FIO0CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x1C))
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170 #define FIO1DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x20))
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171 #define FIO1MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x30))
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172 #define FIO1PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x34))
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173 #define FIO1SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x38))
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174 #define FIO1CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x3C))
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176 #define FIO2DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x40))
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177 #define FIO2MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x50))
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178 #define FIO2PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x54))
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179 #define FIO2SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x58))
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180 #define FIO2CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x5C))
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182 #define FIO3DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x60))
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183 #define FIO3MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x70))
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184 #define FIO3PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x74))
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185 #define FIO3SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x78))
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186 #define FIO3CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x7C))
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188 #define FIO4DIR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x80))
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189 #define FIO4MASK (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x90))
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190 #define FIO4PIN (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x94))
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191 #define FIO4SET (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x98))
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192 #define FIO4CLR (*(volatile unsigned int *)(FIO_BASE_ADDR + 0x9C))
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194 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
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195 #define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
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196 #define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
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197 #define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
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198 #define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
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199 #define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
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201 #define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
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202 #define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
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203 #define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
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204 #define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
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205 #define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
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207 #define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
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208 #define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
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209 #define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
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210 #define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
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211 #define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
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213 #define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x04))
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214 #define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x24))
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215 #define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x44))
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216 #define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x64))
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217 #define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x84))
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219 #define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
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220 #define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
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221 #define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
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222 #define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
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223 #define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
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225 #define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
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226 #define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
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227 #define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
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228 #define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
\r
229 #define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
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231 #define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
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232 #define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
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233 #define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
\r
234 #define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
\r
235 #define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
\r
237 #define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
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238 #define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
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239 #define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
\r
240 #define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
\r
241 #define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
\r
243 #define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
\r
244 #define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
\r
245 #define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
\r
246 #define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
\r
247 #define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
\r
249 #define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
\r
250 #define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
\r
251 #define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
\r
252 #define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
\r
253 #define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
\r
255 #define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
\r
256 #define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
\r
257 #define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
\r
258 #define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
\r
259 #define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
\r
261 #define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
\r
262 #define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
\r
263 #define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
\r
264 #define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
\r
265 #define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
\r
267 #define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
\r
268 #define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
\r
269 #define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
\r
270 #define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
\r
271 #define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
\r
273 #define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
\r
274 #define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25))
\r
275 #define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
\r
276 #define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
\r
277 #define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
\r
279 #define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
\r
280 #define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
\r
281 #define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
\r
282 #define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
\r
283 #define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
\r
285 #define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
\r
286 #define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
\r
287 #define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
\r
288 #define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
\r
289 #define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
\r
291 #define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
\r
292 #define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
\r
293 #define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
\r
294 #define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
\r
295 #define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
\r
297 #define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
\r
298 #define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
\r
299 #define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
\r
300 #define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
\r
301 #define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
\r
303 #define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
\r
304 #define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
\r
305 #define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
\r
306 #define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
\r
307 #define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
\r
309 #define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
\r
310 #define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29))
\r
311 #define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
\r
312 #define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
\r
313 #define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
\r
315 #define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
\r
316 #define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
\r
317 #define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
\r
318 #define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
\r
319 #define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
\r
321 #define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
\r
322 #define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
\r
323 #define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
\r
324 #define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
\r
325 #define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
\r
327 #define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
\r
328 #define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
\r
329 #define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
\r
330 #define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
\r
331 #define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
\r
333 #define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
\r
334 #define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
\r
335 #define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
\r
336 #define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
\r
337 #define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
\r
339 #define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
\r
340 #define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
\r
341 #define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
\r
342 #define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
\r
343 #define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
\r
345 #define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
\r
346 #define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D))
\r
347 #define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
\r
348 #define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
\r
349 #define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
\r
351 #define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
\r
352 #define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
\r
353 #define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
\r
354 #define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
\r
355 #define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
\r
357 #define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
\r
358 #define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
\r
359 #define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
\r
360 #define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
\r
361 #define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
\r
363 #define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
\r
364 #define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
\r
365 #define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
\r
366 #define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
\r
367 #define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
\r
369 #define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
\r
370 #define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
\r
371 #define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
\r
372 #define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
\r
373 #define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
\r
376 /* System Control Block(SCB) modules include Memory Accelerator Module,
\r
377 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
\r
378 Reset, and Code Security/Debugging */
\r
379 #define SCB_BASE_ADDR 0xE01FC000
\r
381 /* Memory Accelerator Module (MAM) */
\r
382 #define MAMCR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x000))
\r
383 #define MAMTIM (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x004))
\r
384 #define MEMMAP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x040))
\r
386 /* Phase Locked Loop (PLL) */
\r
387 #define PLLCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x080))
\r
388 #define PLLCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x084))
\r
389 #define PLLSTAT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x088))
\r
390 #define PLLFEED (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x08C))
\r
392 /* Power Control */
\r
393 #define PCON (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C0))
\r
394 #define PCONP (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x0C4))
\r
396 /* Clock Divider */
\r
397 #define APBDIV (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x100))
\r
398 #define CCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x104))
\r
399 #define USBCLKCFG (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x108))
\r
400 #define CLKSRCSEL (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x10C))
\r
401 #define PCLKSEL0 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A8))
\r
402 #define PCLKSEL1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1AC))
\r
404 /* External Interrupts */
\r
405 #define EXTINT (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x140))
\r
406 #define INTWAKE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x144))
\r
407 #define EXTMODE (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x148))
\r
408 #define EXTPOLAR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x14C))
\r
410 /* Reset, reset source identification */
\r
411 #define RSIR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x180))
\r
413 /* RSID, code security protection */
\r
414 #define CSPR (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x184))
\r
416 /* AHB configuration */
\r
417 #define AHBCFG1 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x188))
\r
418 #define AHBCFG2 (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x18C))
\r
420 /* System Controls and Status */
\r
421 #define SCS (*(volatile unsigned int *)(SCB_BASE_ADDR + 0x1A0))
\r
423 /*MPMC(EMC) registers*/
\r
424 #define STATIC_MEM0_BASE 0x80000000
\r
425 #define STATIC_MEM1_BASE 0x81000000
\r
426 #define STATIC_MEM2_BASE 0x82000000
\r
427 #define STATIC_MEM3_BASE 0x83000000
\r
429 #define DYNAMIC_MEM0_BASE 0xA0000000
\r
430 #define DYNAMIC_MEM1_BASE 0xB0000000
\r
431 #define DYNAMIC_MEM2_BASE 0xC0000000
\r
432 #define DYNAMIC_MEM3_BASE 0xD0000000
\r
434 /* External Memory Controller (EMC) */
\r
435 #define EMC_BASE_ADDR 0xFFE08000
\r
436 #define EMC_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x000))
\r
437 #define EMC_STAT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x004))
\r
438 #define EMC_CONFIG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x008))
\r
440 /* Dynamic RAM access registers */
\r
441 #define EMC_DYN_CTRL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x020))
\r
442 #define EMC_DYN_RFSH (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x024))
\r
443 #define EMC_DYN_RD_CFG (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x028))
\r
444 #define EMC_DYN_RP (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x030))
\r
445 #define EMC_DYN_RAS (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x034))
\r
446 #define EMC_DYN_SREX (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x038))
\r
447 #define EMC_DYN_APR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x03C))
\r
448 #define EMC_DYN_DAL (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x040))
\r
449 #define EMC_DYN_WR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x044))
\r
450 #define EMC_DYN_RC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x048))
\r
451 #define EMC_DYN_RFC (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x04C))
\r
452 #define EMC_DYN_XSR (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x050))
\r
453 #define EMC_DYN_RRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x054))
\r
454 #define EMC_DYN_MRD (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x058))
\r
456 #define EMC_DYN_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x100))
\r
457 #define EMC_DYN_RASCAS0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x104))
\r
458 #define EMC_DYN_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x140))
\r
459 #define EMC_DYN_RASCAS1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x144))
\r
460 #define EMC_DYN_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x160))
\r
461 #define EMC_DYN_RASCAS2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x164))
\r
462 #define EMC_DYN_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x180))
\r
463 #define EMC_DYN_RASCAS3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x184))
\r
465 /* static RAM access registers */
\r
466 #define EMC_STA_CFG0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x200))
\r
467 #define EMC_STA_WAITWEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x204))
\r
468 #define EMC_STA_WAITOEN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x208))
\r
469 #define EMC_STA_WAITRD0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x20C))
\r
470 #define EMC_STA_WAITPAGE0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x210))
\r
471 #define EMC_STA_WAITWR0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x214))
\r
472 #define EMC_STA_WAITTURN0 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x218))
\r
474 #define EMC_STA_CFG1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x220))
\r
475 #define EMC_STA_WAITWEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x224))
\r
476 #define EMC_STA_WAITOEN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x228))
\r
477 #define EMC_STA_WAITRD1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x22C))
\r
478 #define EMC_STA_WAITPAGE1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x230))
\r
479 #define EMC_STA_WAITWR1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x234))
\r
480 #define EMC_STA_WAITTURN1 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x238))
\r
482 #define EMC_STA_CFG2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x240))
\r
483 #define EMC_STA_WAITWEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x244))
\r
484 #define EMC_STA_WAITOEN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x248))
\r
485 #define EMC_STA_WAITRD2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x24C))
\r
486 #define EMC_STA_WAITPAGE2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x250))
\r
487 #define EMC_STA_WAITWR2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x254))
\r
488 #define EMC_STA_WAITTURN2 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x258))
\r
490 #define EMC_STA_CFG3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x260))
\r
491 #define EMC_STA_WAITWEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x264))
\r
492 #define EMC_STA_WAITOEN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x268))
\r
493 #define EMC_STA_WAITRD3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x26C))
\r
494 #define EMC_STA_WAITPAGE3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x270))
\r
495 #define EMC_STA_WAITWR3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x274))
\r
496 #define EMC_STA_WAITTURN3 (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x278))
\r
498 #define EMC_STA_EXT_WAIT (*(volatile unsigned int *)(EMC_BASE_ADDR + 0x880))
\r
502 #define TMR0_BASE_ADDR 0xE0004000
\r
503 #define T0IR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x00))
\r
504 #define T0TCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x04))
\r
505 #define T0TC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x08))
\r
506 #define T0PR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x0C))
\r
507 #define T0PC (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x10))
\r
508 #define T0MCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x14))
\r
509 #define T0MR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x18))
\r
510 #define T0MR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x1C))
\r
511 #define T0MR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x20))
\r
512 #define T0MR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x24))
\r
513 #define T0CCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x28))
\r
514 #define T0CR0 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x2C))
\r
515 #define T0CR1 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x30))
\r
516 #define T0CR2 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x34))
\r
517 #define T0CR3 (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x38))
\r
518 #define T0EMR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x3C))
\r
519 #define T0CTCR (*(volatile unsigned int *)(TMR0_BASE_ADDR + 0x70))
\r
522 #define TMR1_BASE_ADDR 0xE0008000
\r
523 #define T1IR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x00))
\r
524 #define T1TCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x04))
\r
525 #define T1TC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x08))
\r
526 #define T1PR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x0C))
\r
527 #define T1PC (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x10))
\r
528 #define T1MCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x14))
\r
529 #define T1MR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x18))
\r
530 #define T1MR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x1C))
\r
531 #define T1MR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x20))
\r
532 #define T1MR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x24))
\r
533 #define T1CCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x28))
\r
534 #define T1CR0 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x2C))
\r
535 #define T1CR1 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x30))
\r
536 #define T1CR2 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x34))
\r
537 #define T1CR3 (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x38))
\r
538 #define T1EMR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x3C))
\r
539 #define T1CTCR (*(volatile unsigned int *)(TMR1_BASE_ADDR + 0x70))
\r
542 #define TMR2_BASE_ADDR 0xE0070000
\r
543 #define T2IR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x00))
\r
544 #define T2TCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x04))
\r
545 #define T2TC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x08))
\r
546 #define T2PR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x0C))
\r
547 #define T2PC (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x10))
\r
548 #define T2MCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x14))
\r
549 #define T2MR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x18))
\r
550 #define T2MR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x1C))
\r
551 #define T2MR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x20))
\r
552 #define T2MR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x24))
\r
553 #define T2CCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x28))
\r
554 #define T2CR0 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x2C))
\r
555 #define T2CR1 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x30))
\r
556 #define T2CR2 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x34))
\r
557 #define T2CR3 (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x38))
\r
558 #define T2EMR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x3C))
\r
559 #define T2CTCR (*(volatile unsigned int *)(TMR2_BASE_ADDR + 0x70))
\r
562 #define TMR3_BASE_ADDR 0xE0074000
\r
563 #define T3IR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x00))
\r
564 #define T3TCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x04))
\r
565 #define T3TC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x08))
\r
566 #define T3PR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x0C))
\r
567 #define T3PC (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x10))
\r
568 #define T3MCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x14))
\r
569 #define T3MR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x18))
\r
570 #define T3MR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x1C))
\r
571 #define T3MR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x20))
\r
572 #define T3MR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x24))
\r
573 #define T3CCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x28))
\r
574 #define T3CR0 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x2C))
\r
575 #define T3CR1 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x30))
\r
576 #define T3CR2 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x34))
\r
577 #define T3CR3 (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x38))
\r
578 #define T3EMR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x3C))
\r
579 #define T3CTCR (*(volatile unsigned int *)(TMR3_BASE_ADDR + 0x70))
\r
582 /* Pulse Width Modulator (PWM) */
\r
583 #define PWM0_BASE_ADDR 0xE0014000
\r
584 #define PWM0IR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x00))
\r
585 #define PWM0TCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x04))
\r
586 #define PWM0TC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x08))
\r
587 #define PWM0PR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x0C))
\r
588 #define PWM0PC (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x10))
\r
589 #define PWM0MCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x14))
\r
590 #define PWM0MR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x18))
\r
591 #define PWM0MR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x1C))
\r
592 #define PWM0MR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x20))
\r
593 #define PWM0MR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x24))
\r
594 #define PWM0CCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x28))
\r
595 #define PWM0CR0 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x2C))
\r
596 #define PWM0CR1 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x30))
\r
597 #define PWM0CR2 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x34))
\r
598 #define PWM0CR3 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x38))
\r
599 #define PWM0EMR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x3C))
\r
600 #define PWM0MR4 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x40))
\r
601 #define PWM0MR5 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x44))
\r
602 #define PWM0MR6 (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x48))
\r
603 #define PWM0PCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x4C))
\r
604 #define PWM0LER (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x50))
\r
605 #define PWM0CTCR (*(volatile unsigned int *)(PWM0_BASE_ADDR + 0x70))
\r
607 #define PWM1_BASE_ADDR 0xE0018000
\r
608 #define PWM1IR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x00))
\r
609 #define PWM1TCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x04))
\r
610 #define PWM1TC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x08))
\r
611 #define PWM1PR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x0C))
\r
612 #define PWM1PC (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x10))
\r
613 #define PWM1MCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x14))
\r
614 #define PWM1MR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x18))
\r
615 #define PWM1MR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x1C))
\r
616 #define PWM1MR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x20))
\r
617 #define PWM1MR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x24))
\r
618 #define PWM1CCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x28))
\r
619 #define PWM1CR0 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x2C))
\r
620 #define PWM1CR1 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x30))
\r
621 #define PWM1CR2 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x34))
\r
622 #define PWM1CR3 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x38))
\r
623 #define PWM1EMR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x3C))
\r
624 #define PWM1MR4 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x40))
\r
625 #define PWM1MR5 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x44))
\r
626 #define PWM1MR6 (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x48))
\r
627 #define PWM1PCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x4C))
\r
628 #define PWM1LER (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x50))
\r
629 #define PWM1CTCR (*(volatile unsigned int *)(PWM1_BASE_ADDR + 0x70))
\r
632 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
\r
633 #define UART0_BASE_ADDR 0xE000C000
\r
634 #define U0RBR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))
\r
635 #define U0THR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))
\r
636 #define U0DLL (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x00))
\r
637 #define U0DLM (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04))
\r
638 #define U0IER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x04))
\r
639 #define U0IIR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08))
\r
640 #define U0FCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x08))
\r
641 #define U0LCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x0C))
\r
642 #define U0LSR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x14))
\r
643 #define U0SCR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x1C))
\r
644 #define U0ACR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x20))
\r
645 #define U0ICR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x24))
\r
646 #define U0FDR (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x28))
\r
647 #define U0TER (*(volatile unsigned int *)(UART0_BASE_ADDR + 0x30))
\r
649 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
\r
650 #define UART1_BASE_ADDR 0xE0010000
\r
651 #define U1RBR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))
\r
652 #define U1THR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))
\r
653 #define U1DLL (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x00))
\r
654 #define U1DLM (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04))
\r
655 #define U1IER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x04))
\r
656 #define U1IIR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08))
\r
657 #define U1FCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x08))
\r
658 #define U1LCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x0C))
\r
659 #define U1MCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x10))
\r
660 #define U1LSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x14))
\r
661 #define U1MSR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x18))
\r
662 #define U1SCR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x1C))
\r
663 #define U1ACR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x20))
\r
664 #define U1FDR (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x28))
\r
665 #define U1TER (*(volatile unsigned int *)(UART1_BASE_ADDR + 0x30))
\r
667 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
\r
668 #define UART2_BASE_ADDR 0xE0078000
\r
669 #define U2RBR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))
\r
670 #define U2THR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))
\r
671 #define U2DLL (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x00))
\r
672 #define U2DLM (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04))
\r
673 #define U2IER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x04))
\r
674 #define U2IIR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08))
\r
675 #define U2FCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x08))
\r
676 #define U2LCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x0C))
\r
677 #define U2LSR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x14))
\r
678 #define U2SCR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x1C))
\r
679 #define U2ACR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x20))
\r
680 #define U2ICR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x24))
\r
681 #define U2FDR (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x28))
\r
682 #define U2TER (*(volatile unsigned int *)(UART2_BASE_ADDR + 0x30))
\r
684 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
\r
685 #define UART3_BASE_ADDR 0xE007C000
\r
686 #define U3RBR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))
\r
687 #define U3THR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))
\r
688 #define U3DLL (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x00))
\r
689 #define U3DLM (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04))
\r
690 #define U3IER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x04))
\r
691 #define U3IIR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08))
\r
692 #define U3FCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x08))
\r
693 #define U3LCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x0C))
\r
694 #define U3LSR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x14))
\r
695 #define U3SCR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x1C))
\r
696 #define U3ACR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x20))
\r
697 #define U3ICR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x24))
\r
698 #define U3FDR (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x28))
\r
699 #define U3TER (*(volatile unsigned int *)(UART3_BASE_ADDR + 0x30))
\r
701 /* I2C Interface 0 */
\r
702 #define I2C0_BASE_ADDR 0xE001C000
\r
703 #define I20CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00))
\r
704 #define I20STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04))
\r
705 #define I20DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08))
\r
706 #define I20ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C))
\r
707 #define I20SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10))
\r
708 #define I20SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14))
\r
709 #define I20CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18))
\r
710 //Slightly different naming
\r
711 #define I2C0CONSET (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x00))
\r
712 #define I2C0STAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x04))
\r
713 #define I2C0DAT (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x08))
\r
714 #define I2C0ADR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x0C))
\r
715 #define I2C0SCLH (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x10))
\r
716 #define I2C0SCLL (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x14))
\r
717 #define I2C0CONCLR (*(volatile unsigned int *)(I2C0_BASE_ADDR + 0x18))
\r
720 /* I2C Interface 1 */
\r
721 #define I2C1_BASE_ADDR 0xE005C000
\r
722 #define I21CONSET (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x00))
\r
723 #define I21STAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x04))
\r
724 #define I21DAT (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x08))
\r
725 #define I21ADR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x0C))
\r
726 #define I21SCLH (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x10))
\r
727 #define I21SCLL (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x14))
\r
728 #define I21CONCLR (*(volatile unsigned int *)(I2C1_BASE_ADDR + 0x18))
\r
730 /* I2C Interface 2 */
\r
731 #define I2C2_BASE_ADDR 0xE0080000
\r
732 #define I22CONSET (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x00))
\r
733 #define I22STAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x04))
\r
734 #define I22DAT (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x08))
\r
735 #define I22ADR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x0C))
\r
736 #define I22SCLH (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x10))
\r
737 #define I22SCLL (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x14))
\r
738 #define I22CONCLR (*(volatile unsigned int *)(I2C2_BASE_ADDR + 0x18))
\r
740 /* SPI0 (Serial Peripheral Interface 0) */
\r
741 #define SPI0_BASE_ADDR 0xE0020000
\r
742 #define S0SPCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x00))
\r
743 #define S0SPSR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x04))
\r
744 #define S0SPDR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x08))
\r
745 #define S0SPCCR (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x0C))
\r
746 #define S0SPINT (*(volatile unsigned int *)(SPI0_BASE_ADDR + 0x1C))
\r
748 /* SSP0 Controller */
\r
749 #define SSP0_BASE_ADDR 0xE0068000
\r
750 #define SSP0CR0 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x00))
\r
751 #define SSP0CR1 (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x04))
\r
752 #define SSP0DR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x08))
\r
753 #define SSP0SR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x0C))
\r
754 #define SSP0CPSR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x10))
\r
755 #define SSP0IMSC (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x14))
\r
756 #define SSP0RIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x18))
\r
757 #define SSP0MIS (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x1C))
\r
758 #define SSP0ICR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x20))
\r
759 #define SSP0DMACR (*(volatile unsigned int *)(SSP0_BASE_ADDR + 0x24))
\r
761 /* SSP1 Controller */
\r
762 #define SSP1_BASE_ADDR 0xE0030000
\r
763 #define SSP1CR0 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x00))
\r
764 #define SSP1CR1 (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x04))
\r
765 #define SSP1DR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x08))
\r
766 #define SSP1SR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x0C))
\r
767 #define SSP1CPSR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x10))
\r
768 #define SSP1IMSC (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x14))
\r
769 #define SSP1RIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x18))
\r
770 #define SSP1MIS (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x1C))
\r
771 #define SSP1ICR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x20))
\r
772 #define SSP1DMACR (*(volatile unsigned int *)(SSP1_BASE_ADDR + 0x24))
\r
775 /* Real Time Clock */
\r
776 #define RTC_BASE_ADDR 0xE0024000
\r
777 #define RTC_ILR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x00))
\r
778 #define RTC_CTC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x04))
\r
779 #define RTC_CCR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x08))
\r
780 #define RTC_CIIR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x0C))
\r
781 #define RTC_AMR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x10))
\r
782 #define RTC_CTIME0 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x14))
\r
783 #define RTC_CTIME1 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x18))
\r
784 #define RTC_CTIME2 (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x1C))
\r
785 #define RTC_SEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x20))
\r
786 #define RTC_MIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x24))
\r
787 #define RTC_HOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x28))
\r
788 #define RTC_DOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x2C))
\r
789 #define RTC_DOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x30))
\r
790 #define RTC_DOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x34))
\r
791 #define RTC_MONTH (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x38))
\r
792 #define RTC_YEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x3C))
\r
793 #define RTC_CISS (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x40))
\r
794 #define RTC_ALSEC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x60))
\r
795 #define RTC_ALMIN (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x64))
\r
796 #define RTC_ALHOUR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x68))
\r
797 #define RTC_ALDOM (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x6C))
\r
798 #define RTC_ALDOW (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x70))
\r
799 #define RTC_ALDOY (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x74))
\r
800 #define RTC_ALMON (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x78))
\r
801 #define RTC_ALYEAR (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x7C))
\r
802 #define RTC_PREINT (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x80))
\r
803 #define RTC_PREFRAC (*(volatile unsigned int *)(RTC_BASE_ADDR + 0x84))
\r
806 /* A/D Converter 0 (AD0) */
\r
807 #define AD0_BASE_ADDR 0xE0034000
\r
808 #define AD0CR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x00))
\r
809 #define AD0GDR (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x04))
\r
810 #define AD0INTEN (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x0C))
\r
811 #define AD0DR0 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x10))
\r
812 #define AD0DR1 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x14))
\r
813 #define AD0DR2 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x18))
\r
814 #define AD0DR3 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x1C))
\r
815 #define AD0DR4 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x20))
\r
816 #define AD0DR5 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x24))
\r
817 #define AD0DR6 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x28))
\r
818 #define AD0DR7 (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x2C))
\r
819 #define AD0STAT (*(volatile unsigned int *)(AD0_BASE_ADDR + 0x30))
\r
822 /* D/A Converter */
\r
823 #define DAC_BASE_ADDR 0xE006C000
\r
824 #define DACR (*(volatile unsigned int *)(DAC_BASE_ADDR + 0x00))
\r
828 #define WDG_BASE_ADDR 0xE0000000
\r
829 #define WDMOD (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x00))
\r
830 #define WDTC (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x04))
\r
831 #define WDFEED (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x08))
\r
832 #define WDTV (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x0C))
\r
833 #define WDCLKSEL (*(volatile unsigned int *)(WDG_BASE_ADDR + 0x10))
\r
835 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
\r
836 #define CAN_ACCEPT_BASE_ADDR 0xE003C000
\r
837 #define CAN_AFMR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x00))
\r
838 #define CAN_SFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x04))
\r
839 #define CAN_SFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x08))
\r
840 #define CAN_EFF_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
\r
841 #define CAN_EFF_GRP_SA (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x10))
\r
842 #define CAN_EOT (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x14))
\r
843 #define CAN_LUT_ERR_ADR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x18))
\r
844 #define CAN_LUT_ERR (*(volatile unsigned int *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
\r
846 #define CAN_CENTRAL_BASE_ADDR 0xE0040000
\r
847 #define CAN_TX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x00))
\r
848 #define CAN_RX_SR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x04))
\r
849 #define CAN_MSR (*(volatile unsigned int *)(CAN_CENTRAL_BASE_ADDR + 0x08))
\r
851 #define CAN1_BASE_ADDR 0xE0044000
\r
852 #define CAN1MOD (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x00))
\r
853 #define CAN1CMR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x04))
\r
854 #define CAN1GSR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x08))
\r
855 #define CAN1ICR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x0C))
\r
856 #define CAN1IER (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x10))
\r
857 #define CAN1BTR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x14))
\r
858 #define CAN1EWL (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x18))
\r
859 #define CAN1SR (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x1C))
\r
860 #define CAN1RFS (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x20))
\r
861 #define CAN1RID (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x24))
\r
862 #define CAN1RDA (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x28))
\r
863 #define CAN1RDB (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x2C))
\r
865 #define CAN1TFI1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x30))
\r
866 #define CAN1TID1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x34))
\r
867 #define CAN1TDA1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x38))
\r
868 #define CAN1TDB1 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x3C))
\r
869 #define CAN1TFI2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x40))
\r
870 #define CAN1TID2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x44))
\r
871 #define CAN1TDA2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x48))
\r
872 #define CAN1TDB2 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x4C))
\r
873 #define CAN1TFI3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x50))
\r
874 #define CAN1TID3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x54))
\r
875 #define CAN1TDA3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x58))
\r
876 #define CAN1TDB3 (*(volatile unsigned int *)(CAN1_BASE_ADDR + 0x5C))
\r
878 #define CAN2_BASE_ADDR 0xE0048000
\r
879 #define CAN2MOD (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x00))
\r
880 #define CAN2CMR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x04))
\r
881 #define CAN2GSR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x08))
\r
882 #define CAN2ICR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x0C))
\r
883 #define CAN2IER (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x10))
\r
884 #define CAN2BTR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x14))
\r
885 #define CAN2EWL (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x18))
\r
886 #define CAN2SR (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x1C))
\r
887 #define CAN2RFS (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x20))
\r
888 #define CAN2RID (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x24))
\r
889 #define CAN2RDA (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x28))
\r
890 #define CAN2RDB (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x2C))
\r
892 #define CAN2TFI1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x30))
\r
893 #define CAN2TID1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x34))
\r
894 #define CAN2TDA1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x38))
\r
895 #define CAN2TDB1 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x3C))
\r
896 #define CAN2TFI2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x40))
\r
897 #define CAN2TID2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x44))
\r
898 #define CAN2TDA2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x48))
\r
899 #define CAN2TDB2 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x4C))
\r
900 #define CAN2TFI3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x50))
\r
901 #define CAN2TID3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x54))
\r
902 #define CAN2TDA3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x58))
\r
903 #define CAN2TDB3 (*(volatile unsigned int *)(CAN2_BASE_ADDR + 0x5C))
\r
906 /* MultiMedia Card Interface(MCI) Controller */
\r
907 #define MCI_BASE_ADDR 0xE008C000
\r
908 #define MCI_POWER (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x00))
\r
909 #define MCI_CLOCK (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x04))
\r
910 #define MCI_ARGUMENT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x08))
\r
911 #define MCI_COMMAND (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x0C))
\r
912 #define MCI_RESP_CMD (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x10))
\r
913 #define MCI_RESP0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x14))
\r
914 #define MCI_RESP1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x18))
\r
915 #define MCI_RESP2 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x1C))
\r
916 #define MCI_RESP3 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x20))
\r
917 #define MCI_DATA_TMR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x24))
\r
918 #define MCI_DATA_LEN (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x28))
\r
919 #define MCI_DATA_CTRL (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x2C))
\r
920 #define MCI_DATA_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x30))
\r
921 #define MCI_STATUS (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x34))
\r
922 #define MCI_CLEAR (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x38))
\r
923 #define MCI_MASK0 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x3C))
\r
924 #define MCI_MASK1 (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x40))
\r
925 #define MCI_FIFO_CNT (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x48))
\r
926 #define MCI_FIFO (*(volatile unsigned int *)(MCI_BASE_ADDR + 0x80))
\r
929 /* I2S Interface Controller (I2S) */
\r
930 #define I2S_BASE_ADDR 0xE0088000
\r
931 #define I2S_DAO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x00))
\r
932 #define I2S_DAI (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x04))
\r
933 #define I2S_TX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x08))
\r
934 #define I2S_RX_FIFO (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x0C))
\r
935 #define I2S_STATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x10))
\r
936 #define I2S_DMA1 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x14))
\r
937 #define I2S_DMA2 (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x18))
\r
938 #define I2S_IRQ (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x1C))
\r
939 #define I2S_TXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x20))
\r
940 #define I2S_RXRATE (*(volatile unsigned int *)(I2S_BASE_ADDR + 0x24))
\r
943 /* General-purpose DMA Controller */
\r
944 #define DMA_BASE_ADDR 0xFFE04000
\r
945 #define GPDMA_INT_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x000))
\r
946 #define GPDMA_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x004))
\r
947 #define GPDMA_INT_TCCLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x008))
\r
948 #define GPDMA_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x00C))
\r
949 #define GPDMA_INT_ERR_CLR (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x010))
\r
950 #define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x014))
\r
951 #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x018))
\r
952 #define GPDMA_ENABLED_CHNS (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x01C))
\r
953 #define GPDMA_SOFT_BREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x020))
\r
954 #define GPDMA_SOFT_SREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x024))
\r
955 #define GPDMA_SOFT_LBREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x028))
\r
956 #define GPDMA_SOFT_LSREQ (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x02C))
\r
957 #define GPDMA_CONFIG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x030))
\r
958 #define GPDMA_SYNC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x034))
\r
960 /* DMA channel 0 registers */
\r
961 #define GPDMA_CH0_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x100))
\r
962 #define GPDMA_CH0_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x104))
\r
963 #define GPDMA_CH0_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x108))
\r
964 #define GPDMA_CH0_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x10C))
\r
965 #define GPDMA_CH0_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x110))
\r
967 /* DMA channel 1 registers */
\r
968 #define GPDMA_CH1_SRC (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x120))
\r
969 #define GPDMA_CH1_DEST (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x124))
\r
970 #define GPDMA_CH1_LLI (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x128))
\r
971 #define GPDMA_CH1_CTRL (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x12C))
\r
972 #define GPDMA_CH1_CFG (*(volatile unsigned int *)(DMA_BASE_ADDR + 0x130))
\r
975 /* USB Controller */
\r
976 #define USB_INT_BASE_ADDR 0xE01FC1C0
\r
977 #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
\r
979 #define USB_INT_STAT (*(volatile unsigned int *)(USB_INT_BASE_ADDR + 0x00))
\r
981 /* USB Device Interrupt Registers */
\r
982 #define DEV_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x00))
\r
983 #define DEV_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x04))
\r
984 #define DEV_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x08))
\r
985 #define DEV_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x0C))
\r
986 #define DEV_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x2C))
\r
988 /* USB Device Endpoint Interrupt Registers */
\r
989 #define EP_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x30))
\r
990 #define EP_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x34))
\r
991 #define EP_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x38))
\r
992 #define EP_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x3C))
\r
993 #define EP_INT_PRIO (*(volatile unsigned int *)(USB_BASE_ADDR + 0x40))
\r
995 /* USB Device Endpoint Realization Registers */
\r
996 #define REALIZE_EP (*(volatile unsigned int *)(USB_BASE_ADDR + 0x44))
\r
997 #define EP_INDEX (*(volatile unsigned int *)(USB_BASE_ADDR + 0x48))
\r
998 #define MAXPACKET_SIZE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x4C))
\r
1000 /* USB Device Command Reagisters */
\r
1001 #define CMD_CODE (*(volatile unsigned int *)(USB_BASE_ADDR + 0x10))
\r
1002 #define CMD_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x14))
\r
1004 /* USB Device Data Transfer Registers */
\r
1005 #define RX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x18))
\r
1006 #define TX_DATA (*(volatile unsigned int *)(USB_BASE_ADDR + 0x1C))
\r
1007 #define RX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x20))
\r
1008 #define TX_PLENGTH (*(volatile unsigned int *)(USB_BASE_ADDR + 0x24))
\r
1009 #define USB_CTRL (*(volatile unsigned int *)(USB_BASE_ADDR + 0x28))
\r
1011 /* USB Device DMA Registers */
\r
1012 #define DMA_REQ_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x50))
\r
1013 #define DMA_REQ_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0x54))
\r
1014 #define DMA_REQ_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0x58))
\r
1015 #define UDCA_HEAD (*(volatile unsigned int *)(USB_BASE_ADDR + 0x80))
\r
1016 #define EP_DMA_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x84))
\r
1017 #define EP_DMA_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x88))
\r
1018 #define EP_DMA_DIS (*(volatile unsigned int *)(USB_BASE_ADDR + 0x8C))
\r
1019 #define DMA_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0x90))
\r
1020 #define DMA_INT_EN (*(volatile unsigned int *)(USB_BASE_ADDR + 0x94))
\r
1021 #define EOT_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA0))
\r
1022 #define EOT_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA4))
\r
1023 #define EOT_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xA8))
\r
1024 #define NDD_REQ_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xAC))
\r
1025 #define NDD_REQ_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB0))
\r
1026 #define NDD_REQ_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB4))
\r
1027 #define SYS_ERR_INT_STAT (*(volatile unsigned int *)(USB_BASE_ADDR + 0xB8))
\r
1028 #define SYS_ERR_INT_CLR (*(volatile unsigned int *)(USB_BASE_ADDR + 0xBC))
\r
1029 #define SYS_ERR_INT_SET (*(volatile unsigned int *)(USB_BASE_ADDR + 0xC0))
\r
1032 /* USB Host Controller */
\r
1033 #define USBHC_BASE_ADDR 0xFFE0C000
\r
1034 #define HC_REVISION (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x00))
\r
1035 #define HC_CONTROL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x04))
\r
1036 #define HC_CMD_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x08))
\r
1037 #define HC_INT_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x0C))
\r
1038 #define HC_INT_EN (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x10))
\r
1039 #define HC_INT_DIS (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x14))
\r
1040 #define HC_HCCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x18))
\r
1041 #define HC_PERIOD_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x1C))
\r
1042 #define HC_CTRL_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x20))
\r
1043 #define HC_CTRL_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x24))
\r
1044 #define HC_BULK_HEAD_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x28))
\r
1045 #define HC_BULK_CUR_ED (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x2C))
\r
1046 #define HC_DONE_HEAD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x30))
\r
1047 #define HC_FM_INTERVAL (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x34))
\r
1048 #define HC_FM_REMAINING (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x38))
\r
1049 #define HC_FM_NUMBER (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x3C))
\r
1050 #define HC_PERIOD_START (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x40))
\r
1051 #define HC_LS_THRHLD (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x44))
\r
1052 #define HC_RH_DESCA (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x48))
\r
1053 #define HC_RH_DESCB (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x4C))
\r
1054 #define HC_RH_STAT (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x50))
\r
1055 #define HC_RH_PORT_STAT1 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x54))
\r
1056 #define HC_RH_PORT_STAT2 (*(volatile unsigned int *)(USBHC_BASE_ADDR + 0x58))
\r
1058 /* USB OTG Controller */
\r
1059 #define USBOTG_BASE_ADDR 0xFFE0C100
\r
1060 #define OTG_INT_STAT (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x00))
\r
1061 #define OTG_INT_EN (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x04))
\r
1062 #define OTG_INT_SET (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x08))
\r
1063 #define OTG_INT_CLR (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x0C))
\r
1064 #define OTG_STAT_CTRL (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x10))
\r
1065 #define OTG_TIMER (*(volatile unsigned int *)(USBOTG_BASE_ADDR + 0x14))
\r
1067 #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
\r
1068 #define OTG_I2C_RX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00))
\r
1069 #define OTG_I2C_TX (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x00))
\r
1070 #define OTG_I2C_STS (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x04))
\r
1071 #define OTG_I2C_CTL (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x08))
\r
1072 #define OTG_I2C_CLKHI (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x0C))
\r
1073 #define OTG_I2C_CLKLO (*(volatile unsigned int *)(USBOTG_I2C_BASE_ADDR + 0x10))
\r
1075 #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
\r
1076 #define OTG_CLK_CTRL (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x04))
\r
1077 #define OTG_CLK_STAT (*(volatile unsigned int *)(USBOTG_CLK_BASE_ADDR + 0x08))
\r
1080 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
\r
1081 #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
\r
1082 #define MAC_MAC1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
\r
1083 #define MAC_MAC2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
\r
1084 #define MAC_IPGT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
\r
1085 #define MAC_IPGR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
\r
1086 #define MAC_CLRT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
\r
1087 #define MAC_MAXF (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
\r
1088 #define MAC_SUPP (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
\r
1089 #define MAC_TEST (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
\r
1090 #define MAC_MCFG (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
\r
1091 #define MAC_MCMD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
\r
1092 #define MAC_MADR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
\r
1093 #define MAC_MWTD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
\r
1094 #define MAC_MRDD (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
\r
1095 #define MAC_MIND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
\r
1097 #define MAC_SA0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
\r
1098 #define MAC_SA1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
\r
1099 #define MAC_SA2 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
\r
1101 #define MAC_COMMAND (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
\r
1102 #define MAC_STATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
\r
1103 #define MAC_RXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
\r
1104 #define MAC_RXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
\r
1105 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
\r
1106 #define MAC_RXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
\r
1107 #define MAC_RXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
\r
1108 #define MAC_TXDESCRIPTOR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
\r
1109 #define MAC_TXSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
\r
1110 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
\r
1111 #define MAC_TXPRODUCEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
\r
1112 #define MAC_TXCONSUMEINDEX (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
\r
1114 #define MAC_TSV0 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
\r
1115 #define MAC_TSV1 (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
\r
1116 #define MAC_RSV (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
\r
1118 #define MAC_FLOWCONTROLCNT (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
\r
1119 #define MAC_FLOWCONTROLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
\r
1121 #define MAC_RXFILTERCTRL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
\r
1122 #define MAC_RXFILTERWOLSTS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
\r
1123 #define MAC_RXFILTERWOLCLR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
\r
1125 #define MAC_HASHFILTERL (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
\r
1126 #define MAC_HASHFILTERH (*(volatile unsigned int *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
\r
1128 #define MAC_INTSTATUS (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
\r
1129 #define MAC_INTENABLE (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
\r
1130 #define MAC_INTCLEAR (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
\r
1131 #define MAC_INTSET (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
\r
1133 #define MAC_POWERDOWN (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
\r
1134 #define MAC_MODULEID (*(volatile unsigned int *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
\r
1137 #endif /* __LPC23xx_H */
\r