1 ;******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
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2 ;* File Name : 71x_init.s
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3 ;* Author : MCD Application Team
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4 ;* Date First Issued : 06/23/2004
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5 ;* Description : This is the first code executed after RESET.
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6 ;* This code used to initialize system stacks
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7 ;* and critical peripherals before entering the C code.
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8 ;*******************************************************************************
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10 ;* 13/01/2006 : V3.1
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11 ;* 24/05/2005 : V3.0
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12 ;* 30/11/2004 : V2.0
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13 ;* 14/07/2004 : V1.3
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14 ;* 01/01/2004 : V1.2
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15 ;*******************************************************************************
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16 ; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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17 ; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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18 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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19 ; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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20 ; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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21 ; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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22 ;*******************************************************************************/
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25 ; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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33 Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
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35 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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36 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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40 EIC_Base_addr EQU 0xFFFFF800; EIC base address
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41 ICR_off_addr EQU 0x00 ; Interrupt Control register offset
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42 CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset
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43 IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset
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44 FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset
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45 IER_off_addr EQU 0x20 ; Interrupt Enable Register offset
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46 IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset
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47 SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0
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49 EMI_Base_addr EQU 0x6C000000; EMI base address
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50 BCON0_off_addr EQU 0x00 ; Bank 0 configuration register offset
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51 BCON1_off_addr EQU 0x04 ; Bank 1 configuration register offset
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52 BCON2_off_addr EQU 0x08 ; Bank 2 configuration register offset
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53 BCON3_off_addr EQU 0x0C ; Bank 3 configuration register offset
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55 EMI_ENABLE EQU 0x8000
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56 EMI_SIZE_16 EQU 0x0001
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58 GPIO2_Base_addr EQU 0xE0005000; GPIO2 base address
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59 PC0_off_addr EQU 0x00 ; Port Configuration Register 0 offset
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60 PC1_off_addr EQU 0x04 ; Port Configuration Register 1 offset
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61 PC2_off_addr EQU 0x08 ; Port Configuration Register 2 offset
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62 PD_off_addr EQU 0x0C ; Port Data Register offset
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64 CPM_Base_addr EQU 0xA0000040; CPM Base Address
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65 BOOTCR_off_addr EQU 0x10 ; CPM - Boot Configuration Register
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66 FLASH_mask EQU 0x0000 ; to remap FLASH at 0x0
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67 RAM_mask EQU 0x0002 ; to remap RAM at 0x0
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69 ;|----------------------------------------------------------------------------------|
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70 ;| - APB Bridge (System Peripheral) |
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71 ;|----------------------------------------------------------------------------------|
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72 APB1_base_addr EQU 0xC0000000 ; APB Bridge1 Base Address
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73 APB2_base_addr EQU 0xE0000000 ; APB Bridge2 Base Address
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74 CKDIS_off_addr EQU 0x10 ; APB Bridge1 - Clock Disable Register
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75 SWRES_off_addr EQU 0x14 ; APB Bridge1 - Software Reset Register
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76 CKDIS1_config_all EQU 0x27FB ; To enable/disable clock of all APB1's peripherals
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77 SWRES1_config_all EQU 0x27FB ; To reset all APB1's peripherals
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78 CKDIS2_config_all EQU 0x7FDD ; To enable/disable clock of all APB2's peripherals
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79 SWRES2_config_all EQU 0x7FDD ; To reset all APB2's peripherals
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83 ;---------------------------------------------------------------
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85 ;---------------------------------------------------------------
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86 MODULE ?program_start
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87 SECTION IRQ_STACK:DATA:NOROOT(3)
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88 SECTION FIQ_STACK:DATA:NOROOT(3)
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89 SECTION UND_STACK:DATA:NOROOT(3)
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90 SECTION ABT_STACK:DATA:NOROOT(3)
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91 SECTION SVC_STACK:DATA:NOROOT(3)
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92 SECTION CSTACK:DATA:NOROOT(3)
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93 SECTION .text:CODE(2)
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94 PUBLIC __iar_program_start
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100 ;*******************************************************************************
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101 ;******* -- MACROS -- *******
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102 ;*******************************************************************************
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103 ;*******************************************************************************
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104 ;* Macro Name : EMI_INIT
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105 ;* Description : This macro Initialize EMI bank 1: 16-bit 7 wait state
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108 ;*******************************************************************************
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110 LDR r0, =GPIO2_Base_addr ; Configure P2.0 -> 3 in AF_PP mode
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111 LDR r2, [r0, #PC0_off_addr]
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112 ORR r2, r2,#0x0000000F
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113 STR r2, [r0, #PC0_off_addr]
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114 LDR r2, [r0, #PC1_off_addr]
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115 ORR r2, r2,#0x0000000F
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116 STR r2, [r0, #PC1_off_addr]
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117 LDR r2, [r0, #PC2_off_addr]
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118 ORR r2, r2,#0x0000000F
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119 STR r2, [r0, #PC2_off_addr]
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120 LDR r0, =EMI_Base_addr
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121 LDR r1, =0x18|EMI_ENABLE|EMI_SIZE_16
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122 STR r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state
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124 ;*******************************************************************************
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125 ;* Macro Name : EIC_INIT
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126 ;* Description : This macro Initialize the EIC as following :
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129 ; - IVR contain the load PC opcode (0xE59FFXXX)
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130 ; - Current priority level equal to 0
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131 ; - All channels are disabled
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132 ; - All channels priority equal to 0
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133 ; - All SIR registers contain offset to the related IRQ
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137 ;*******************************************************************************
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140 LDR r3, =EIC_Base_addr
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141 LDR r4, =0xE59F0000
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142 STR r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset]
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143 ; instruction code in IVR[31:16]
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144 LDR r2, =32 ; 32 Channel to initialize
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145 LDR r0, =T0TIMI_Addr ; Read the address of the IRQs
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147 LDR r1, =0x00000FFF
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149 LDR r5, =SIR0_off_addr ; Read SIR0 address
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150 SUB r4,r0,#8 ; subtract 8 for prefetch
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151 LDR r1, =0xF7E8 ; Add the offset from IVR to 0x00000000
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152 ; address(IVR address + 7E8 = 0x00000000)
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153 ; 0xF7E8 used to complete the
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154 ; LDR pc,[pc,#offset] opcode (0xE59FFXXX)
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155 ADD r1,r4,r1 ; Compute the jump offset from IVR to the
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157 EIC_INI MOV r4, r1, LSL #16 ; Left shift the result
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158 STR r4, [r3, r5] ; Store the result in SIRx register
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159 ADD r1, r1, #4 ; Next IRQ address
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160 ADD r5, r5, #4 ; Next SIR
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161 SUBS r2, r2, #1 ; Decrement the number of SIR registers
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163 BNE EIC_INI ; If more then continue
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165 ;*******************************************************************************
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166 ;* Macro Name : PERIPHERAL_INIT
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167 ;* Description : This macro reset all device peripherals.
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170 ;*******************************************************************************
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171 PERIPHERAL_INIT MACRO
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173 LDR r1, =APB1_base_addr ; r0= APB1 base address
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174 LDR r2, =APB2_base_addr ; r0= APB2 base address
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175 LDR r0, =CKDIS1_config_all
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176 STRH r0, [r1, #CKDIS_off_addr]; Clock Disabling for all APB1 peripherals
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177 LDR r0, =CKDIS2_config_all
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178 STRH r0, [r2, #CKDIS_off_addr]; Clock Disabling for all APB2 peripherals
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179 LDR r0, =SWRES1_config_all
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180 STRH r0, [r1, #SWRES_off_addr]; Keep all APB1 peripherals under reset
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181 LDR r0, =SWRES2_config_all
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182 STRH r0, [r2, #SWRES_off_addr]; Keep all APB2 peripherals under reset
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183 MOV r7, #10 ; Wait that the selected macrocells exit from reset
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184 loop1 SUBS r7, r7, #1
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187 STRH r0, [r1, #SWRES_off_addr]; Enable all all APB1 peripherals
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188 STRH r0, [r2, #SWRES_off_addr]; Enable all all APB2 peripherals
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189 STRH r0, [r1, #CKDIS_off_addr]; Clock Enabling for all APB1 peripherals
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190 STRH r0, [r2, #CKDIS_off_addr]; Clock Enabling for all APB2 peripherals
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191 MOV r7, #10 ; Wait that the selected macrocells exit from reset
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192 loop2 SUBS r7, r7, #1
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195 ;********************************************************************************************
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198 ; If you need to remap memory before entring the main program
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199 ; uncomment next ligne
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200 ; #define remapping
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202 ; Then define which memory to remap to address 0x00000000
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203 ; Uncomment next line if you want to remap RAM
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204 ; #define remap_ram
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206 ; Uncomment next line if you want to remap FLASH
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207 ; #define remap_flash
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211 __iar_program_start
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214 NOP ; Wait for OSC stabilization
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224 MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit
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225 ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
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227 MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit
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228 ldr sp,=SFE(UND_STACK) ; End of UNDEF_STACK
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230 MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
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231 ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
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235 ; Uncomment next ligne if you need to reset all device pripherals
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236 ; PERIPHERAL_INIT ; Reset all device peripherals
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238 ; Uncomment next ligne if you need to enable the EMI Bank 1
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239 ; EMI_INIT ; Initialize EIM Bank 1
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241 ;Uncomment next ligne if you need to initialize the EIC
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242 EIC_INIT ; Initialize EIC
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244 ;******************************************************************************
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246 ;Description : Remapping memory whether RAM,FLASH
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247 ; at Address 0x0 after the application has started executing.
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248 ; Remapping is generally done to allow RAM to replace FLASH
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250 ; the remapping of RAM allow copying of vector table into RAM
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251 ; To enable the memory remapping uncomment: (see above)
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252 ; #define remapping to enable memory remapping
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254 ; #define remap_ram to remap RAM
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256 ; #define remap_flash to remap FLASH
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257 ;******************************************************************************
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260 MOV r0, #FLASH_mask
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266 LDR r1, =CPM_Base_addr
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267 LDRH r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register
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268 BIC r2, r2, #0x03 ; Reset the two LSB bits of BOOTCR
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269 ORR r2, r2, r0 ; change the two LSB bits of BOOTCR
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270 STRH r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register
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273 MSR CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode
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274 ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
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276 MSR CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode
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277 ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
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279 MSR CPSR_c, #Mode_SYS ; Change to system mode, Enable IRQ and FIQ
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280 ldr sp,=SFE(CSTACK) ; End of CSTACK(user)
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284 ; --- Now branches to a C lib function that copies RO data from their
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285 ; load region to their execute region, create the RW and ZI regions
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286 ; then jumps to user C main program.
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288 ; main() must be called from Supervisor mode
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289 MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
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291 b ?main ; Note : use B not BL, because an application will
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292 ; never return this way
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297 ;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****
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