git.sur5r.net Git - freertos/blob - Demo/ARM7_STR71x_IAR/Library/rccu.c

   1 /******************** (C) COPYRIGHT 2003 STMicroelectronics ********************\r
   2 * File Name          : rccu.c\r
   3 * Author             : MCD Application Team\r
   4 * Date First Issued  : 07/28/2003\r
   5 * Description        : This file provides all the RCCU software functions\r
   6 ********************************************************************************\r
   7 * History:\r
   8 *  30/11/2004 : V2.0\r
   9 *  14/07/2004 : V1.3\r
  10 *  01/01/2004 : V1.2\r
  11 *******************************************************************************\r
  12  THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH\r
  13  CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
  14  AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT\r
  15  OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT\r
  16  OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION\r
  17  CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  18 *******************************************************************************/\r
  19 #include "rccu.h"\r
  20 \r
  21 /*******************************************************************************\r
  22 * Function Name  : RCCU_PLL1Config\r
  23 * Description    : Configures the PLL1 div & mul factors.\r
  24 * Input          : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,\r
  25 *                  RCCU_PLL1_Mul_24 )\r
  26 *                : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,\r
  27 *                  RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)\r
  28 * Return         : None\r
  29 *******************************************************************************/\r
  30 void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )\r
  31 {\r
  32   u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );\r
  33   RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;\r
  34 }\r
  35 \r
  36 /*******************************************************************************\r
  37 * Function Name  : RCCU_PLL2Config\r
  38 * Description    : Configures the PLL2 div & mul factors.\r
  39 * Input          : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, \r
  40 *                  RCCU_Mul_PLL2_28 )\r
  41 *                : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,\r
  42 *                  RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)\r
  43 * Return         : None\r
  44 *******************************************************************************/\r
  45 void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div )\r
  46 {\r
  47   u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );\r
  48   PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div  | RCCU_FREEN_Mask );\r
  49 }\r
  50 \r
  51 /*******************************************************************************\r
  52 * Function Name  : RCCU_RCLKSourceConfig\r
  53 * Description    : Selects the RCLK source clock\r
  54 * Input          : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 )\r
  55 * Return         : None\r
  56 *******************************************************************************/\r
  57 void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )\r
  58 {\r
  59   switch ( New_Clock )\r
  60   {\r
  61     case RCCU_CLOCK2    :{// Resets the CSU_Cksel bit in clk_flag\r
  62                              RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;\r
  63                           // Set the CK2_16 Bit in the CFR\r
  64                              RCCU->CFR |= RCCU_CK2_16_Mask;\r
  65                           // Deselect The CKAF\r
  66                              RCCU->CCR   &= ~RCCU_CKAF_SEL_Mask;\r
  67                            // switch off the PLL1\r
  68                               RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\\r
  69                               |0x00000003) & ~RCCU_FREEN_Mask;\r
  70                               break;}\r
  71     case RCCU_CLOCK2_16  :{// ReSet the CK2_16 Bit in the CFR\r
  72                               RCCU->CFR &= ~RCCU_CK2_16_Mask;\r
  73                            // Deselect The CKAF\r
  74                               RCCU->CCR   &= ~RCCU_CKAF_SEL_Mask;\r
  75                            // switch off the PLL1\r
  76                               RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\\r
  77                               |0x00000003) & ~RCCU_FREEN_Mask;\r
  78                               break;}\r
  79     case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR\r
  80                               RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask;\r
  81                            // Waits the PLL1 to lock if DX bits are different from '111'\r
  82                            // If all DX bit are set the PLL lock flag in meaningless\r
  83                               if (( RCCU->PLL1CR & 0x0007 ) != 7)\r
  84                                 while(!(RCCU->CFR & RCCU_LOCK_Mask));\r
  85                            // Deselect The CKAF\r
  86                               RCCU->CCR  &= ~RCCU_CKAF_SEL_Mask;\r
  87                            // Select The CSU_CKSEL\r
  88                               RCCU->CFR |= RCCU_CSU_CKSEL_Mask;\r
  89                               break;}\r
  90     case RCCU_RTC_CLOCK  :   {RCCU->CCR |= 0x04;\r
  91                               break;}\r
  92   }\r
  93 }\r
  94 \r
  95 /*******************************************************************************\r
  96 * Function Name  : RCCU_RCLKClockSource\r
  97 * Description    : Returns the current RCLK source clock\r
  98 * Input          : None\r
  99 * Return         : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK\r
 100 *******************************************************************************/\r
 101 RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void )\r
 102 {\r
 103   if ((RCCU->CCR & 0x04)==0x04)\r
 104     return RCCU_RTC_CLOCK;\r
 105 \r
 106   else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0)\r
 107     return RCCU_CLOCK2_16;\r
 108 \r
 109   else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask)\r
 110     return RCCU_PLL1_Output;\r
 111 \r
 112   else\r
 113     return RCCU_CLOCK2;\r
 114 }\r
 115 \r
 116 /*******************************************************************************\r
 117 * Function Name  : RCCU_USBClockSource\r
 118 * Description    : Gets the RCLK source clock\r
 119 * Input          : None\r
 120 * Return         : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK )\r
 121 *******************************************************************************/\r
 122 RCCU_USB_Clocks RCCU_USBClockSource ( void )\r
 123 {\r
 124   if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 )\r
 125      return RCCU_PLL2_Output;\r
 126   else return RCCU_USBCK;\r
 127 }\r
 128 \r
 129 /*******************************************************************************\r
 130 * Function Name  : RCCU_FrequencyValue\r
 131 * Description    : Calculates & Returns any internal RCCU clock frequency\r
 132 *                  passed in parametres\r
 133 * Input          : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK )\r
 134 * Return         : u32\r
 135 *******************************************************************************/\r
 136 u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk )\r
 137 {\r
 138   u32 Tmp;\r
 139   u8 Div, Mul;\r
 140   RCCU_RCLK_Clocks CurrentRCLK;\r
 141 \r
 142   Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 :  RCCU_Main_Osc;\r
 143 \r
 144   if ( Internal_Clk == RCCU_CLK2 )\r
 145   {\r
 146    Div = 1;\r
 147    Mul = 1;\r
 148   }\r
 149   else\r
 150   { CurrentRCLK = RCCU_RCLKClockSource ();\r
 151     switch ( CurrentRCLK ){\r
 152       case RCCU_CLOCK2_16 : Div = 16;\r
 153                             Mul = 1;\r
 154                             break;\r
 155       case RCCU_CLOCK2    : Div = 1;\r
 156                             Mul = 1;\r
 157                             break;\r
 158       case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index;\r
 159                               switch ( Mul )\r
 160                               {case 0: Mul = 20; break;\r
 161                                case 1: Mul = 12; break;\r
 162                                case 2: Mul = 28; break;\r
 163                                case 3: Mul = 16; break;\r
 164                               }\r
 165                               Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1;\r
 166                               break;}\r
 167      case RCCU_RTC_CLOCK :  Mul = 1;\r
 168                             Div = 1;\r
 169                             Tmp = RCCU_RTC_Osc;\r
 170                             break;}}\r
 171 \r
 172   switch ( Internal_Clk ){\r
 173       case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask;\r
 174                        break;}\r
 175       case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index;\r
 176                        break;}\r
 177       case RCCU_FCLK :{Div <<=  PCU->PDIVR & 0x3;\r
 178                        break;}}\r
 179 \r
 180   return (Tmp * Mul) / Div;\r
 181 }\r
 182 \r
 183 /******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/\r