1 ;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
\r
2 ;* File Name : 75x_init.s
\r
3 ;* Author : MCD Application Team
\r
4 ;* Date First Issued : 03/10/2006
\r
5 ;* Description : This module performs:
\r
6 ;* - Memory remapping (if required),
\r
7 ;* - Stack pointer initialisation for each mode ,
\r
8 ;* - Interrupt Controller Initialisation
\r
9 ;* - Branches to ?main in the C library (which eventually
\r
11 ;* On reset, the ARM core starts up in Supervisor (SVC) mode,
\r
12 ;* in ARM state,with IRQ and FIQ disabled.
\r
13 ;*******************************************************************************
\r
17 ;*******************************************************************************
\r
18 ; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
19 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
\r
20 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
\r
21 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
\r
22 ; CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
\r
23 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
24 ;*******************************************************************************
\r
26 IMPORT WAKUP_Addr ; imported from 75x_vect.s
\r
31 ; Depending on Your Application, Disable or Enable the following Defines
\r
32 ; ----------------------------------------------------------------------------
\r
33 ; SMI Bank0 configuration
\r
34 ; ----------------------------------------------------------------------------
\r
35 ; If you need to accees the SMI Bank0
\r
36 ; uncomment next line
\r
37 ;#define SMI_Bank0_EN
\r
39 ; ----------------------------------------------------------------------------
\r
41 ; ----------------------------------------------------------------------------
\r
42 ;#define Remap_SRAM ; remap SRAM at address 0x00
\r
44 ; ----------------------------------------------------------------------------
\r
45 ; EIC initialization
\r
46 ; ----------------------------------------------------------------------------
\r
47 #define EIC_INIT ; Configure and Initialize EIC
\r
49 ; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
\r
58 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
\r
59 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
\r
63 MRCC_PCLKEN_Addr EQU 0x60000030 ; Peripheral Clock Enable register base address
\r
66 CFG_GLCONF_Addr EQU 0x60000010 ; Global Configuration register base address
\r
67 SRAM_mask EQU 0x0002 ; to remap RAM at 0x0
\r
70 GPIOREMAP0R_Addr EQU 0xFFFFE420
\r
71 SMI_EN_Mask EQU 0x00000001
\r
74 SMI_CR1_Addr EQU 0x90000000
\r
76 ; EIC Registers offsets
\r
77 EIC_Base_addr EQU 0xFFFFF800 ; EIC base address
\r
78 ICR_off_addr EQU 0x00 ; Interrupt Control register offset
\r
79 CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset
\r
80 IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset
\r
81 FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset
\r
82 IER_off_addr EQU 0x20 ; Interrupt Enable Register offset
\r
83 IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset
\r
84 SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0
\r
87 ;---------------------------------------------------------------
\r
89 ;---------------------------------------------------------------
\r
90 MODULE ?program_start
\r
91 SECTION IRQ_STACK:DATA:NOROOT(3)
\r
92 SECTION FIQ_STACK:DATA:NOROOT(3)
\r
93 SECTION UND_STACK:DATA:NOROOT(3)
\r
94 SECTION ABT_STACK:DATA:NOROOT(3)
\r
95 SECTION SVC_STACK:DATA:NOROOT(3)
\r
96 SECTION CSTACK:DATA:NOROOT(3)
\r
97 SECTION .text:CODE(2)
\r
98 PUBLIC __iar_program_start
\r
103 __iar_program_start:
\r
107 ; Reset all Peripheral Clocks
\r
108 ; This is usefull only when using debugger to Reset\Run the application
\r
110 #ifdef SMI_Bank0_EN
\r
111 LDR r0, =0x01000000 ; Disable peripherals clock (except GPIO)
\r
113 LDR r0, =0x00000000 ; Disable peripherals clock
\r
115 LDR r1, =MRCC_PCLKEN_Addr
\r
118 #ifdef SMI_Bank0_EN
\r
119 LDR r0, =0x1875623F ; Peripherals kept under reset (except GPIO)
\r
121 LDR r0, =0x1975623F ; Peripherals kept under reset
\r
130 STR r0, [r1,#4] ; Disable peripherals reset
\r
132 ; Initialize stack pointer registers
\r
133 ; Enter each mode in turn and set up the stack pointer
\r
136 MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
\r
137 ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
\r
139 MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
\r
140 ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
\r
142 MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
\r
143 ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
\r
145 MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
\r
146 ldr sp,=SFE(UND_STACK) ; End of UND_STACK
\r
148 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
\r
149 ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
\r
151 ; ------------------------------------------------------------------------------
\r
152 ; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register,
\r
153 ; enable SMI alternate function in GPIO_REMAP register and enable
\r
154 ; Bank0 in SMI_CR1 register.
\r
155 ; ------------------------------------------------------------------------------
\r
156 #ifdef SMI_Bank0_EN
\r
157 MOV r0, #0x01000000
\r
158 LDR r1, =MRCC_PCLKEN_Addr
\r
159 STR r0, [r1] ; Enable GPIOs clock
\r
161 LDR r1, =GPIOREMAP0R_Addr
\r
162 MOV r0, #SMI_EN_Mask
\r
165 STR r2, [r1] ; Enable SMI alternate function
\r
167 LDR r0, =0x251 ; SMI Bank0 enabled, Prescaler = 2, Deselect Time = 5
\r
168 LDR r1, =SMI_CR1_Addr
\r
169 STR r0, [r1] ; Configure CR1 register
\r
171 STR r0, [r1,#4] ; Reset CR2 register
\r
174 ; ------------------------------------------------------------------------------
\r
175 ; Description : Remapping SRAM at address 0x00 after the application has
\r
176 ; started executing.
\r
177 ; ------------------------------------------------------------------------------
\r
180 LDR r1, =CFG_GLCONF_Addr
\r
181 LDR r2, [r1] ; Read GLCONF Register
\r
182 BIC r2, r2, #0x03 ; Reset the SW_BOOT bits
\r
183 ORR r2, r2, r0 ; Change the SW_BOOT bits
\r
184 STR r2, [r1] ; Write GLCONF Register
\r
187 ;-------------------------------------------------------------------------------
\r
188 ;Description : Initialize the EIC as following :
\r
191 ; - IVR contains the load PC opcode
\r
192 ; - All channels are disabled
\r
193 ; - All channels priority equal to 0
\r
194 ; - All SIR registers contains offset to the related IRQ table entry
\r
195 ;-------------------------------------------------------------------------------
\r
197 LDR r3, =EIC_Base_addr
\r
198 LDR r4, =0x00000000
\r
199 STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ
\r
200 STR r4, [r3, #IER_off_addr] ; Disable all interrupts channels
\r
202 LDR r4, =0xFFFFFFFF
\r
203 STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits
\r
206 STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits
\r
208 LDR r4, =0x00000000
\r
209 STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register
\r
211 LDR r4, =0xE59F0000 ; Write the LDR pc,pc,#offset..
\r
212 STR r4, [r3, #IVR_off_addr] ; ..instruction code in IVR[31:16]
\r
215 LDR r2,= 32 ; 32 Channel to initialize
\r
216 LDR r0, =WAKUP_Addr ; Read the address of the IRQs address table
\r
217 LDR r1, =0x00000FFF
\r
219 LDR r5,=SIR0_off_addr ; Read SIR0 address
\r
220 SUB r4,r0,#8 ; subtract 8 for prefetch
\r
221 LDR r1, =0xF7E8 ; add the offset to the 0x00 address..
\r
222 ; ..(IVR address + 7E8 = 0x00)
\r
223 ; 0xF7E8 used to complete the LDR pc,offset opcode
\r
224 ADD r1,r4,r1 ; compute the jump offset
\r
226 MOV r4, r1, LSL #16 ; Left shift the result
\r
227 STR r4, [r3, r5] ; Store the result in SIRx register
\r
228 ADD r1, r1, #4 ; Next IRQ address
\r
229 ADD r5, r5, #4 ; Next SIR
\r
230 SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize
\r
231 BNE EIC_INI ; If more then continue
\r
236 ; --- Branch to C Library entry point
\r
240 B ?main ; use B not BL, because an application will never return this way
\r
249 ;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE*****
\r