1 ;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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2 ;* File Name : 91x_init.s
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3 ;* Author : MCD Application Team
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4 ;* Date First Issued : 05/18/2006 : Version 1.0
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5 ;* Description : This module performs:
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6 ;* - FLASH/RAM initialization,
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7 ;* - Stack pointer initialization for each mode ,
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8 ;* - Branches to ?main in the C library (which eventually
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11 ;* On reset, the ARM core starts up in Supervisor (SVC) mode,
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12 ;* in ARM state,with IRQ and FIQ disabled.
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13 ;*******************************************************************************
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15 ;* 05/22/2007 : Version 1.2
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16 ;* 05/24/2006 : Version 1.1
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17 ;* 05/18/2006 : Version 1.0
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18 ;*******************************************************************************
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19 ;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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20 ;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
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21 ;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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22 ;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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23 ;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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24 ;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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25 ;******************************************************************************/
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27 ; At power up, the CPU defaults to run on the oscillator clock, so Depending
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28 ; of your Application, Disable or Enable the following Define
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30 #define PLL_Clock ; Use PLL as the default clock source @ 96 MHz only with
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31 ; Bank 0 @ 0x0 and Bank 1 @ 0x80000
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32 ; #define RTC_Clock ; Use RTC as the default clock source
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33 ; #define OSC_Clock ; Use OSC as the default clock source
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36 ; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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44 Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
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46 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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47 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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51 ; --- STR9X SCU specific definitions
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53 SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address
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54 SCU_CLKCNTR_OFST EQU 0x00000000 ; Clock Control register Offset
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55 SCU_PLLCONF_OFST EQU 0x00000004 ; PLL Configuration register Offset
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56 SCU_SYSSTATUS_OFST EQU 0x00000008 ; System Status Register Offset
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57 SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset
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59 ; --- STR9X FMI specific definitions
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61 FMI_BASE_Address EQU 0x54000000 ; FMI Base Address
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62 FMI_BBSR_OFST EQU 0x00000000 ; Boot Bank Size Register
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63 FMI_NBBSR_OFST EQU 0x00000004 ; Non-boot Bank Size Register
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64 FMI_BBADR_OFST EQU 0x0000000C ; Boot Bank Base Address Register
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65 FMI_NBBADR_OFST EQU 0x00000010 ; Non-boot Bank Base Address Register
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66 FMI_CR_OFST EQU 0x00000018 ; Control Register
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68 ;---------------------------------------------------------------
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70 ;---------------------------------------------------------------
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71 MODULE ?program_start
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73 SECTION IRQ_STACK:DATA:NOROOT(3)
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74 SECTION FIQ_STACK:DATA:NOROOT(3)
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75 SECTION UND_STACK:DATA:NOROOT(3)
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76 SECTION ABT_STACK:DATA:NOROOT(3)
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77 SECTION SVC_STACK:DATA:NOROOT(3)
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78 SECTION CSTACK:DATA:NOROOT(3)
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79 SECTION .icode:CODE:NOROOT(2)
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80 PUBLIC __iar_program_start
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84 __iar_program_start:
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91 NOP ; execute some instructions to access CPU registers after wake
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92 NOP ; up from Reset, while waiting for OSC stabilization
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103 ; ------------------------------------------------------------------------------
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104 ; Description : Enable the Buffered mode.
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105 ; Just enable the buffered define on the 91x_conf.h
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106 ; http://www.arm.com/pdfs/DDI0164A_966E_S.pdf
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107 ; ------------------------------------------------------------------------------
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109 MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0
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110 ORR r0, r0, #0x8 ; Enable Write Buffer on AHB
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111 MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1
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115 ; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
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116 ; when the bank 0 is the boot bank, then enable the Bank 1.
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118 LDR R6, =FMI_BASE_Address
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120 LDR R7, = 0x4 ; BOOT BANK Size = 512KB
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121 STR R7, [R6, #FMI_BBSR_OFST] ; (2^4) * 32 = 512KB
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123 LDR R7, = 0x2 ; NON BOOT BANK Size = 32KB
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124 STR R7, [R6, #FMI_NBBSR_OFST] ; (2^2) * 8 = 32KB
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126 LDR R7, = 0x0 ; BOOT BANK Address = 0x0
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127 STR R7, [R6, #FMI_BBADR_OFST]
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129 LDR R7, = 0x20000 ; NON BOOT BANK Address = 0x80000
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130 STR R7, [R6, #FMI_NBBADR_OFST] ; need to put 0x20000 because FMI
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131 ; bus on A[25:2] of CPU bus
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133 LDR R7, = 0x18 ; Enable CS on both banks
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134 STR R7, [R6, #FMI_CR_OFST] ; LDR R7, = 0x19 ;in RevD
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135 ; to enable 8 words PFQ deepth
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137 ; --- Enable 96K RAM, PFQBC enabled, DTCM & AHB wait-states disabled
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138 LDR R0, = SCU_BASE_Address
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140 STR R1, [R0, #SCU_SCR0_OFST]
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142 ; ------------------------------------------------------------------------------
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143 ; --- System clock configuration
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144 ; ------------------------------------------------------------------------------
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146 #ifdef PLL_Clock ; Use 96 MHZ PLL clock as the default frequency
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148 ; --- wait states Flash confguration
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150 LDR R6, = 0x00080000 ;Write a Write Flash Configuration
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151 LDR R7, =0x60 ;Register command (60h) to any word
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152 STRH R7, [R6] ;address in Bank 1.
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154 LDR R6, = 0x00083040 ;Write a Write Flash Configuration
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155 LDR R7, = 0x3 ;Register Confirm command (03h)
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156 STRH R7, [R6] ;2Wstaites in read,PWD,LVD enabled,
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158 ; --- PLL configuration
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159 LDR R1, = 0x00020002 ;Set OSC as clock source
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160 STR R1, [R0, #SCU_CLKCNTR_OFST ]
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163 NOP ; Wait for OSC stabilization
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179 LDR R1, = 0x000ac019 ;Set PLL ENABLE, to 96Mhz
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180 STR R1, [R0, #SCU_PLLCONF_OFST]
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183 LDR R1,[R0, #SCU_SYSSTATUS_OFST] ;Wait until PLL is Locked
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187 LDR R1, = 0x00020080 ;Set PLL as clock source after pll
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188 STR R1, [R0, #SCU_CLKCNTR_OFST ] ;is locked and FMICLK=RCLK,
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192 #ifdef RTC_Clock ;Use RTC as the default clock source
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193 LDR R1, = 0x00020001 ;Set RTC as clock source and
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194 STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK
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197 #ifdef OSC_Clock ;Use Osc as the default clock source
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198 LDR R1, = 0x00020002 ;Set OSC as clock source and
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199 STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK
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203 ; --- Initialize Stack pointer registers
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205 ; Enter each mode in turn and set up the stack pointer
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207 MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
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208 LDR SP, =SFE(FIQ_STACK)
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210 MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
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211 LDR SP, = SFE(IRQ_STACK)
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213 MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
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214 LDR SP, = SFE(ABT_STACK)
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216 MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
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217 LDR SP, = SFE(UND_STACK)
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219 MSR CPSR_c, #Mode_SYS ; IRQs & FIQs are now enabled
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220 LDR SP, = SFE(CSTACK)
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222 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
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223 LDR SP, = SFE(SVC_STACK)
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225 ; --- Set bits 17-18(DTCM/ITCM order bits)of the Core Configuration Control
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228 MCR p15,0x1,r0,c15,c1,0
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230 ; --- Now enter the C code
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231 B ?main ; Note : use B not BL, because an application will
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232 ; never return this way
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238 ;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****
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