1 /*This file is prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief Exception and interrupt vectors.
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6 * This file maps all events supported by an AVR32.
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8 * - Compiler: IAR EWAVR32
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9 * - Supported devices: All AVR32 devices with an INTC module can be used.
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12 * \author Atmel Corporation: http://www.atmel.com \n
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13 * Support and FAQ: http://support.atmel.no/
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15 ******************************************************************************/
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17 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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19 * Redistribution and use in source and binary forms, with or without
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20 * modification, are permitted provided that the following conditions are met:
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22 * 1. Redistributions of source code must retain the above copyright notice, this
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23 * list of conditions and the following disclaimer.
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25 * 2. Redistributions in binary form must reproduce the above copyright notice,
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26 * this list of conditions and the following disclaimer in the documentation
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27 * and/or other materials provided with the distribution.
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29 * 3. The name of Atmel may not be used to endorse or promote products derived
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30 * from this software without specific prior written permission.
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32 * 4. This software may only be redistributed and used in connection with an Atmel
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35 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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36 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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38 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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39 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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41 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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42 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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44 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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48 #if __CORE__ != __AVR32A__ && __CORE__ != __AVR32B__
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49 #error Implementation of the AVR32 architecture not supported by the INTC driver.
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53 #include <avr32/io.h>
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60 // Start of Exception Vector Table.
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62 // EVBA must be aligned with a power of two strictly greater than the EVBA-
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63 // relative offset of the last vector.
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64 COMMON EVTAB:CODE:ROOT(9)
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67 // Force EVBA initialization.
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78 // Unrecoverable Exception.
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79 _handle_Unrecoverable_Exception:
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83 // TLB Multiple Hit.
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84 _handle_TLB_Multiple_Hit:
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88 // Bus Error Data Fetch.
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89 _handle_Bus_Error_Data_Fetch:
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93 // Bus Error Instruction Fetch.
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94 _handle_Bus_Error_Instruction_Fetch:
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103 // Instruction Address.
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104 _handle_Instruction_Address:
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108 // ITLB Protection.
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109 _handle_ITLB_Protection:
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114 _handle_Breakpoint:
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119 _handle_Illegal_Opcode:
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123 // Unimplemented Instruction.
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124 _handle_Unimplemented_Instruction:
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128 // Privilege Violation.
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129 _handle_Privilege_Violation:
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133 // Floating-Point: UNUSED IN AVR32UC and AVR32AP.
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134 _handle_Floating_Point:
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138 // Coprocessor Absent: UNUSED IN AVR32UC.
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139 _handle_Coprocessor_Absent:
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143 // Data Address (Read).
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144 _handle_Data_Address_Read:
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148 // Data Address (Write).
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149 _handle_Data_Address_Write:
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153 // DTLB Protection (Read).
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154 _handle_DTLB_Protection_Read:
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158 // DTLB Protection (Write).
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159 _handle_DTLB_Protection_Write:
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163 // DTLB Modified: UNUSED IN AVR32UC.
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164 _handle_DTLB_Modified:
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173 // DTLB Miss (Read).
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174 _handle_DTLB_Miss_Read:
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178 // DTLB Miss (Write).
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179 _handle_DTLB_Miss_Write:
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183 // Supervisor Call.
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184 _handle_Supervisor_Call:
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188 // Interrupt support.
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189 // The interrupt controller must provide the offset address relative to EVBA.
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191 // All interrupts call a C function named _get_interrupt_handler.
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192 // This function will read group and interrupt line number to then return in
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193 // R12 a pointer to a user-provided interrupt handler.
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197 REPTI priority, 0, 1, 2, 3
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199 #if __CORE__ == __AVR32A__
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200 // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
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201 // CPU upon interrupt entry. No other register is saved by hardware.
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202 #elif __CORE__ == __AVR32B__
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203 // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
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204 // the CPU upon interrupt entry. No other register is saved by hardware.
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207 mov r12, priority // Pass the int_level parameter to the _get_interrupt_handler function.
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208 mcall __get_interrupt_handler
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209 cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
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210 #if __CORE__ == __AVR32A__
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211 movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
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212 #elif __CORE__ == __AVR32B__
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213 breq spint<priority> // If this was a spurious interrupt (R12 == NULL), branch.
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214 st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
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215 popm r8-r12, lr, pc // Restore registers and jump to the handler.
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219 rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
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223 // Constant data area.
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228 EXTERN _get_interrupt_handler
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229 __get_interrupt_handler:
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230 DC32 _get_interrupt_handler
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232 // Values to store in the interrupt priority registers for the various interrupt priority levels.
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233 // The interrupt priority registers contain the interrupt priority level and
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234 // the EVBA-relative interrupt vector offset.
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237 DC32 (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
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238 (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
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239 (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
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240 (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
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