1 /* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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3 /*This file is prepared for Doxygen automatic documentation generation.*/
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4 /*! \file *********************************************************************
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6 * \brief INTC driver for AVR32 UC3.
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8 * AVR32 Interrupt Controller driver module.
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10 * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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11 * - Supported devices: All AVR32 devices with an INTC module can be used.
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14 * \author Atmel Corporation: http://www.atmel.com \n
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15 * Support and FAQ: http://support.atmel.no/
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17 ******************************************************************************/
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19 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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21 * Redistribution and use in source and binary forms, with or without
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22 * modification, are permitted provided that the following conditions are met:
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24 * 1. Redistributions of source code must retain the above copyright notice, this
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25 * list of conditions and the following disclaimer.
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27 * 2. Redistributions in binary form must reproduce the above copyright notice,
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28 * this list of conditions and the following disclaimer in the documentation
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29 * and/or other materials provided with the distribution.
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31 * 3. The name of Atmel may not be used to endorse or promote products derived
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32 * from this software without specific prior written permission.
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34 * 4. This software may only be redistributed and used in connection with an Atmel
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37 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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38 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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40 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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41 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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44 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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46 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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50 #include <avr32/io.h>
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51 #include "compiler.h"
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52 #include "preprocessor.h"
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55 // define _evba from exception.S
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58 //! Values to store in the interrupt priority registers for the various interrupt priority levels.
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59 extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
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61 //! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
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62 //! Each line handler table contains a set of pointers to interrupt handlers.
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63 #if (defined __GNUC__)
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64 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
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65 static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
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66 #elif (defined __ICCAVR32__)
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67 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
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68 static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
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70 MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
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71 #undef DECL_INT_LINE_HANDLER_TABLE
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73 //! Table containing for each interrupt group the number of interrupt request
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74 //! lines and a pointer to the table of interrupt line handlers.
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77 unsigned int num_irqs;
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78 volatile __int_handler *_int_line_handler_table;
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79 } _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
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81 #define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
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82 {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
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83 MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
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84 #undef INSERT_INT_LINE_HANDLER_TABLE
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88 /*! \brief Default interrupt handler.
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90 * \note Taken and adapted from Newlib.
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92 #if (defined __GNUC__)
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93 __attribute__((__interrupt__))
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94 #elif (defined __ICCAVR32__)
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97 static void _unhandled_interrupt(void)
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99 // Catch unregistered interrupts.
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104 /*! \brief Gets the interrupt handler of the current event at the \a int_level
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105 * interrupt priority level (called from exception.S).
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107 * \param int_level Interrupt priority level to handle.
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109 * \return Interrupt handler to execute.
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111 * \note Taken and adapted from Newlib.
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113 __int_handler _get_interrupt_handler(unsigned int int_level)
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115 // ICR3 is mapped first, ICR0 last.
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116 // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
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117 // pass a single argument to a function.
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118 unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
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119 unsigned int int_req = AVR32_INTC.irr[int_grp];
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121 // As an interrupt may disappear while it is being fetched by the CPU
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122 // (spurious interrupt caused by a delayed response from an MCU peripheral to
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123 // an interrupt flag clear or interrupt disable instruction), check if there
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124 // are remaining interrupt lines to process.
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125 // If a spurious interrupt occurs, the status register (SR) contains an
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126 // execution mode and interrupt level masks corresponding to a level 0
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127 // interrupt, whatever the interrupt priority level causing the spurious
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128 // event. This behavior has been chosen because a spurious interrupt has not
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129 // to be a priority one and because it may not cause any trouble to other
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131 // However, these spurious interrupts place the hardware in an unstable state
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132 // and could give problems in other/future versions of the CPU, so the
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133 // software has to be written so that they never occur. The only safe way of
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134 // achieving this is to always clear or disable peripheral interrupts with the
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135 // following sequence:
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136 // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
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137 // 2: Perform the bus access to the peripheral register that clears or
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138 // disables the interrupt.
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139 // 3: Wait until the interrupt has actually been cleared or disabled by the
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140 // peripheral. This is usually performed by reading from a register in the
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141 // same peripheral (it DOES NOT have to be the same register that was
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142 // accessed in step 2, but it MUST be in the same peripheral), what takes
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143 // bus system latencies into account, but peripheral internal latencies
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144 // (generally 0 cycle) also have to be considered.
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145 // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
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146 // Note that steps 1 and 4 are useless inside interrupt handlers as the
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147 // corresponding interrupt level is automatically masked by IxM (unless IxM is
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148 // explicitly cleared by the software).
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150 // Get the right IRQ handler.
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152 // If several interrupt lines are active in the group, the interrupt line with
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153 // the highest number is selected. This is to be coherent with the
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154 // prioritization of interrupt groups performed by the hardware interrupt
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157 // If no handler has been registered for the pending interrupt,
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158 // _unhandled_interrupt will be selected thanks to the initialization of
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159 // _int_line_handler_table_x by INTC_init_interrupts.
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161 // exception.S will provide the interrupt handler with a clean interrupt stack
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162 // frame, with nothing more pushed onto the stack. The interrupt handler must
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163 // manage the `rete' instruction, what can be done thanks to pure assembly,
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164 // inline assembly or the `__attribute__((__interrupt__))' C function
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166 return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
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169 //! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S
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170 static __inline__ void INTC_init_evba(void)
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172 Set_system_register(AVR32_EVBA, (int)&_evba );
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175 void INTC_init_interrupts(void)
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177 unsigned int int_grp, int_req;
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181 // For all interrupt groups,
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182 for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
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184 // For all interrupt request lines of each group,
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185 for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
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187 // Assign _unhandled_interrupt as default interrupt handler.
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188 _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
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191 // Set the interrupt group priority register to its default value.
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192 // By default, all interrupt groups are linked to the interrupt priority
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193 // level 0 and to the interrupt vector _int0.
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194 AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
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199 void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
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201 // Determine the group of the IRQ.
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202 unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
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204 // Store in _int_line_handler_table_x the pointer to the interrupt handler, so
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205 // that _get_interrupt_handler can retrieve it when the interrupt is vectored.
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206 _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
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208 // Program the corresponding IPRX register to set the interrupt priority level
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209 // and the interrupt vector offset that will be fetched by the core interrupt
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211 // NOTE: The _intx functions are intermediate assembly functions between the
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212 // core interrupt system and the user interrupt handler.
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213 AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
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