[freertos] / Demo / AVR32_UC3A_GCC / Atmel_SW_Framework / DRIVERS / INTC / intc.c

/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */\r

/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
 *\r
 * \brief INTC driver for AVR32 UC3.\r
 *\r
 * AVR32 Interrupt Controller driver module.\r
 *\r
 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32\r
 * - Supported devices:  All AVR32 devices with an INTC module can be used.\r
 * - AppNote:\r
 *\r
 * \author               Atmel Corporation: http://www.atmel.com \n\r
 *                       Support and FAQ: http://support.atmel.no/\r
 *\r
 ******************************************************************************/\r
\r
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.\r
 *\r
 * Redistribution and use in source and binary forms, with or without\r
 * modification, are permitted provided that the following conditions are met:\r
 *\r
 * 1. Redistributions of source code must retain the above copyright notice, this\r
 * list of conditions and the following disclaimer.\r
 *\r
 * 2. Redistributions in binary form must reproduce the above copyright notice,\r
 * this list of conditions and the following disclaimer in the documentation\r
 * and/or other materials provided with the distribution.\r
 *\r
 * 3. The name of Atmel may not be used to endorse or promote products derived\r
 * from this software without specific prior written permission.\r
 *\r
 * 4. This software may only be redistributed and used in connection with an Atmel\r
 * AVR product.\r
 *\r
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE\r
 *\r
 */\r
\r
#include <avr32/io.h>\r
#include "compiler.h"\r
#include "preprocessor.h"\r
#include "intc.h"\r
\r
// define _evba from exception.S\r
extern void _evba;\r
\r
//! Values to store in the interrupt priority registers for the various interrupt priority levels.\r
extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];\r
\r
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.\r
//! Each line handler table contains a set of pointers to interrupt handlers.\r
#if (defined __GNUC__)\r
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];\r
#elif (defined __ICCAVR32__)\r
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];\r
#endif\r
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);\r
#undef DECL_INT_LINE_HANDLER_TABLE\r
\r
//! Table containing for each interrupt group the number of interrupt request\r
//! lines and a pointer to the table of interrupt line handlers.\r
static const struct\r
{\r
  unsigned int num_irqs;\r
  volatile __int_handler *_int_line_handler_table;\r
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =\r
{\r
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
  {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},\r
  MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)\r
#undef INSERT_INT_LINE_HANDLER_TABLE\r
};\r
\r
\r
/*! \brief Default interrupt handler.\r
 *\r
 * \note Taken and adapted from Newlib.\r
 */\r
#if (defined __GNUC__)\r
__attribute__((__interrupt__))\r
#elif (defined __ICCAVR32__)\r
__interrupt\r
#endif\r
static void _unhandled_interrupt(void)\r
{\r
  // Catch unregistered interrupts.\r
  while (TRUE);\r
}\r
\r
\r
/*! \brief Gets the interrupt handler of the current event at the \a int_level\r
 *         interrupt priority level (called from exception.S).\r
 *\r
 * \param int_level Interrupt priority level to handle.\r
 *\r
 * \return Interrupt handler to execute.\r
 *\r
 * \note Taken and adapted from Newlib.\r
 */\r
__int_handler _get_interrupt_handler(unsigned int int_level)\r
{\r
  // ICR3 is mapped first, ICR0 last.\r
  // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to\r
  // pass a single argument to a function.\r
  unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];\r
  unsigned int int_req = AVR32_INTC.irr[int_grp];\r
\r
  // As an interrupt may disappear while it is being fetched by the CPU\r
  // (spurious interrupt caused by a delayed response from an MCU peripheral to\r
  // an interrupt flag clear or interrupt disable instruction), check if there\r
  // are remaining interrupt lines to process.\r
  // If a spurious interrupt occurs, the status register (SR) contains an\r
  // execution mode and interrupt level masks corresponding to a level 0\r
  // interrupt, whatever the interrupt priority level causing the spurious\r
  // event. This behavior has been chosen because a spurious interrupt has not\r
  // to be a priority one and because it may not cause any trouble to other\r
  // interrupts.\r
  // However, these spurious interrupts place the hardware in an unstable state\r
  // and could give problems in other/future versions of the CPU, so the\r
  // software has to be written so that they never occur. The only safe way of\r
  // achieving this is to always clear or disable peripheral interrupts with the\r
  // following sequence:\r
  // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.\r
  // 2: Perform the bus access to the peripheral register that clears or\r
  //    disables the interrupt.\r
  // 3: Wait until the interrupt has actually been cleared or disabled by the\r
  //    peripheral. This is usually performed by reading from a register in the\r
  //    same peripheral (it DOES NOT have to be the same register that was\r
  //    accessed in step 2, but it MUST be in the same peripheral), what takes\r
  //    bus system latencies into account, but peripheral internal latencies\r
  //    (generally 0 cycle) also have to be considered.\r
  // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.\r
  // Note that steps 1 and 4 are useless inside interrupt handlers as the\r
  // corresponding interrupt level is automatically masked by IxM (unless IxM is\r
  // explicitly cleared by the software).\r
  //\r
  // Get the right IRQ handler.\r
  //\r
  // If several interrupt lines are active in the group, the interrupt line with\r
  // the highest number is selected. This is to be coherent with the\r
  // prioritization of interrupt groups performed by the hardware interrupt\r
  // controller.\r
  //\r
  // If no handler has been registered for the pending interrupt,\r
  // _unhandled_interrupt will be selected thanks to the initialization of\r
  // _int_line_handler_table_x by INTC_init_interrupts.\r
  //\r
  // exception.S will provide the interrupt handler with a clean interrupt stack\r
  // frame, with nothing more pushed onto the stack. The interrupt handler must\r
  // manage the `rete' instruction, what can be done thanks to pure assembly,\r
  // inline assembly or the `__attribute__((__interrupt__))' C function\r
  // attribute.\r
  return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;\r
}\r
\r
//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S\r
static __inline__ void INTC_init_evba(void)\r
{\r
  Set_system_register(AVR32_EVBA, (int)&_evba );\r
}\r
\r
void INTC_init_interrupts(void)\r
{\r
  unsigned int int_grp, int_req;\r
\r
  INTC_init_evba();\r
\r
  // For all interrupt groups,\r
  for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)\r
  {\r
    // For all interrupt request lines of each group,\r
    for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)\r
    {\r
      // Assign _unhandled_interrupt as default interrupt handler.\r
      _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;\r
    }\r
\r
    // Set the interrupt group priority register to its default value.\r
    // By default, all interrupt groups are linked to the interrupt priority\r
    // level 0 and to the interrupt vector _int0.\r
    AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];\r
  }\r
}\r
\r
\r
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)\r
{\r
  // Determine the group of the IRQ.\r
  unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;\r
\r
  // Store in _int_line_handler_table_x the pointer to the interrupt handler, so\r
  // that _get_interrupt_handler can retrieve it when the interrupt is vectored.\r
  _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;\r
\r
  // Program the corresponding IPRX register to set the interrupt priority level\r
  // and the interrupt vector offset that will be fetched by the core interrupt\r
  // system.\r
  // NOTE: The _intx functions are intermediate assembly functions between the\r
  // core interrupt system and the user interrupt handler.\r
  AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];\r
}\r