1 /* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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3 /*This file has been prepared for Doxygen automatic documentation generation.*/
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4 /*! \file *********************************************************************
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6 * \brief High-level library abstracting features such as oscillators/pll/dfll
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7 * configuration, clock configuration, System-sensible parameters
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8 * configuration, buses clocks configuration, sleep mode, reset.
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11 * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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12 * - Supported devices: All AVR32 devices.
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15 * \author Atmel Corporation: http://www.atmel.com \n
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16 * Support and FAQ: http://support.atmel.no/
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18 *****************************************************************************/
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20 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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22 * Redistribution and use in source and binary forms, with or without
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23 * modification, are permitted provided that the following conditions are met:
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25 * 1. Redistributions of source code must retain the above copyright notice, this
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26 * list of conditions and the following disclaimer.
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28 * 2. Redistributions in binary form must reproduce the above copyright notice,
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29 * this list of conditions and the following disclaimer in the documentation
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30 * and/or other materials provided with the distribution.
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32 * 3. The name of Atmel may not be used to endorse or promote products derived
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33 * from this software without specific prior written permission.
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35 * 4. This software may only be redistributed and used in connection with an Atmel
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38 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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39 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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40 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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41 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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42 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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44 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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45 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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47 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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50 #include "power_clocks_lib.h"
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53 //! Device-specific data
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55 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration
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59 static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration
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62 long int pcl_configure_clocks(pcl_freq_param_t *param)
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64 #ifndef AVR32_PM_VERSION_RESETVALUE
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65 // Implementation for UC3A, UC3A3, UC3B parts.
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66 return(pm_configure_clocks(param));
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68 #ifdef AVR32_PM_410_H_INCLUDED
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69 // Implementation for UC3C parts.
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70 return(pcl_configure_clocks_uc3c(param));
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72 // Implementation for UC3L parts.
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73 return(pcl_configure_clocks_uc3l(param));
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79 //! Device-specific implementation
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81 // FORWARD declaration
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82 static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,
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83 unsigned long main_clock_freq_hz,
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84 pcl_freq_param_t *param);
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86 long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)
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88 // Supported main clock sources: PCL_MC_RCSYS
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90 // Supported synchronous clocks frequencies if RCSYS is the main clock source:
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91 // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
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93 // NOTE: by default, this implementation doesn't perform thorough checks on the
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94 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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96 #ifdef AVR32SFW_INPUT_CHECK
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97 // Verify that fCPU >= fPBx
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98 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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102 #ifdef AVR32SFW_INPUT_CHECK
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103 // Verify that the target frequencies are reachable.
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104 if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
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105 || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
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109 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
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113 long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
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115 // Supported main clock sources: PCL_MC_RC120M
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117 // Supported synchronous clocks frequencies if RC120M is the main clock source:
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118 // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
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120 // NOTE: by default, this implementation doesn't perform thorough checks on the
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121 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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123 #ifdef AVR32SFW_INPUT_CHECK
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124 // Verify that fCPU >= fPBx
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125 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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129 #ifdef AVR32SFW_INPUT_CHECK
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130 // Verify that the target frequencies are reachable.
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131 if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
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132 || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
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136 // Start the 120MHz internal RCosc (RC120M) clock
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137 scif_start_rc120M();
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139 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
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143 long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
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145 // Supported main clock sources: PCL_MC_OSC0
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147 // Supported synchronous clocks frequencies if OSC0 is the main clock source:
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148 // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
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149 // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
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151 // NOTE: by default, this implementation doesn't perform thorough checks on the
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152 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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154 unsigned long main_clock_freq;
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157 #ifdef AVR32SFW_INPUT_CHECK
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158 // Verify that fCPU >= fPBx
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159 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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163 main_clock_freq = param->osc0_f;
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164 #ifdef AVR32SFW_INPUT_CHECK
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165 // Verify that the target frequencies are reachable.
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166 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
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167 || (param->pbb_f > main_clock_freq))
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170 // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
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171 scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
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173 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
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175 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
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179 long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
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181 // Supported main clock sources: PCL_MC_DFLL
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183 // Supported synchronous clocks frequencies if DFLL is the main clock source:
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184 // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
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185 // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
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187 // NOTE: by default, this implementation doesn't perform thorough checks on the
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188 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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190 unsigned long main_clock_freq;
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191 scif_gclk_opt_t *pgc_dfllif_ref_opt;
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194 #ifdef AVR32SFW_INPUT_CHECK
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195 // Verify that fCPU >= fPBx
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196 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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200 main_clock_freq = param->dfll_f;
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201 #ifdef AVR32SFW_INPUT_CHECK
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202 // Verify that the target DFLL output frequency is in the correct range.
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203 if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
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205 // Verify that the target frequencies are reachable.
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206 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
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207 || (param->pbb_f > main_clock_freq))
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210 pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params;
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211 // Implementation note: this implementation configures the DFLL in closed-loop
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212 // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
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213 // as a reference (RCSYS being used as the generic clock source, undivided).
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214 scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);
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216 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
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220 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)
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222 // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M
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224 // Supported synchronous clocks frequencies if RCSYS is the main clock source:
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225 // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
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227 // Supported synchronous clocks frequencies if RC120M is the main clock source:
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228 // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
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230 // Supported synchronous clocks frequencies if OSC0 is the main clock source:
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231 // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
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232 // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
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234 // Supported synchronous clocks frequencies if DFLL is the main clock source:
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235 // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
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236 // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
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238 // NOTE: by default, this implementation doesn't perform thorough checks on the
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239 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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242 #ifdef AVR32SFW_INPUT_CHECK
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243 // Verify that fCPU >= fPBx
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244 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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248 if(PCL_MC_RCSYS == param->main_clk_src)
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250 return(pcl_configure_clocks_rcsys(param));
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252 else if(PCL_MC_RC120M == param->main_clk_src)
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254 return(pcl_configure_clocks_rc120m(param));
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256 else if(PCL_MC_OSC0 == param->main_clk_src)
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258 return(pcl_configure_clocks_osc0(param));
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260 else // PCL_MC_DFLL0 == param->main_clk_src
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262 return(pcl_configure_clocks_dfll0(param));
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266 static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
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269 //# Set the Synchronous clock division ratio for each clock domain
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271 pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
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274 //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
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277 flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
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279 flashc_set_flash_waitstate_and_readmode(param->cpu_f);
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284 //# Switch the main clock source to the selected clock.
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286 pm_set_mclk_source(main_clk_src);
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291 #endif // UC3L device-specific implementation
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293 //! UC3C Device-specific implementation
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295 static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
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297 #define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
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298 #define AVR32_PM_PBA_MAX_FREQ 66000000
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299 #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
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300 #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
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302 // Implementation for UC3C parts.
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303 // Supported frequencies:
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304 // Fosc0 mul div PLL div2_en cpu_f pba_f Comment
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305 // 12 15 1 192 1 12 12
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306 // 12 9 3 40 1 20 20 PLL out of spec
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307 // 12 15 1 192 1 24 12
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308 // 12 9 1 120 1 30 15
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309 // 12 9 3 40 0 40 20 PLL out of spec
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310 // 12 15 1 192 1 48 12
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311 // 12 15 1 192 1 48 24
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312 // 12 8 1 108 1 54 27
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313 // 12 9 1 120 1 60 15
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314 // 12 9 1 120 1 60 30
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315 // 12 10 1 132 1 66 16.5
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317 unsigned long in_cpu_f = param->cpu_f;
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318 unsigned long in_osc0_f = param->osc0_f;
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319 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
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320 unsigned long pll_freq, rest;
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321 Bool b_div2_pba, b_div2_cpu;
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323 // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
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324 scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
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326 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
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327 // Set the main clock source as being OSC0.
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328 pm_set_mclk_source(PM_CLK_SRC_OSC0);
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330 // Start with CPU freq config
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331 if (in_cpu_f == in_osc0_f)
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333 param->cpu_f = in_osc0_f;
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334 param->pba_f = in_osc0_f;
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337 else if (in_cpu_f < in_osc0_f)
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342 rest = in_cpu_f % in_osc0_f;
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344 for (div = 1; div < 32; div++)
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346 if ((div * rest) % in_osc0_f == 0)
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352 mul = (in_cpu_f * div) / in_osc0_f;
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354 if (mul > PM_MAX_MUL)
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357 // export 2power from PLL div to div2_cpu
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364 // Here we know the mul and div parameter of the PLL config.
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365 // . Check out if the PLL has a valid in_cpu_f.
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366 // . Try to have for the PLL frequency (VCO output) the highest possible value
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367 // to reduce jitter.
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368 while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
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370 if (2 * mul > PM_MAX_MUL)
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382 pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
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384 // Update real CPU Frequency
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385 param->cpu_f = pll_freq / (1 << div2_cpu);
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388 scif_pll_opt_t opt;
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390 opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1
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391 opt.lockcount = 16, // lockcount in main clock for the PLL wait lock
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392 opt.div = div, // DIV=1 in the formula
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393 opt.mul = mul, // MUL=7 in the formula
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394 opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
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395 opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
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396 opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
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399 scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
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402 scif_pll_enable(SCIF_PLL0);
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404 /* Wait for PLL0 locked */
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405 scif_wait_for_pll_locked(SCIF_PLL0) ;
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408 while (rest > AVR32_PM_PBA_MAX_FREQ ||
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409 rest != param->pba_f)
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412 rest = pll_freq / (1 << div2_pba);
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413 if (rest < param->pba_f)
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417 // Update real PBA Frequency
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418 param->pba_f = pll_freq / (1 << div2_pba);
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427 b_div2_cpu = FALSE;
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435 b_div2_pba = FALSE;
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437 if (b_div2_cpu == TRUE )
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439 pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
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440 pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
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441 pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
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443 if (b_div2_pba == TRUE )
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445 pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
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446 pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
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449 // Set Flashc Wait State
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450 flashc_set_flash_waitstate_and_readmode(param->cpu_f);
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452 // Set the main clock source as being PLL0.
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453 pm_set_mclk_source(PM_CLK_SRC_PLL0);
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457 #endif // UC3C device-specific implementation
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459 long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
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461 #ifndef AVR32_PM_VERSION_RESETVALUE
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462 // Implementation for UC3A, UC3A3, UC3B parts.
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463 if(PCL_OSC0 == osc)
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465 // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
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466 // enable the OSC0, set the main clock source as being OSC0.
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467 pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
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471 return PCL_NOT_SUPPORTED;
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474 // Implementation for UC3C, UC3L parts.
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475 #if AVR32_PM_VERSION_RESETVALUE < 0x400
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476 return PCL_NOT_SUPPORTED;
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478 if(PCL_OSC0 == osc)
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480 // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
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481 scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
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483 scif_enable_osc(SCIF_OSC0, startup, true);
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484 // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
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486 flashcdw_set_flash_waitstate_and_readmode(fcrystal);
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488 flashc_set_flash_waitstate_and_readmode(fcrystal);
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490 // Set the main clock source as being OSC0.
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491 pm_set_mclk_source(PM_CLK_SRC_OSC0);
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495 return PCL_NOT_SUPPORTED;
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502 long int pcl_configure_usb_clock(void)
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504 #ifndef AVR32_PM_VERSION_RESETVALUE
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505 // Implementation for UC3A, UC3A3, UC3B parts.
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506 pm_configure_usb_clock();
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509 #ifdef AVR32_PM_410_H_INCLUDED
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510 const scif_pll_opt_t opt = {
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511 .osc = SCIF_OSC0, // Sel Osc0 or Osc1
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512 .lockcount = 16, // lockcount in main clock for the PLL wait lock
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513 .div = 1, // DIV=1 in the formula
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514 .mul = 5, // MUL=7 in the formula
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515 .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
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516 .pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
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517 .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
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520 /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
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521 scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
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524 scif_pll_enable(SCIF_PLL1);
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526 /* Wait for PLL1 locked */
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527 scif_wait_for_pll_locked(SCIF_PLL1) ;
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529 // Implementation for UC3C parts.
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530 // Setup the generic clock for USB
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531 scif_gc_setup(AVR32_SCIF_GCLK_USB,
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533 AVR32_SCIF_GC_NO_DIV_CLOCK,
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535 // Now enable the generic clock
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536 scif_gc_enable(AVR32_SCIF_GCLK_USB);
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539 return PCL_NOT_SUPPORTED;
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547 void pcl_write_gplp(unsigned long gplp, unsigned long value)
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549 #ifndef AVR32_PM_VERSION_RESETVALUE
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550 // Implementation for UC3A, UC3A3, UC3B parts.
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551 pm_write_gplp(&AVR32_PM,gplp,value);
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553 scif_write_gplp(gplp,value);
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557 unsigned long pcl_read_gplp(unsigned long gplp)
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559 #ifndef AVR32_PM_VERSION_RESETVALUE
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560 // Implementation for UC3A, UC3A3, UC3B parts.
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561 return pm_read_gplp(&AVR32_PM,gplp);
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563 return scif_read_gplp(gplp);
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