1 /* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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3 /*This file is prepared for Doxygen automatic documentation generation.*/
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4 /*! \file *********************************************************************
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6 * \brief Compiler file for AVR32.
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8 * This file defines commonly used types and macros.
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10 * - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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11 * - Supported devices: All AVR32 devices can be used.
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14 * \author Atmel Corporation: http://www.atmel.com \n
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15 * Support and FAQ: http://support.atmel.no/
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17 ******************************************************************************/
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19 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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21 * Redistribution and use in source and binary forms, with or without
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22 * modification, are permitted provided that the following conditions are met:
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24 * 1. Redistributions of source code must retain the above copyright notice, this
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25 * list of conditions and the following disclaimer.
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27 * 2. Redistributions in binary form must reproduce the above copyright notice,
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28 * this list of conditions and the following disclaimer in the documentation
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29 * and/or other materials provided with the distribution.
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31 * 3. The name of Atmel may not be used to endorse or promote products derived
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32 * from this software without specific prior written permission.
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34 * 4. This software may only be redistributed and used in connection with an Atmel
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37 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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38 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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40 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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41 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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44 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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46 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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50 #ifndef _COMPILER_H_
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51 #define _COMPILER_H_
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53 #if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__)
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54 # include <avr32/io.h>
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56 #if (defined __ICCAVR32__)
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57 # include <intrinsics.h>
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59 #include "preprocessor.h"
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64 //_____ D E C L A R A T I O N S ____________________________________________
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66 #ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
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72 #if (defined __ICCAVR32__)
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74 /*! \name Compiler Keywords
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76 * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
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80 #define __inline__ inline
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81 #define __volatile__
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87 /*! \name Usual Types
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90 typedef unsigned char Bool; //!< Boolean.
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92 #if !defined(__bool_true_false_are_defined)
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93 typedef unsigned char bool; //!< Boolean.
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96 typedef signed char S8 ; //!< 8-bit signed integer.
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97 typedef unsigned char U8 ; //!< 8-bit unsigned integer.
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98 typedef signed short int S16; //!< 16-bit signed integer.
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99 typedef unsigned short int U16; //!< 16-bit unsigned integer.
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100 typedef signed long int S32; //!< 32-bit signed integer.
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101 typedef unsigned long int U32; //!< 32-bit unsigned integer.
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102 typedef signed long long int S64; //!< 64-bit signed integer.
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103 typedef unsigned long long int U64; //!< 64-bit unsigned integer.
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104 typedef float F32; //!< 32-bit floating-point number.
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105 typedef double F64; //!< 64-bit floating-point number.
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109 /*! \name Status Types
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112 typedef Bool Status_bool_t; //!< Boolean status.
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113 typedef U8 Status_t; //!< 8-bit-coded status.
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117 /*! \name Aliasing Aggregate Types
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154 //! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
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167 //! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
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170 volatile S64 *s64ptr;
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171 volatile U64 *u64ptr;
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172 volatile S32 *s32ptr;
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173 volatile U32 *u32ptr;
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174 volatile S16 *s16ptr;
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175 volatile U16 *u16ptr;
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176 volatile S8 *s8ptr ;
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177 volatile U8 *u8ptr ;
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180 //! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
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193 //! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
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196 const volatile S64 *s64ptr;
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197 const volatile U64 *u64ptr;
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198 const volatile S32 *s32ptr;
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199 const volatile U32 *u32ptr;
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200 const volatile S16 *s16ptr;
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201 const volatile U16 *u16ptr;
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202 const volatile S8 *s8ptr ;
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203 const volatile U8 *u8ptr ;
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206 //! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
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219 //! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
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222 volatile S64 *s64ptr;
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223 volatile U64 *u64ptr;
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224 volatile S32 *s32ptr;
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225 volatile U32 *u32ptr;
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226 volatile S16 *s16ptr;
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227 volatile U16 *u16ptr;
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228 volatile S8 *s8ptr ;
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229 volatile U8 *u8ptr ;
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232 //! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
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245 //! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
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248 const volatile S64 *s64ptr;
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249 const volatile U64 *u64ptr;
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250 const volatile S32 *s32ptr;
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251 const volatile U32 *u32ptr;
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252 const volatile S16 *s16ptr;
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253 const volatile U16 *u16ptr;
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254 const volatile S8 *s8ptr ;
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255 const volatile U8 *u8ptr ;
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260 #endif // __AVR32_ABI_COMPILER__
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263 //_____ M A C R O S ________________________________________________________
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265 /*! \name Usual Constants
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276 #ifndef __cplusplus
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277 #if !defined(__bool_true_false_are_defined)
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278 #define false FALSE
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293 #ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
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295 /*! \name Bit-Field Handling
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299 /*! \brief Reads the bits of a value specified by a given bit-mask.
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301 * \param value Value to read bits from.
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302 * \param mask Bit-mask indicating bits to read.
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304 * \return Read bits.
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306 #define Rd_bits( value, mask) ((value) & (mask))
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308 /*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
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310 * \param lvalue C lvalue to write bits to.
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311 * \param mask Bit-mask indicating bits to write.
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312 * \param bits Bits to write.
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314 * \return Resulting value with written bits.
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316 #define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
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317 ((bits ) & (mask)))
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319 /*! \brief Tests the bits of a value specified by a given bit-mask.
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321 * \param value Value of which to test bits.
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322 * \param mask Bit-mask indicating bits to test.
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324 * \return \c 1 if at least one of the tested bits is set, else \c 0.
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326 #define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)
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328 /*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
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330 * \param lvalue C lvalue of which to clear bits.
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331 * \param mask Bit-mask indicating bits to clear.
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333 * \return Resulting value with cleared bits.
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335 #define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
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337 /*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
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339 * \param lvalue C lvalue of which to set bits.
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340 * \param mask Bit-mask indicating bits to set.
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342 * \return Resulting value with set bits.
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344 #define Set_bits(lvalue, mask) ((lvalue) |= (mask))
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346 /*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
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348 * \param lvalue C lvalue of which to toggle bits.
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349 * \param mask Bit-mask indicating bits to toggle.
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351 * \return Resulting value with toggled bits.
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353 #define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
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355 /*! \brief Reads the bit-field of a value specified by a given bit-mask.
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357 * \param value Value to read a bit-field from.
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358 * \param mask Bit-mask indicating the bit-field to read.
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360 * \return Read bit-field.
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362 #define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))
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364 /*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
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366 * \param lvalue C lvalue to write a bit-field to.
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367 * \param mask Bit-mask indicating the bit-field to write.
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368 * \param bitfield Bit-field to write.
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370 * \return Resulting value with written bit-field.
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372 #define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
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377 /*! \brief This macro is used to test fatal errors.
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379 * The macro tests if the expression is FALSE. If it is, a fatal error is
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380 * detected and the application hangs up.
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382 * \param expr Expression to evaluate and supposed to be nonzero.
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384 #ifdef _ASSERT_ENABLE_
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385 #define Assert(expr) \
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387 if (!(expr)) while (TRUE);\
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390 #define Assert(expr)
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394 /*! \name Zero-Bit Counting
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396 * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when
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397 * applied to constant expressions (values known at compile time), so they are
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398 * more optimized than the use of the corresponding assembly instructions and
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399 * they can be used as constant expressions e.g. to initialize objects having
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400 * static storage duration, and like the corresponding assembly instructions
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401 * when applied to non-constant expressions (values unknown at compile time), so
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402 * they are more optimized than an assembly periphrasis. Hence, clz and ctz
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403 * ensure a possible and optimized behavior for both constant and non-constant
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408 /*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
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410 * \param u Value of which to count the leading zero bits.
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412 * \return The count of leading zero bits in \a u.
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414 #if (defined __GNUC__)
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415 #define clz(u) __builtin_clz(u)
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416 #elif (defined __ICCAVR32__)
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417 #define clz(u) __count_leading_zeros(u)
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420 /*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
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422 * \param u Value of which to count the trailing zero bits.
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424 * \return The count of trailing zero bits in \a u.
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426 #if (defined __GNUC__)
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427 #define ctz(u) __builtin_ctz(u)
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428 #elif (defined __ICCAVR32__)
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429 #define ctz(u) __count_trailing_zeros(u)
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435 /*! \name Bit Reversing
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439 /*! \brief Reverses the bits of \a u8.
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441 * \param u8 U8 of which to reverse the bits.
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443 * \return Value resulting from \a u8 with reversed bits.
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445 #define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
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447 /*! \brief Reverses the bits of \a u16.
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449 * \param u16 U16 of which to reverse the bits.
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451 * \return Value resulting from \a u16 with reversed bits.
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453 #define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))
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455 /*! \brief Reverses the bits of \a u32.
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457 * \param u32 U32 of which to reverse the bits.
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459 * \return Value resulting from \a u32 with reversed bits.
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461 #if (defined __GNUC__)
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462 #define bit_reverse32(u32) \
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465 unsigned int __value = (U32)(u32);\
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466 __asm__ ("brev\t%0" : "+r" (__value) : : "cc");\
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470 #elif (defined __ICCAVR32__)
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471 #define bit_reverse32(u32) ((U32)__bit_reverse((U32)(u32)))
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474 /*! \brief Reverses the bits of \a u64.
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476 * \param u64 U64 of which to reverse the bits.
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478 * \return Value resulting from \a u64 with reversed bits.
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480 #define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\
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481 ((U64)bit_reverse32((U64)(u64)) << 32)))
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486 /*! \name Alignment
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490 /*! \brief Tests alignment of the number \a val with the \a n boundary.
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492 * \param val Input value.
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493 * \param n Boundary.
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495 * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
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497 #define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )
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499 /*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
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501 * \param val Input value.
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502 * \param n Boundary.
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504 * \return Alignment of the number \a val with respect to the \a n boundary.
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506 #define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )
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508 /*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
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510 * \param lval Input/output lvalue.
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511 * \param n Boundary.
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512 * \param alg Alignment.
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514 * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
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516 #define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )
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518 /*! \brief Aligns the number \a val with the upper \a n boundary.
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520 * \param val Input value.
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521 * \param n Boundary.
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523 * \return Value resulting from the number \a val aligned with the upper \a n boundary.
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525 #define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))
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527 /*! \brief Aligns the number \a val with the lower \a n boundary.
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529 * \param val Input value.
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530 * \param n Boundary.
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532 * \return Value resulting from the number \a val aligned with the lower \a n boundary.
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534 #define Align_down(val, n ) ( (val) & ~((n) - 1))
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539 /*! \name Mathematics
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541 * The same considerations as for clz and ctz apply here but AVR32-GCC does not
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542 * provide built-in functions to access the assembly instructions abs, min and
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543 * max and it does not produce them by itself in most cases, so two sets of
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544 * macros are defined here:
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545 * - Abs, Min and Max to apply to constant expressions (values known at
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547 * - abs, min and max to apply to non-constant expressions (values unknown at
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552 /*! \brief Takes the absolute value of \a a.
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554 * \param a Input value.
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556 * \return Absolute value of \a a.
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558 * \note More optimized if only used with values known at compile time.
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560 #define Abs(a) (((a) < 0 ) ? -(a) : (a))
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562 /*! \brief Takes the minimal value of \a a and \a b.
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564 * \param a Input value.
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565 * \param b Input value.
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567 * \return Minimal value of \a a and \a b.
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569 * \note More optimized if only used with values known at compile time.
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571 #define Min(a, b) (((a) < (b)) ? (a) : (b))
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573 /*! \brief Takes the maximal value of \a a and \a b.
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575 * \param a Input value.
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576 * \param b Input value.
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578 * \return Maximal value of \a a and \a b.
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580 * \note More optimized if only used with values known at compile time.
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582 #define Max(a, b) (((a) > (b)) ? (a) : (b))
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584 /*! \brief Takes the absolute value of \a a.
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586 * \param a Input value.
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588 * \return Absolute value of \a a.
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590 * \note More optimized if only used with values unknown at compile time.
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592 #if (defined __GNUC__)
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596 int __value = (a);\
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597 __asm__ ("abs\t%0" : "+r" (__value) : : "cc");\
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601 #elif (defined __ICCAVR32__)
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602 #define abs(a) Abs(a)
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605 /*! \brief Takes the minimal value of \a a and \a b.
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607 * \param a Input value.
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608 * \param b Input value.
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610 * \return Minimal value of \a a and \a b.
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612 * \note More optimized if only used with values unknown at compile time.
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614 #if (defined __GNUC__)
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615 #define min(a, b) \
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618 int __value, __arg_a = (a), __arg_b = (b);\
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619 __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
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623 #elif (defined __ICCAVR32__)
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624 #define min(a, b) __min(a, b)
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627 /*! \brief Takes the maximal value of \a a and \a b.
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629 * \param a Input value.
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630 * \param b Input value.
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632 * \return Maximal value of \a a and \a b.
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634 * \note More optimized if only used with values unknown at compile time.
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636 #if (defined __GNUC__)
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637 #define max(a, b) \
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640 int __value, __arg_a = (a), __arg_b = (b);\
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641 __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
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645 #elif (defined __ICCAVR32__)
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646 #define max(a, b) __max(a, b)
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652 /*! \brief Calls the routine at address \a addr.
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654 * It generates a long call opcode.
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656 * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
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657 * it is invoked from the CPU supervisor mode.
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659 * \param addr Address of the routine to call.
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661 * \note It may be used as a long jump opcode in some special cases.
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663 #define Long_call(addr) ((*(void (*)(void))(addr))())
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665 /*! \brief Resets the CPU by software.
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667 * \warning It shall not be called from the CPU application mode.
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669 #if (defined __GNUC__)
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670 #define Reset_CPU() \
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673 __asm__ __volatile__ (\
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674 "lddpc r9, 3f\n\t"\
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675 "mfsr r8, %[SR]\n\t"\
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676 "bfextu r8, r8, %[SR_M_OFFSET], %[SR_M_SIZE]\n\t"\
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677 "cp.w r8, 0b001\n\t"\
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679 "sub r8, pc, $ - 1f\n\t"\
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683 "mtsr %[SR], r9\n"\
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699 "stdsp sp[0], sp\n\t"\
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700 "ldmts sp, sp\n\t"\
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702 "lddpc pc, 2f\n\t"\
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707 ".word %[RESET_SR]"\
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709 : [SR] "i" (AVR32_SR),\
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710 [SR_M_OFFSET] "i" (AVR32_SR_M_OFFSET),\
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711 [SR_M_SIZE] "i" (AVR32_SR_M_SIZE),\
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712 [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))\
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716 #elif (defined __ICCAVR32__)
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717 #define Reset_CPU() \
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719 extern void *volatile __program_start;\
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720 __asm__ __volatile__ (\
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721 "mov r7, LWRD(__program_start)\n\t"\
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722 "orh r7, HWRD(__program_start)\n\t"\
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723 "mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\
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724 "orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | (AVR32_SR_M_SUP << AVR32_SR_M_OFFSET))")\n\t"\
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725 "mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\
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726 "bfextu r8, r8, "ASTRINGZ(AVR32_SR_M_OFFSET)", "ASTRINGZ(AVR32_SR_M_SIZE)"\n\t"\
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727 "cp.w r8, 001b\n\t"\
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729 "sub r8, pc, -12\n\t"\
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732 "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\
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740 "st.w r0[4], r7\n\t"\
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748 "stdsp sp[0], sp\n\t"\
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749 "ldmts sp, sp\n\t"\
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758 /*! \name System Register Access
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762 /*! \brief Gets the value of the \a sysreg system register.
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764 * \param sysreg Address of the system register of which to get the value.
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766 * \return Value of the \a sysreg system register.
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768 #if (defined __GNUC__)
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769 #define Get_system_register(sysreg) __builtin_mfsr(sysreg)
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770 #elif (defined __ICCAVR32__)
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771 #define Get_system_register(sysreg) __get_system_register(sysreg)
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774 /*! \brief Sets the value of the \a sysreg system register to \a value.
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776 * \param sysreg Address of the system register of which to set the value.
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777 * \param value Value to set the \a sysreg system register to.
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779 #if (defined __GNUC__)
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780 #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)
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781 #elif (defined __ICCAVR32__)
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782 #define Set_system_register(sysreg, value) __set_system_register(sysreg, value)
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788 /*! \name CPU Status Register Access
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792 /*! \brief Tells whether exceptions are globally enabled.
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794 * \return \c 1 if exceptions are globally enabled, else \c 0.
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796 #define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))
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798 /*! \brief Disables exceptions globally.
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800 #if (defined __GNUC__)
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801 #define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
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802 #elif (defined __ICCAVR32__)
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803 #define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))
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806 /*! \brief Enables exceptions globally.
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808 #if (defined __GNUC__)
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809 #define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})
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810 #elif (defined __ICCAVR32__)
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811 #define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))
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814 /*! \brief Tells whether interrupts are globally enabled.
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816 * \return \c 1 if interrupts are globally enabled, else \c 0.
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818 #define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))
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820 /*! \brief Disables interrupts globally.
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822 #if (defined __GNUC__)
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823 #define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})
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824 #elif (defined __ICCAVR32__)
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825 #define Disable_global_interrupt() (__disable_interrupt())
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828 /*! \brief Enables interrupts globally.
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830 #if (defined __GNUC__)
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831 #define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})
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832 #elif (defined __ICCAVR32__)
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833 #define Enable_global_interrupt() (__enable_interrupt())
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836 /*! \brief Tells whether interrupt level \a int_level is enabled.
\r
838 * \param int_level Interrupt level (0 to 3).
\r
840 * \return \c 1 if interrupt level \a int_level is enabled, else \c 0.
\r
842 #define Is_interrupt_level_enabled(int_level) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_level, M_MASK)))
\r
844 /*! \brief Disables interrupt level \a int_level.
\r
846 * \param int_level Interrupt level to disable (0 to 3).
\r
848 #if (defined __GNUC__)
\r
849 #define Disable_interrupt_level(int_level) ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})
\r
850 #elif (defined __ICCAVR32__)
\r
851 #define Disable_interrupt_level(int_level) (__set_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))
\r
854 /*! \brief Enables interrupt level \a int_level.
\r
856 * \param int_level Interrupt level to enable (0 to 3).
\r
858 #if (defined __GNUC__)
\r
859 #define Enable_interrupt_level(int_level) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})
\r
860 #elif (defined __ICCAVR32__)
\r
861 #define Enable_interrupt_level(int_level) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))
\r
864 /*! \brief Protects subsequent code from interrupts.
\r
866 #define AVR32_ENTER_CRITICAL_REGION( ) \
\r
868 Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
\r
869 Disable_global_interrupt(); // Disable the appropriate interrupts.
\r
871 /*! \brief This macro must always be used in conjunction with AVR32_ENTER_CRITICAL_REGION
\r
872 * so that interrupts are enabled again.
\r
874 #define AVR32_LEAVE_CRITICAL_REGION( ) \
\r
875 if (global_interrupt_enabled) Enable_global_interrupt(); \
\r
881 /*! \name Debug Register Access
\r
885 /*! \brief Gets the value of the \a dbgreg debug register.
\r
887 * \param dbgreg Address of the debug register of which to get the value.
\r
889 * \return Value of the \a dbgreg debug register.
\r
891 #if (defined __GNUC__)
\r
892 #define Get_debug_register(dbgreg) __builtin_mfdr(dbgreg)
\r
893 #elif (defined __ICCAVR32__)
\r
894 #define Get_debug_register(dbgreg) __get_debug_register(dbgreg)
\r
897 /*! \brief Sets the value of the \a dbgreg debug register to \a value.
\r
899 * \param dbgreg Address of the debug register of which to set the value.
\r
900 * \param value Value to set the \a dbgreg debug register to.
\r
902 #if (defined __GNUC__)
\r
903 #define Set_debug_register(dbgreg, value) __builtin_mtdr(dbgreg, value)
\r
904 #elif (defined __ICCAVR32__)
\r
905 #define Set_debug_register(dbgreg, value) __set_debug_register(dbgreg, value)
\r
910 #endif // __AVR32_ABI_COMPILER__
\r
913 //! Boolean evaluating MCU little endianism.
\r
914 #if ((defined __GNUC__) && (defined __AVR32__)) || ((defined __ICCAVR32__) || (defined __AAVR32__))
\r
915 #define LITTLE_ENDIAN_MCU FALSE
\r
917 #error If you are here, you should check what is exactly the processor you are using...
\r
918 #define LITTLE_ENDIAN_MCU FALSE
\r
921 // Check that MCU endianism is correctly defined.
\r
922 #ifndef LITTLE_ENDIAN_MCU
\r
923 #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE
\r
926 //! Boolean evaluating MCU big endianism.
\r
927 #define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU)
\r
930 #ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
\r
932 /*! \name MCU Endianism Handling
\r
936 #if (LITTLE_ENDIAN_MCU==TRUE)
\r
937 #define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
\r
938 #define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
\r
940 #define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
\r
941 #define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
\r
942 #define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32.
\r
943 #define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32.
\r
944 #define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32.
\r
945 #define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32.
\r
946 #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32.
\r
947 #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32.
\r
948 #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32.
\r
949 #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32.
\r
951 #define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
\r
952 #define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
\r
953 #define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64.
\r
954 #define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64.
\r
955 #define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64.
\r
956 #define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64.
\r
957 #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64.
\r
958 #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64.
\r
959 #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64.
\r
960 #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64.
\r
961 #define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64.
\r
962 #define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64.
\r
963 #define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64.
\r
964 #define LSB3D(u64) (((U8 *)&(u64))[3]) //!< Least significant byte of 4th rank of \a u64.
\r
965 #define LSB4D(u64) (((U8 *)&(u64))[4]) //!< Least significant byte of 5th rank of \a u64.
\r
966 #define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64.
\r
967 #define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64.
\r
968 #define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64.
\r
969 #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64.
\r
970 #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64.
\r
971 #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64.
\r
972 #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64.
\r
973 #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64.
\r
974 #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64.
\r
975 #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64.
\r
976 #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64.
\r
978 #elif (BIG_ENDIAN_MCU==TRUE)
\r
979 #define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.
\r
980 #define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.
\r
982 #define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.
\r
983 #define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.
\r
984 #define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.
\r
985 #define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.
\r
986 #define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.
\r
987 #define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.
\r
988 #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
\r
989 #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
\r
990 #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
\r
991 #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
\r
993 #define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.
\r
994 #define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.
\r
995 #define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.
\r
996 #define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.
\r
997 #define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.
\r
998 #define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.
\r
999 #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
\r
1000 #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
\r
1001 #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
\r
1002 #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
\r
1003 #define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.
\r
1004 #define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.
\r
1005 #define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.
\r
1006 #define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64.
\r
1007 #define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64.
\r
1008 #define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.
\r
1009 #define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.
\r
1010 #define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.
\r
1011 #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
\r
1012 #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
\r
1013 #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
\r
1014 #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
\r
1015 #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
\r
1016 #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
\r
1017 #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
\r
1018 #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
\r
1021 #error Unknown endianism.
\r
1027 /*! \name Endianism Conversion
\r
1029 * The same considerations as for clz and ctz apply here but AVR32-GCC's
\r
1030 * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when
\r
1031 * applied to constant expressions, so two sets of macros are defined here:
\r
1032 * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
\r
1033 * at compile time);
\r
1034 * - swap16, swap32 and swap64 to apply to non-constant expressions (values
\r
1035 * unknown at compile time).
\r
1039 /*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
\r
1041 * \param u16 U16 of which to toggle the endianism.
\r
1043 * \return Value resulting from \a u16 with toggled endianism.
\r
1045 * \note More optimized if only used with values known at compile time.
\r
1047 #define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
\r
1048 ((U16)(u16) << 8)))
\r
1050 /*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
\r
1052 * \param u32 U32 of which to toggle the endianism.
\r
1054 * \return Value resulting from \a u32 with toggled endianism.
\r
1056 * \note More optimized if only used with values known at compile time.
\r
1058 #define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
\r
1059 ((U32)Swap16((U32)(u32)) << 16)))
\r
1061 /*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
\r
1063 * \param u64 U64 of which to toggle the endianism.
\r
1065 * \return Value resulting from \a u64 with toggled endianism.
\r
1067 * \note More optimized if only used with values known at compile time.
\r
1069 #define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
\r
1070 ((U64)Swap32((U64)(u64)) << 32)))
\r
1072 /*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
\r
1074 * \param u16 U16 of which to toggle the endianism.
\r
1076 * \return Value resulting from \a u16 with toggled endianism.
\r
1078 * \note More optimized if only used with values unknown at compile time.
\r
1080 #if (defined __GNUC__)
\r
1081 #define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16)))
\r
1082 #elif (defined __ICCAVR32__)
\r
1083 #define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16)))
\r
1086 /*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
\r
1088 * \param u32 U32 of which to toggle the endianism.
\r
1090 * \return Value resulting from \a u32 with toggled endianism.
\r
1092 * \note More optimized if only used with values unknown at compile time.
\r
1094 #if (defined __GNUC__)
\r
1095 #define swap32(u32) ((U32)__builtin_bswap_32((U32)(u32)))
\r
1096 #elif (defined __ICCAVR32__)
\r
1097 #define swap32(u32) ((U32)__swap_bytes((U32)(u32)))
\r
1100 /*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
\r
1102 * \param u64 U64 of which to toggle the endianism.
\r
1104 * \return Value resulting from \a u64 with toggled endianism.
\r
1106 * \note More optimized if only used with values unknown at compile time.
\r
1108 #define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
\r
1109 ((U64)swap32((U64)(u64)) << 32)))
\r
1114 /*! \name Target Abstraction
\r
1118 #define _GLOBEXT_ extern //!< extern storage-class specifier.
\r
1119 #define _CONST_TYPE_ const //!< const type qualifier.
\r
1120 #define _MEM_TYPE_SLOW_ //!< Slow memory type.
\r
1121 #define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.
\r
1122 #define _MEM_TYPE_FAST_ //!< Fast memory type.
\r
1124 typedef U8 Byte; //!< 8-bit unsigned integer.
\r
1126 #define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.
\r
1127 #define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.
\r
1128 #define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.
\r
1129 #define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.
\r
1131 #define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
\r
1132 #define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
\r
1133 #define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
\r
1134 #define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
\r
1135 #define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
\r
1136 #define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
\r
1137 #define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
\r
1138 #define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
\r
1142 #endif // __AVR32_ABI_COMPILER__
\r
1145 #endif // _COMPILER_H_
\r