1 /* This file is part of the ATMEL AVR32-SoftwareFramework-AT32UC3-1.5.0 Release */
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3 /*This file is prepared for Doxygen automatic documentation generation.*/
4 /*! \file *********************************************************************
6 * \brief Exception and interrupt vectors.
8 * This file maps all events supported by an AVR32.
10 * - Compiler: GNU GCC for AVR32
11 * - Supported devices: All AVR32 devices with an INTC module can be used.
14 * \author Atmel Corporation: http://www.atmel.com \n
15 * Support and FAQ: http://support.atmel.no/
17 ******************************************************************************/
19 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
24 * 1. Redistributions of source code must retain the above copyright notice, this
25 * list of conditions and the following disclaimer.
27 * 2. Redistributions in binary form must reproduce the above copyright notice,
28 * this list of conditions and the following disclaimer in the documentation
29 * and/or other materials provided with the distribution.
31 * 3. The name of Atmel may not be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * 4. This software may only be redistributed and used in connection with an Atmel
37 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
38 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
39 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
40 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
41 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
44 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
46 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
50 #if !__AVR32_UC__ && !__AVR32_AP__
51 #error Implementation of the AVR32 architecture not supported by the INTC driver.
62 .section .exception, "ax", @progbits
65 // Start of Exception Vector Table.
67 // EVBA must be aligned with a power of two strictly greater than the EVBA-
68 // relative offset of the last vector.
73 .type _evba, @function
77 // Unrecoverable Exception.
78 _handle_Unrecoverable_Exception:
83 _handle_TLB_Multiple_Hit:
87 // Bus Error Data Fetch.
88 _handle_Bus_Error_Data_Fetch:
92 // Bus Error Instruction Fetch.
93 _handle_Bus_Error_Instruction_Fetch:
102 // Instruction Address.
103 _handle_Instruction_Address:
108 _handle_ITLB_Protection:
118 _handle_Illegal_Opcode:
122 // Unimplemented Instruction.
123 _handle_Unimplemented_Instruction:
127 // Privilege Violation.
128 _handle_Privilege_Violation:
132 // Floating-Point: UNUSED IN AVR32UC and AVR32AP.
133 _handle_Floating_Point:
137 // Coprocessor Absent: UNUSED IN AVR32UC.
138 _handle_Coprocessor_Absent:
142 // Data Address (Read).
143 _handle_Data_Address_Read:
147 // Data Address (Write).
148 _handle_Data_Address_Write:
152 // DTLB Protection (Read).
153 _handle_DTLB_Protection_Read:
157 // DTLB Protection (Write).
158 _handle_DTLB_Protection_Write:
162 // DTLB Modified: UNUSED IN AVR32UC.
163 _handle_DTLB_Modified:
173 _handle_DTLB_Miss_Read:
177 // DTLB Miss (Write).
178 _handle_DTLB_Miss_Write:
183 _handle_Supervisor_Call:
184 lda.w pc, SCALLYield
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187 // Interrupt support.
188 // The interrupt controller must provide the offset address relative to EVBA.
190 // All interrupts call a C function named _get_interrupt_handler.
191 // This function will read group and interrupt line number to then return in
192 // R12 a pointer to a user-provided interrupt handler.
196 .irp priority, 0, 1, 2, 3
199 // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
200 // CPU upon interrupt entry. No other register is saved by hardware.
202 // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
203 // the CPU upon interrupt entry. No other register is saved by hardware.
206 mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
207 call _get_interrupt_handler
208 cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
210 movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
212 breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch.
213 st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
214 popm r8-r12, lr, pc // Restore registers and jump to the handler.
218 rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
222 // Constant data area.
226 // Values to store in the interrupt priority registers for the various interrupt priority levels.
227 // The interrupt priority registers contain the interrupt priority level and
228 // the EVBA-relative interrupt vector offset.
230 .type ipr_val, @object
232 .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
233 (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
234 (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
235 (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)