1 /*******************************************************************************
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2 * (c) Copyright 2009 Actel Corporation. All rights reserved.
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4 * SmartFusion A2FxxxM3 Cortex Microcontroller Software Interface - Peripheral
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7 * This file describes the interrupt assignment and peripheral registers for
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8 * the SmartFusion A2FxxxM3 familly of devices.
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10 * SVN $Revision: 2331 $
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11 * SVN $Date: 2010-02-26 12:02:06 +0000 (Fri, 26 Feb 2010) $
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13 #ifndef __A2FXXXM3_H__
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14 #define __A2FXXXM3_H__
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21 * ==========================================================================
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22 * ---------- Interrupt Number Definition -----------------------------------
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23 * ==========================================================================
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28 /****** Cortex-M3 Processor Exceptions Numbers *********************************************************/
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29 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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30 HardFault_IRQn = -13, /*!< 2 Hard Fault Interrupt */
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31 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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32 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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33 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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34 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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35 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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36 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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37 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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39 /****** SmartFusion specific Interrupt Numbers *********************************************************/
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40 WdogWakeup_IRQn = 0, /*!< WatchDog wakeup interrupt */
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41 BrownOut_1_5V_IRQn = 1, /*!< Supply dropped below 1.5V */
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42 BrownOut_3_3V_IRQn = 2, /*!< Supply dropped below 1.5V */
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43 RTC_Match_IRQn = 3, /*!< RTC match interrupt */
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44 RTCIF_Pub_IRQn = 4, /*!< RTC interface push button interrupt */
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45 EthernetMAC_IRQn = 5, /*!< Ethernet MAC interrupt */
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46 IAP_IRQn = 6, /*!< In Application Programming (IAP) interrupt */
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47 ENVM0_IRQn = 7, /*!< eNVM0 operation completion interrupt */
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48 ENVM1_IRQn = 8, /*!< eNVM1 operation completion interrupt */
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49 DMA_IRQn = 9, /*!< Peripheral DMA interrupt */
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50 UART0_IRQn = 10, /*!< UART0 interrupt */
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51 UART1_IRQn = 11, /*!< UART1 interrupt */
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52 SPI0_IRQn = 12, /*!< SPI0 interrupt */
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53 SPI1_IRQn = 13, /*!< SP1 interrupt */
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54 I2C0_IRQn = 14, /*!< I2C0 interrupt */
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55 I2C0_SMBAlert_IRQn = 15, /*!< I2C0 SMBus Alert interrupt */
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56 I2C0_SMBus_IRQn = 16, /*!< I2C0 SMBus Suspend interrupt */
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57 I2C1_IRQn = 17, /*!< I2C1 interrupt */
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58 I2C1_SMBAlert_IRQn = 18, /*!< I2C1 SMBus Alert interrupt */
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59 I2C1_SMBus_IRQn = 19, /*!< I2C1 SMBus Suspend interrupt */
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60 Timer1_IRQn = 20, /*!< Timer1 interrupt */
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61 Timer2_IRQn = 21, /*!< Timer2 interrupt */
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62 PLL_Lock_IRQn = 22, /*!< PLL lock interrupt */
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63 PLL_LockLost_IRQn = 23, /*!< PLL loss of lock interrupt */
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64 CommError_IRQn = 24, /*!< Communications Matrix error interrupt */
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65 Fabric_IRQn = 31, /*!< FPGA fabric interrupt */
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66 GPIO0_IRQn = 32, /*!< GPIO 0 interrupt */
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67 GPIO1_IRQn = 33, /*!< GPIO 1 interrupt */
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68 GPIO2_IRQn = 34, /*!< GPIO 2 interrupt */
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69 GPIO3_IRQn = 35, /*!< GPIO 3 interrupt */
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70 GPIO4_IRQn = 36, /*!< GPIO 4 interrupt */
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71 GPIO5_IRQn = 37, /*!< GPIO 5 interrupt */
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72 GPIO6_IRQn = 38, /*!< GPIO 6 interrupt */
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73 GPIO7_IRQn = 39, /*!< GPIO 7 interrupt */
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74 GPIO8_IRQn = 40, /*!< GPIO 8 interrupt */
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75 GPIO9_IRQn = 41, /*!< GPIO 9 interrupt */
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76 GPIO10_IRQn = 42, /*!< GPIO 10 interrupt */
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77 GPIO11_IRQn = 43, /*!< GPIO 11 interrupt */
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78 GPIO12_IRQn = 44, /*!< GPIO 12 interrupt */
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79 GPIO13_IRQn = 45, /*!< GPIO 13 interrupt */
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80 GPIO14_IRQn = 46, /*!< GPIO 14 interrupt */
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81 GPIO15_IRQn = 47, /*!< GPIO 15 interrupt */
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82 GPIO16_IRQn = 48, /*!< GPIO 16 interrupt */
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83 GPIO17_IRQn = 49, /*!< GPIO 17 interrupt */
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84 GPIO18_IRQn = 50, /*!< GPIO 18 interrupt */
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85 GPIO19_IRQn = 51, /*!< GPIO 19 interrupt */
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86 GPIO20_IRQn = 52, /*!< GPIO 20 interrupt */
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87 GPIO21_IRQn = 53, /*!< GPIO 21 interrupt */
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88 GPIO22_IRQn = 54, /*!< GPIO 22 interrupt */
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89 GPIO23_IRQn = 55, /*!< GPIO 23 interrupt */
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90 GPIO24_IRQn = 56, /*!< GPIO 24 interrupt */
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91 GPIO25_IRQn = 57, /*!< GPIO 25 interrupt */
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92 GPIO26_IRQn = 58, /*!< GPIO 26 interrupt */
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93 GPIO27_IRQn = 59, /*!< GPIO 27 interrupt */
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94 GPIO28_IRQn = 60, /*!< GPIO 28 interrupt */
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95 GPIO29_IRQn = 61, /*!< GPIO 29 interrupt */
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96 GPIO30_IRQn = 62, /*!< GPIO 30 interrupt */
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97 GPIO31_IRQn = 63, /*!< GPIO 31 interrupt */
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98 ACE_PC0_Flag0_IRQn = 64, /*!< ACE SSE program counter 0 flag 0 interrupt */
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99 ACE_PC0_Flag1_IRQn = 65, /*!< ACE SSE program counter 0 flag 1 interrupt */
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100 ACE_PC0_Flag2_IRQn = 66, /*!< ACE SSE program counter 0 flag 2 interrupt */
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101 ACE_PC0_Flag3_IRQn = 67, /*!< ACE SSE program counter 0 flag 3 interrupt */
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102 ACE_PC1_Flag0_IRQn = 68, /*!< ACE SSE program counter 1 flag 0 interrupt */
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103 ACE_PC1_Flag1_IRQn = 69, /*!< ACE SSE program counter 1 flag 1 interrupt */
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104 ACE_PC1_Flag2_IRQn = 70, /*!< ACE SSE program counter 1 flag 2 interrupt */
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105 ACE_PC1_Flag3_IRQn = 71, /*!< ACE SSE program counter 1 flag 3 interrupt */
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106 ACE_PC2_Flag0_IRQn = 72, /*!< ACE SSE program counter 2 flag 0 interrupt */
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107 ACE_PC2_Flag1_IRQn = 73, /*!< ACE SSE program counter 2 flag 1 interrupt */
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108 ACE_PC2_Flag2_IRQn = 74, /*!< ACE SSE program counter 2 flag 2 interrupt */
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109 ACE_PC2_Flag3_IRQn = 75, /*!< ACE SSE program counter 2 flag 3 interrupt */
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110 ACE_ADC0_DataValid_IRQn = 76, /*!< ACE ADC0 data valid interrupt */
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111 ACE_ADC1_DataValid_IRQn = 77, /*!< ACE ADC1 data valid interrupt */
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112 ACE_ADC2_DataValid_IRQn = 78, /*!< ACE ADC2 data valid interrupt */
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113 ACE_ADC0_CalDone_IRQn = 79, /*!< ACE ADC0 calibration done interrupt */
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114 ACE_ADC1_CalDone_IRQn = 80, /*!< ACE ADC1 calibration done interrupt */
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115 ACE_ADC2_CalDone_IRQn = 81, /*!< ACE ADC2 calibration done interrupt */
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116 ACE_ADC0_CalStart_IRQn = 82, /*!< ACE ADC0 calibration start interrupt */
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117 ACE_ADC1_CalStart_IRQn = 83, /*!< ACE ADC1 calibration start interrupt */
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118 ACE_ADC2_CalStart_IRQn = 84, /*!< ACE ADC2 calibration start interrupt */
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119 ACE_Comp0_Fall_IRQn = 85, /*!< ACE comparator 0 falling under reference interrupt */
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120 ACE_Comp1_Fall_IRQn = 86, /*!< ACE comparator 1 falling under reference interrupt */
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121 ACE_Comp2_Fall_IRQn = 87, /*!< ACE comparator 2 falling under reference interrupt */
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122 ACE_Comp3_Fall_IRQn = 88, /*!< ACE comparator 3 falling under reference interrupt */
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123 ACE_Comp4_Fall_IRQn = 89, /*!< ACE comparator 4 falling under reference interrupt */
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124 ACE_Comp5_Fall_IRQn = 90, /*!< ACE comparator 5 falling under reference interrupt */
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125 ACE_Comp6_Fall_IRQn = 91, /*!< ACE comparator 6 falling under reference interrupt */
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126 ACE_Comp7_Fall_IRQn = 92, /*!< ACE comparator 7 falling under reference interrupt */
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127 ACE_Comp8_Fall_IRQn = 93, /*!< ACE comparator 8 falling under reference interrupt */
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128 ACE_Comp9_Fall_IRQn = 94, /*!< ACE comparator 9 falling under reference interrupt */
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129 ACE_Comp10_Fall_IRQn = 95, /*!< ACE comparator 10 falling under reference interrupt */
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130 ACE_Comp11_Fall_IRQn = 96, /*!< ACE comparator 11 falling under reference interrupt */
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131 ACE_Comp0_Rise_IRQn = 97, /*!< ACE comparator 0 rising over reference interrupt */
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132 ACE_Comp1_Rise_IRQn = 98, /*!< ACE comparator 1 rising over reference interrupt */
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133 ACE_Comp2_Rise_IRQn = 99, /*!< ACE comparator 2 rising over reference interrupt */
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134 ACE_Comp3_Rise_IRQn = 100, /*!< ACE comparator 3 rising over reference interrupt */
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135 ACE_Comp4_Rise_IRQn = 101, /*!< ACE comparator 4 rising over reference interrupt */
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136 ACE_Comp5_Rise_IRQn = 102, /*!< ACE comparator 5 rising over reference interrupt */
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137 ACE_Comp6_Rise_IRQn = 103, /*!< ACE comparator 6 rising over reference interrupt */
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138 ACE_Comp7_Rise_IRQn = 104, /*!< ACE comparator 7 rising over reference interrupt */
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139 ACE_Comp8_Rise_IRQn = 105, /*!< ACE comparator 8 rising over reference interrupt */
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140 ACE_Comp9_Rise_IRQn = 106, /*!< ACE comparator 9 rising over reference interrupt */
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141 ACE_Comp10_Rise_IRQn = 107, /*!< ACE comparator 10 rising over reference interrupt */
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142 ACE_Comp11_Rise_IRQn = 108, /*!< ACE comparator 11 rising over reference interrupt */
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143 ACE_ADC0_FifoFull_IRQn = 109, /*!< ACE ADC0 FIFO full interrupt */
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144 ACE_ADC0_FifoAFull_IRQn = 110, /*!< ACE ADC0 FIFO almost full interrupt */
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145 ACE_ADC0_FifoEmpty_IRQn = 111, /*!< ACE ADC0 FIFO empty interrupt */
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146 ACE_ADC1_FifoFull_IRQn = 112, /*!< ACE ADC1 FIFO full interrupt */
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147 ACE_ADC1_FifoAFull_IRQn = 113, /*!< ACE ADC1 FIFO almost full interrupt */
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148 ACE_ADC1_FifoEmpty_IRQn = 114, /*!< ACE ADC1 FIFO empty interrupt */
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149 ACE_ADC2_FifoFull_IRQn = 115, /*!< ACE ADC2 FIFO full interrupt */
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150 ACE_ADC2_FifoAFull_IRQn = 116, /*!< ACE ADC2 FIFO almost full interrupt */
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151 ACE_ADC2_FifoEmpty_IRQn = 117, /*!< ACE ADC2 FIFO empty interrupt */
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152 ACE_PPE_Flag0_IRQn = 118, /*!< ACE post processing engine flag 0 interrupt */
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153 ACE_PPE_Flag1_IRQn = 119, /*!< ACE post processing engine flag 1 interrupt */
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154 ACE_PPE_Flag2_IRQn = 120, /*!< ACE post processing engine flag 2 interrupt */
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155 ACE_PPE_Flag3_IRQn = 121, /*!< ACE post processing engine flag 3 interrupt */
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156 ACE_PPE_Flag4_IRQn = 122, /*!< ACE post processing engine flag 4 interrupt */
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157 ACE_PPE_Flag5_IRQn = 123, /*!< ACE post processing engine flag 5 interrupt */
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158 ACE_PPE_Flag6_IRQn = 124, /*!< ACE post processing engine flag 6 interrupt */
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159 ACE_PPE_Flag7_IRQn = 125, /*!< ACE post processing engine flag 7 interrupt */
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160 ACE_PPE_Flag8_IRQn = 126, /*!< ACE post processing engine flag 8 interrupt */
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161 ACE_PPE_Flag9_IRQn = 127, /*!< ACE post processing engine flag 9 interrupt */
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162 ACE_PPE_Flag10_IRQn = 128, /*!< ACE post processing engine flag 10 interrupt */
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163 ACE_PPE_Flag11_IRQn = 129, /*!< ACE post processing engine flag 11 interrupt */
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164 ACE_PPE_Flag12_IRQn = 130, /*!< ACE post processing engine flag 12 interrupt */
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165 ACE_PPE_Flag13_IRQn = 131, /*!< ACE post processing engine flag 13 interrupt */
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166 ACE_PPE_Flag14_IRQn = 132, /*!< ACE post processing engine flag 14 interrupt */
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167 ACE_PPE_Flag15_IRQn = 133, /*!< ACE post processing engine flag 15 interrupt */
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168 ACE_PPE_Flag16_IRQn = 134, /*!< ACE post processing engine flag 16 interrupt */
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169 ACE_PPE_Flag17_IRQn = 135, /*!< ACE post processing engine flag 17 interrupt */
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170 ACE_PPE_Flag18_IRQn = 136, /*!< ACE post processing engine flag 18 interrupt */
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171 ACE_PPE_Flag19_IRQn = 137, /*!< ACE post processing engine flag 19 interrupt */
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172 ACE_PPE_Flag20_IRQn = 138, /*!< ACE post processing engine flag 20 interrupt */
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173 ACE_PPE_Flag21_IRQn = 139, /*!< ACE post processing engine flag 21 interrupt */
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174 ACE_PPE_Flag22_IRQn = 140, /*!< ACE post processing engine flag 22 interrupt */
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175 ACE_PPE_Flag23_IRQn = 141, /*!< ACE post processing engine flag 23 interrupt */
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176 ACE_PPE_Flag24_IRQn = 142, /*!< ACE post processing engine flag 24 interrupt */
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177 ACE_PPE_Flag25_IRQn = 143, /*!< ACE post processing engine flag 25 interrupt */
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178 ACE_PPE_Flag26_IRQn = 144, /*!< ACE post processing engine flag 26 interrupt */
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179 ACE_PPE_Flag27_IRQn = 145, /*!< ACE post processing engine flag 27 interrupt */
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180 ACE_PPE_Flag28_IRQn = 146, /*!< ACE post processing engine flag 28 interrupt */
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181 ACE_PPE_Flag29_IRQn = 147, /*!< ACE post processing engine flag 29 interrupt */
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182 ACE_PPE_Flag30_IRQn = 148, /*!< ACE post processing engine flag 30 interrupt */
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183 ACE_PPE_Flag31_IRQn = 149 /*!< ACE post processing engine flag 31 interrupt */
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188 * ==========================================================================
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189 * ----------- Processor and Core Peripheral Section ------------------------
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190 * ==========================================================================
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193 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
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194 #define __MPU_PRESENT 1 /*!< SmartFusion includes a MPU */
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195 #define __NVIC_PRIO_BITS 5 /*!< SmartFusion uses 5 Bits for the Priority Levels */
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196 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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199 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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200 #include "system_a2fxxxm3.h" /* SmartFusion System */
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202 /******************************************************************************/
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203 /* Device Specific Peripheral registers structures */
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204 /******************************************************************************/
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205 #if defined ( __CC_ARM )
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206 /* Enable anonymous unions when building using Keil-MDK */
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207 #pragma anon_unions
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209 /*----------------------------------------------------------------------------*/
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210 /*----------------------------------- UART -----------------------------------*/
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211 /*----------------------------------------------------------------------------*/
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219 uint32_t RESERVED0;
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226 uint32_t RESERVED1;
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233 uint32_t RESERVED2;
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238 uint16_t RESERVED4;
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241 uint16_t RESERVED6;
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244 uint16_t RESERVED8;
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247 uint16_t RESERVED10;
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249 uint8_t RESERVED11;
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250 uint16_t RESERVED12;
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253 /*------------------------------------------------------------------------------
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258 uint32_t RESERVED0[32];
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260 __IO uint32_t IER_ERBFI;
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261 __IO uint32_t IER_ETBEI;
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262 __IO uint32_t IER_ELSI;
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263 __IO uint32_t IER_EDSSI;
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265 uint32_t RESERVED1[28];
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267 __IO uint32_t FCR_ENABLE;
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268 __IO uint32_t FCR_CLEAR_RX_FIFO;
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269 __IO uint32_t FCR_CLEAR_TX_FIFO;
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270 __IO uint32_t FCR_RXRDY_TXRDYN_EN;
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271 __IO uint32_t FCR_RESERVED0;
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272 __IO uint32_t FCR_RESERVED1;
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273 __IO uint32_t FCR_RX_TRIG0;
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274 __IO uint32_t FCR_RX_TRIG1;
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276 uint32_t RESERVED2[24];
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278 __IO uint32_t LCR_WLS0;
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279 __IO uint32_t LCR_WLS1;
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280 __IO uint32_t LCR_STB;
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281 __IO uint32_t LCR_PEN;
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282 __IO uint32_t LCR_EPS;
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283 __IO uint32_t LCR_SP;
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284 __IO uint32_t LCR_SB;
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285 __IO uint32_t LCR_DLAB;
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287 uint32_t RESERVED3[24];
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289 __IO uint32_t MCR_DTR;
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290 __IO uint32_t MCR_RTS;
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291 __IO uint32_t MCR_OUT1;
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292 __IO uint32_t MCR_OUT2;
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293 __IO uint32_t MCR_LOOP;
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295 uint32_t RESERVED4[27];
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297 __I uint32_t LSR_DR;
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298 __I uint32_t LSR_OE;
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299 __I uint32_t LSR_PE;
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300 __I uint32_t LSR_FE;
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301 __I uint32_t LSR_BI;
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302 __I uint32_t LSR_THRE;
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303 __I uint32_t LSR_TEMT;
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304 __I uint32_t LSR_FIER;
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306 uint32_t RESERVED5[24];
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308 __I uint32_t MSR_DCTS;
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309 __I uint32_t MSR_DDSR;
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310 __I uint32_t MSR_TERI;
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311 __I uint32_t MSR_DDCD;
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312 __I uint32_t MSR_CTS;
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313 __I uint32_t MSR_DSR;
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314 __I uint32_t MSR_RI;
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315 __I uint32_t MSR_DCD;
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317 } UART_BitBand_TypeDef;
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319 /*----------------------------------------------------------------------------*/
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320 /*----------------------------------- I2C ------------------------------------*/
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321 /*----------------------------------------------------------------------------*/
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326 uint16_t RESERVED1;
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329 uint16_t RESERVED3;
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332 uint16_t RESERVED5;
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335 uint16_t RESERVED7;
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336 __IO uint8_t SMBUS;
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338 uint16_t RESERVED9;
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340 uint8_t RESERVED10;
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341 uint16_t RESERVED11;
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342 __IO uint8_t GLITCHREG;
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343 uint8_t RESERVED12;
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344 uint16_t RESERVED13;
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347 /*------------------------------------------------------------------------------
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358 uint32_t CTRL_ENS1;
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360 uint32_t RESERVED0[56];
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362 uint32_t RESERVED1[31];
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364 } I2C_BitBand_TypeDef;
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366 /*----------------------------------------------------------------------------*/
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367 /*----------------------------------- SPI ------------------------------------*/
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368 /*----------------------------------------------------------------------------*/
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371 __IO uint32_t CONTROL;
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372 __IO uint32_t TXRXDF_SIZE;
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373 __I uint32_t STATUS;
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374 __O uint32_t INT_CLEAR;
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375 __I uint32_t RX_DATA;
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376 __O uint32_t TX_DATA;
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377 __IO uint32_t CLK_GEN;
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378 __IO uint32_t SLAVE_SELECT;
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385 __IO uint32_t CTRL_ENABLE;
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386 __IO uint32_t CTRL_MASTER;
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387 __IO uint32_t CTRL_MODE[2];
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388 __IO uint32_t CTRL_RX_INT_EN;
\r
389 __IO uint32_t CTRL_TX_INT_EN;
\r
390 __IO uint32_t CTRL_RX_OVERFLOW_INT_EN;
\r
391 __IO uint32_t CTRL_TX_UNDERRUN_INT_EN;
\r
392 __IO uint32_t CTRL_TXRXDFCOUNT[16];
\r
393 __IO uint32_t CTRL_SPO;
\r
394 __IO uint32_t CTRL_SPH;
\r
395 __IO uint32_t CTRL_RESERVED[6];
\r
397 __IO uint32_t TXRXDF_SIZE[32];
\r
399 __I uint32_t STATUS_TX_DONE;
\r
400 __I uint32_t STATUS_RX_RDY;
\r
401 __I uint32_t STATUS_RX_CH_OV;
\r
402 __I uint32_t STATUS_TX_CH_UV;
\r
403 __I uint32_t STATUS_RX_FIFO_FULL;
\r
404 __I uint32_t STATUS_RX_FIFO_FULL_NEXT;
\r
405 __I uint32_t STATUS_RX_FIFO_EMPTY;
\r
406 __I uint32_t STATUS_RX_FIFO_EMPTY_NEXT;
\r
407 __I uint32_t STATUS_TX_FIFO_FULL;
\r
408 __I uint32_t STATUS_TX_FIFO_FULL_NEXT;
\r
409 __I uint32_t STATUS_TX_FIFO_EMPTY;
\r
410 __I uint32_t STATUS_TX_FIFO_EMPTY_NEXT;
\r
411 __I uint32_t STATUS_RESERVED[20];
\r
413 __O uint32_t INT_CLEAR_TX_DONE;
\r
414 __O uint32_t INT_CLEAR_RX_RDY;
\r
415 __O uint32_t INT_CLEAR_RX_OVER;
\r
416 __O uint32_t INT_CLEAR_TX_UNDER;
\r
417 __O uint32_t INT_CLEAR[28];
\r
419 __I uint32_t RX_DATA[32];
\r
420 __O uint32_t TX_DATA[32];
\r
421 __IO uint32_t CLK_GEN[32];
\r
422 __IO uint32_t SLAVE_SELECT[32];
\r
423 __I uint32_t MIS_TX_DONE;
\r
424 __I uint32_t MIS_RX_RDY;
\r
425 __I uint32_t MIS_RX_OVER;
\r
426 __I uint32_t MIS_TX_UNDER;
\r
427 __I uint32_t MIS[28];
\r
428 __I uint32_t RIS[32];
\r
429 } SPI_BitBand_TypeDef;
\r
431 /*----------------------------------------------------------------------------*/
\r
432 /*----------------------------------- GPIO -----------------------------------*/
\r
433 /*----------------------------------------------------------------------------*/
\r
436 __IO uint32_t GPIO_0_CFG;
\r
437 __IO uint32_t GPIO_1_CFG;
\r
438 __IO uint32_t GPIO_2_CFG;
\r
439 __IO uint32_t GPIO_3_CFG;
\r
440 __IO uint32_t GPIO_4_CFG;
\r
441 __IO uint32_t GPIO_5_CFG;
\r
442 __IO uint32_t GPIO_6_CFG;
\r
443 __IO uint32_t GPIO_7_CFG;
\r
444 __IO uint32_t GPIO_8_CFG;
\r
445 __IO uint32_t GPIO_9_CFG;
\r
446 __IO uint32_t GPIO_10_CFG;
\r
447 __IO uint32_t GPIO_11_CFG;
\r
448 __IO uint32_t GPIO_12_CFG;
\r
449 __IO uint32_t GPIO_13_CFG;
\r
450 __IO uint32_t GPIO_14_CFG;
\r
451 __IO uint32_t GPIO_15_CFG;
\r
452 __IO uint32_t GPIO_16_CFG;
\r
453 __IO uint32_t GPIO_17_CFG;
\r
454 __IO uint32_t GPIO_18_CFG;
\r
455 __IO uint32_t GPIO_19_CFG;
\r
456 __IO uint32_t GPIO_20_CFG;
\r
457 __IO uint32_t GPIO_21_CFG;
\r
458 __IO uint32_t GPIO_22_CFG;
\r
459 __IO uint32_t GPIO_23_CFG;
\r
460 __IO uint32_t GPIO_24_CFG;
\r
461 __IO uint32_t GPIO_25_CFG;
\r
462 __IO uint32_t GPIO_26_CFG;
\r
463 __IO uint32_t GPIO_27_CFG;
\r
464 __IO uint32_t GPIO_28_CFG;
\r
465 __IO uint32_t GPIO_29_CFG;
\r
466 __IO uint32_t GPIO_30_CFG;
\r
467 __IO uint32_t GPIO_31_CFG;
\r
468 __IO uint32_t GPIO_IRQ;
\r
469 __I uint32_t GPIO_IN;
\r
470 __IO uint32_t GPIO_OUT;
\r
475 __IO uint32_t GPIO_0_CFG[32];
\r
476 __IO uint32_t GPIO_1_CFG[32];
\r
477 __IO uint32_t GPIO_2_CFG[32];
\r
478 __IO uint32_t GPIO_3_CFG[32];
\r
479 __IO uint32_t GPIO_4_CFG[32];
\r
480 __IO uint32_t GPIO_5_CFG[32];
\r
481 __IO uint32_t GPIO_6_CFG[32];
\r
482 __IO uint32_t GPIO_7_CFG[32];
\r
483 __IO uint32_t GPIO_8_CFG[32];
\r
484 __IO uint32_t GPIO_9_CFG[32];
\r
485 __IO uint32_t GPIO_10_CFG[32];
\r
486 __IO uint32_t GPIO_11_CFG[32];
\r
487 __IO uint32_t GPIO_12_CFG[32];
\r
488 __IO uint32_t GPIO_13_CFG[32];
\r
489 __IO uint32_t GPIO_14_CFG[32];
\r
490 __IO uint32_t GPIO_15_CFG[32];
\r
491 __IO uint32_t GPIO_16_CFG[32];
\r
492 __IO uint32_t GPIO_17_CFG[32];
\r
493 __IO uint32_t GPIO_18_CFG[32];
\r
494 __IO uint32_t GPIO_19_CFG[32];
\r
495 __IO uint32_t GPIO_20_CFG[32];
\r
496 __IO uint32_t GPIO_21_CFG[32];
\r
497 __IO uint32_t GPIO_22_CFG[32];
\r
498 __IO uint32_t GPIO_23_CFG[32];
\r
499 __IO uint32_t GPIO_24_CFG[32];
\r
500 __IO uint32_t GPIO_25_CFG[32];
\r
501 __IO uint32_t GPIO_26_CFG[32];
\r
502 __IO uint32_t GPIO_27_CFG[32];
\r
503 __IO uint32_t GPIO_28_CFG[32];
\r
504 __IO uint32_t GPIO_29_CFG[32];
\r
505 __IO uint32_t GPIO_30_CFG[32];
\r
506 __IO uint32_t GPIO_31_CFG[32];
\r
507 __IO uint32_t GPIO_IRQ[32];
\r
508 __I uint32_t GPIO_IN[32];
\r
509 __IO uint32_t GPIO_OUT[32];
\r
510 } GPIO_BitBand_TypeDef;
\r
513 /*----------------------------------------------------------------------------*/
\r
514 /*----------------------------------- RTC ------------------------------------*/
\r
515 /*----------------------------------------------------------------------------*/
\r
518 __IO uint32_t COUNTER0_REG;
\r
519 __IO uint32_t COUNTER1_REG;
\r
520 __IO uint32_t COUNTER2_REG;
\r
521 __IO uint32_t COUNTER3_REG;
\r
522 __IO uint32_t COUNTER4_REG;
\r
524 __IO uint32_t RESERVED0[3];
\r
526 __IO uint32_t MATCHREG0_REG;
\r
527 __IO uint32_t MATCHREG1_REG;
\r
528 __IO uint32_t MATCHREG2_REG;
\r
529 __IO uint32_t MATCHREG3_REG;
\r
530 __IO uint32_t MATCHREG4_REG;
\r
532 __IO uint32_t RESERVED1[3];
\r
534 __IO uint32_t MATCHBITS0_REG;
\r
535 __IO uint32_t MATCHBITS1_REG;
\r
536 __IO uint32_t MATCHBITS2_REG;
\r
537 __IO uint32_t MATCHBITS3_REG;
\r
538 __IO uint32_t MATCHBITS4_REG;
\r
540 __IO uint32_t RESERVED2[3];
\r
542 __IO uint32_t CTRL_STAT_REG;
\r
545 /*----------------------------------------------------------------------------*/
\r
546 /*---------------------------------- Timer -----------------------------------*/
\r
547 /*----------------------------------------------------------------------------*/
\r
550 __I uint32_t TIM1_VAL;
\r
551 __IO uint32_t TIM1_LOADVAL;
\r
552 __IO uint32_t TIM1_BGLOADVAL;
\r
553 __IO uint32_t TIM1_CTRL;
\r
554 __IO uint32_t TIM1_RIS;
\r
555 __I uint32_t TIM1_MIS;
\r
557 __I uint32_t TIM2_VAL;
\r
558 __IO uint32_t TIM2_LOADVAL;
\r
559 __IO uint32_t TIM2_BGLOADVAL;
\r
560 __IO uint32_t TIM2_CTRL;
\r
561 __IO uint32_t TIM2_RIS;
\r
562 __I uint32_t TIM2_MIS;
\r
564 __I uint32_t TIM64_VAL_U;
\r
565 __I uint32_t TIM64_VAL_L;
\r
566 __IO uint32_t TIM64_LOADVAL_U;
\r
567 __IO uint32_t TIM64_LOADVAL_L;
\r
568 __IO uint32_t TIM64_BGLOADVAL_U;
\r
569 __IO uint32_t TIM64_BGLOADVAL_L;
\r
570 __IO uint32_t TIM64_CTRL;
\r
571 __IO uint32_t TIM64_RIS;
\r
572 __I uint32_t TIM64_MIS;
\r
573 __IO uint32_t TIM64_MODE;
\r
576 /*------------------------------------------------------------------------------
\r
581 __I uint32_t TIM1_VALUE_BIT[32];
\r
582 __IO uint32_t TIM1_LOADVAL[32];
\r
583 __IO uint32_t TIM1_BGLOADVAL[32];
\r
585 __IO uint32_t TIM1ENABLE;
\r
586 __IO uint32_t TIM1MODE;
\r
587 __IO uint32_t TIM1INTEN;
\r
588 __IO uint32_t TIM1_CTRL_RESERVED[29];
\r
589 __IO uint32_t TIM1_RIS[32];
\r
590 __I uint32_t TIM1_MIS[32];
\r
592 __I uint32_t TIM2_VALUE[32];
\r
593 __IO uint32_t TIM2_LOADVAL[32];
\r
594 __IO uint32_t TIM2_BGLOADVAL[32];
\r
596 __IO uint32_t TIM2ENABLE;
\r
597 __IO uint32_t TIM2MODE;
\r
598 __IO uint32_t TIM2INTEN;
\r
599 __IO uint32_t TIM2_CTRL[29];
\r
600 __IO uint32_t TIM2_RIS[32];
\r
601 __I uint32_t TIM2_MIS[32];
\r
603 __I uint32_t TIM64VALUEU[32];
\r
604 __I uint32_t TIM64VALUEL[32];
\r
605 __IO uint32_t TIM64LOADVALUEU[32];
\r
606 __IO uint32_t TIM64LOADVALUEL[32];
\r
607 __IO uint32_t TIM64BGLOADVALUEU[32];
\r
608 __IO uint32_t TIM64BGLOADVALUEL[32];
\r
609 __IO uint32_t TIM64ENABLE;
\r
610 __IO uint32_t TIM64MODE;
\r
611 __IO uint32_t TIM64INTEN;
\r
612 __IO uint32_t TIM64_CTRL[29];
\r
613 __IO uint32_t TIM64_RIS[32];
\r
614 __I uint32_t TIM64_MIS[32];
\r
615 __IO uint32_t TIM64_MODE[32];
\r
616 } TIMER_BitBand_TypeDef;
\r
618 /*----------------------------------------------------------------------------*/
\r
619 /*--------------------------------- Watchdog ---------------------------------*/
\r
620 /*----------------------------------------------------------------------------*/
\r
623 __I uint32_t WDOGVALUE;
\r
624 __IO uint32_t WDOGLOAD;
\r
625 __IO uint32_t WDOGMVRP;
\r
626 __O uint32_t WDOGREFRESH;
\r
627 __IO uint32_t WDOGENABLE;
\r
628 __IO uint32_t WDOGCONTROL;
\r
629 __I uint32_t WDOGSTATUS;
\r
630 __IO uint32_t WDOGRIS;
\r
631 __I uint32_t WDOGMIS;
\r
632 } WATCHDOG_TypeDef;
\r
634 /*----------------------------------------------------------------------------*/
\r
635 /*----------------------------- Real Time Clock ------------------------------*/
\r
636 /*----------------------------------------------------------------------------*/
\r
638 /*----------------------------------------------------------------------------*/
\r
639 /*----------------------------- Peripherals DMA ------------------------------*/
\r
640 /*----------------------------------------------------------------------------*/
\r
643 __IO uint32_t CRTL;
\r
644 __IO uint32_t STATUS;
\r
645 __IO uint32_t BUFFER_A_SRC_ADDR;
\r
646 __IO uint32_t BUFFER_A_DEST_ADDR;
\r
647 __IO uint32_t BUFFER_A_TRANSFER_COUNT;
\r
648 __IO uint32_t BUFFER_B_SRC_ADDR;
\r
649 __IO uint32_t BUFFER_B_DEST_ADDR;
\r
650 __IO uint32_t BUFFER_B_TRANSFER_COUNT;
\r
651 } PDMA_Channel_TypeDef;
\r
655 __IO uint32_t RATIO_HIGH_LOW;
\r
656 __IO uint32_t BUFFER_STATUS;
\r
657 uint32_t RESERVED[6];
\r
658 PDMA_Channel_TypeDef CHANNEL[8];
\r
661 /*----------------------------------------------------------------------------*/
\r
662 /*------------------------------ Ethernet MAC --------------------------------*/
\r
663 /*----------------------------------------------------------------------------*/
\r
666 __IO uint32_t CSR0;
\r
667 uint32_t RESERVED0;
\r
668 __IO uint32_t CSR1;
\r
669 uint32_t RESERVED1;
\r
670 __IO uint32_t CSR2;
\r
671 uint32_t RESERVED2;
\r
672 __IO uint32_t CSR3;
\r
673 uint32_t RESERVED3;
\r
674 __IO uint32_t CSR4;
\r
675 uint32_t RESERVED4;
\r
676 __IO uint32_t CSR5;
\r
677 uint32_t RESERVED5;
\r
678 __IO uint32_t CSR6;
\r
679 uint32_t RESERVED6;
\r
680 __IO uint32_t CSR7;
\r
681 uint32_t RESERVED7;
\r
682 __IO uint32_t CSR8;
\r
683 uint32_t RESERVED8;
\r
684 __IO uint32_t CSR9;
\r
685 uint32_t RESERVED9;
\r
686 uint32_t RESERVED10;
\r
687 uint32_t RESERVED11;
\r
688 __IO uint32_t CSR11;
\r
691 /*----------------------------------------------------------------------------*/
\r
692 /*---------------------- Analog Conversion Engine (ACE) ----------------------*/
\r
693 /*----------------------------------------------------------------------------*/
\r
694 /* Analog quad configuration */
\r
698 uint8_t reserved0_0;
\r
699 uint16_t reserved0_1;
\r
701 uint8_t reserved1_0;
\r
702 uint16_t reserved1_1;
\r
704 uint8_t reserved2_0;
\r
705 uint16_t reserved2_1;
\r
707 uint8_t reserved3_0;
\r
708 uint16_t reserved3_1;
\r
710 uint8_t reserved4_0;
\r
711 uint16_t reserved4_1;
\r
713 uint8_t reserved5_0;
\r
714 uint16_t reserved5_1;
\r
716 uint8_t reserved6_0;
\r
717 uint16_t reserved6_1;
\r
719 uint8_t reserved7_0;
\r
720 uint16_t reserved7_1;
\r
722 uint8_t reserved8_0;
\r
723 uint16_t reserved8_1;
\r
725 uint8_t reserved9_0;
\r
726 uint16_t reserved9_1;
\r
728 uint8_t reserved10_0;
\r
729 uint16_t reserved10_1;
\r
731 uint8_t reserved11_0;
\r
732 uint16_t reserved11_1;
\r
735 /* ACE memory map layout */
\r
739 __IO uint32_t SSE_TS_CTRL;
\r
740 __IO uint32_t ADC_SYNC_CONV;
\r
741 __IO uint32_t ANA_COMM_CTRL;
\r
742 __IO uint32_t DAC_SYNC_CTRL;
\r
743 __IO uint32_t PDMA_REQUEST;
\r
744 uint32_t RESERVED0[10];
\r
745 __O uint32_t PC0_LO;
\r
746 __O uint32_t PC0_HI;
\r
747 __IO uint32_t PC0_CTRL;
\r
748 __IO uint32_t PC0_DLY;
\r
749 __IO uint32_t ADC0_CONV_CTRL;
\r
750 __IO uint32_t ADC0_STC;
\r
751 __IO uint32_t ADC0_TVC;
\r
752 __IO uint32_t ADC0_MISC_CTRL;
\r
753 __IO uint32_t DAC0_CTRL;
\r
754 __IO uint32_t DAC0_BYTE0;
\r
755 __IO uint32_t DAC0_BYTE1;
\r
756 __IO uint32_t DAC0_BYTE2;
\r
758 __O uint32_t LC0_JMP_LO;
\r
759 __O uint32_t LC0_JMP_HI;
\r
760 __O uint32_t PC0_FLAGS;
\r
761 __O uint32_t PC1_LO;
\r
762 __O uint32_t PC1_HI;
\r
763 __IO uint32_t PC1_CTRL;
\r
764 __IO uint32_t PC1_DLY;
\r
765 __IO uint32_t ADC1_CONV_CTRL;
\r
766 __IO uint32_t ADC1_STC;
\r
767 __IO uint32_t ADC1_TVC;
\r
768 __IO uint32_t ADC1_MISC_CTRL;
\r
769 __IO uint32_t DAC1_CTRL;
\r
770 __IO uint32_t DAC1_BYTE0;
\r
771 __IO uint32_t DAC1_BYTE1;
\r
772 __IO uint32_t DAC1_BYTE2;
\r
774 __O uint32_t LC1_JMP_LO;
\r
775 __O uint32_t LC1_JMP_HI;
\r
776 __O uint32_t PC1_FLAGS;
\r
777 __O uint32_t PC2_LO;
\r
778 __O uint32_t PC2_HI;
\r
779 __IO uint32_t PC2_CTRL;
\r
780 __IO uint32_t PC2_DLY;
\r
781 __IO uint32_t ADC2_CONV_CTRL;
\r
782 __IO uint32_t ADC2_STC;
\r
783 __IO uint32_t ADC2_TVC;
\r
784 __IO uint32_t ADC2_MISC_CTRL;
\r
785 __IO uint32_t DAC2_CTRL;
\r
786 __IO uint32_t DAC2_BYTE0;
\r
787 __IO uint32_t DAC2_BYTE1;
\r
788 __IO uint32_t DAC2_BYTE2;
\r
790 __O uint32_t LC2_JMP_LO;
\r
791 __O uint32_t LC2_JMP_HI;
\r
792 __O uint32_t PC2_FLAGS;
\r
793 uint32_t RESERVED1;
\r
794 uint32_t RESERVED2;
\r
795 __IO uint32_t SSE_RAM_LO_IDATA;
\r
796 __IO uint32_t SSE_RAM_HI_IDATA;
\r
797 uint32_t RESERVED3[61];
\r
798 AQ_config_t ACB_DATA[6];
\r
799 uint32_t RESERVED4[59];
\r
800 __IO uint32_t SSE_PC0;
\r
801 __IO uint32_t SSE_PC1;
\r
802 __IO uint32_t SSE_PC2;
\r
803 uint32_t RESERVED5[57];
\r
804 __IO uint32_t SSE_DAC0_BYTES01;
\r
805 __IO uint32_t SSE_DAC1_BYTES01;
\r
806 __IO uint32_t SSE_DAC2_BYTES01;
\r
807 uint32_t RESERVED6[61];
\r
808 __O uint32_t SSE_ADC0_RESULTS;
\r
809 __O uint32_t SSE_ADC1_RESULTS;
\r
810 __O uint32_t SSE_ADC2_RESULTS;
\r
811 uint32_t RESERVED7[61];
\r
812 __O uint32_t SSE_PDMA_DATAIN;
\r
813 uint32_t RESERVED8[63];
\r
814 __IO uint32_t SSE_RAM_DATA[512];
\r
815 __I uint32_t ADC0_STATUS;
\r
816 __I uint32_t ADC1_STATUS;
\r
817 __I uint32_t ADC2_STATUS;
\r
818 __I uint32_t COMPARATOR_STATUS;
\r
819 uint32_t RESERVED9[124];
\r
820 __IO uint32_t SSE_IRQ_EN;
\r
821 __I uint32_t SSE_IRQ;
\r
822 __O uint32_t SSE_IRQ_CLR;
\r
823 __IO uint32_t COMP_IRQ_EN;
\r
824 __I uint32_t COMP_IRQ;
\r
825 __O uint32_t COMP_IRQ_CLR;
\r
826 __IO uint32_t PPE_FIFO_IRQ_EN;
\r
827 __I uint32_t PPE_FIFO_IRQ;
\r
828 __O uint32_t PPE_FIFO_IRQ_CLR;
\r
829 __IO uint32_t PPE_FLAGS0_IRQ_EN;
\r
830 __I uint32_t PPE_FLAGS0_IRQ;
\r
831 __O uint32_t PPE_FLAGS0_IRQ_CLR;
\r
832 __IO uint32_t PPE_FLAGS1_IRQ_EN;
\r
833 __I uint32_t PPE_FLAGS1_IRQ;
\r
834 __O uint32_t PPE_FLAGS1_IRQ_CLR;
\r
835 __IO uint32_t PPE_FLAGS2_IRQ_EN;
\r
836 __I uint32_t PPE_FLAGS2_IRQ;
\r
837 __O uint32_t PPE_FLAGS2_IRQ_CLR;
\r
838 __IO uint32_t PPE_FLAGS3_IRQ_EN;
\r
839 __I uint32_t PPE_FLAGS3_IRQ;
\r
840 __O uint32_t PPE_FLAGS3_IRQ_CLR;
\r
841 __IO uint32_t PPE_SFFLAGS_IRQ_EN;
\r
842 __I uint32_t PPE_SFFLAGS_IRQ;
\r
843 __O uint32_t PPE_SFFLAGS_IRQ_CLR;
\r
844 __IO uint32_t FPGA_FLAGS_SEL;
\r
845 uint32_t RESERVED10[39];
\r
846 __IO uint32_t PPE_PDMA_CTRL;
\r
847 __I uint32_t PDMA_STATUS;
\r
848 __IO uint32_t PPE_PDMA_DATAOUT;
\r
849 uint32_t RESERVED11[61];
\r
850 __I uint32_t PPE_NOP;
\r
851 __IO uint32_t PPE_CTRL;
\r
852 __IO uint32_t PPE_PC_ETC;
\r
853 __IO uint32_t PPE_SF;
\r
854 __IO uint32_t PPE_SCRATCH;
\r
855 uint32_t RESERVED12;
\r
856 __IO uint32_t ALU_CTRL;
\r
857 __I uint32_t ALU_STATUS;
\r
858 __IO uint32_t ALU_A;
\r
859 uint32_t RESERVED50;
\r
860 __IO uint32_t ALU_B;
\r
861 uint32_t RESERVED53;
\r
862 __IO uint32_t ALU_C;
\r
863 uint32_t RESERVED51;
\r
864 __IO uint32_t ALU_D;
\r
865 uint32_t RESERVED52;
\r
866 __IO uint32_t ALU_E;
\r
867 uint32_t RESERVED54;
\r
868 __IO uint32_t PPE_FPTR;
\r
869 uint32_t RESERVED55;
\r
870 __IO uint32_t PPE_FLAGS0;
\r
871 __IO uint32_t PPE_FLAGS1;
\r
872 __IO uint32_t PPE_FLAGS2;
\r
873 __IO uint32_t PPE_FLAGS3;
\r
874 __IO uint32_t PPE_SFFLAGS;
\r
875 uint32_t RESERVED13[11];
\r
876 __IO uint32_t ADC0_FIFO_CTRL;
\r
877 __I uint32_t ADC0_FIFO_STATUS;
\r
878 __IO uint32_t ADC0_FIFO_DATA;
\r
879 __IO uint32_t ADC1_FIFO_CTRL;
\r
880 __I uint32_t ADC1_FIFO_STATUS;
\r
881 __IO uint32_t ADC1_FIFO_DATA;
\r
882 __IO uint32_t ADC2_FIFO_CTRL;
\r
883 __I uint32_t ADC2_FIFO_STATUS;
\r
884 __IO uint32_t ADC2_FIFO_DATA;
\r
885 uint32_t RESERVED14[19];
\r
886 __I uint32_t ADC0_FIFO_DATA_PEEK;
\r
887 __I uint32_t ADC0_FIFO_DATA0;
\r
888 __I uint32_t ADC0_FIFO_DATA1;
\r
889 __I uint32_t ADC0_FIFO_DATA2;
\r
890 __I uint32_t ADC0_FIFO_DATA3;
\r
891 __I uint32_t ADC1_FIFO_DATA_PEEK;
\r
892 __I uint32_t ADC1_FIFO_DATA0;
\r
893 __I uint32_t ADC1_FIFO_DATA1;
\r
894 __I uint32_t ADC1_FIFO_DATA2;
\r
895 __I uint32_t ADC1_FIFO_DATA3;
\r
896 __I uint32_t ADC2_FIFO_DATA_PEEK;
\r
897 __I uint32_t ADC2_FIFO_DATA0;
\r
898 __I uint32_t ADC2_FIFO_DATA1;
\r
899 __I uint32_t ADC2_FIFO_DATA2;
\r
900 __I uint32_t ADC2_FIFO_DATA3;
\r
901 uint32_t RESERVED15[177];
\r
902 __IO uint32_t PPE_RAM_DATA[512];
\r
905 /*----------------------------------------------------------------------------*/
\r
906 /*------------------------ In Application Programming ------------------------*/
\r
907 /*----------------------------------------------------------------------------*/
\r
910 __IO uint32_t IAP_IR;
\r
911 __IO uint32_t IAP_DR2;
\r
912 __IO uint32_t IAP_DR3;
\r
913 __IO uint32_t IAP_DR5;
\r
914 __IO uint32_t IAP_DR26;
\r
915 __IO uint32_t IAP_DR32;
\r
916 __IO uint32_t IAP_DR;
\r
917 __IO uint32_t IAP_DR_LENGTH;
\r
918 __IO uint32_t IAP_TAP_NEW_STATE;
\r
919 __IO uint32_t IAP_TAP_CONTROL;
\r
920 __I uint32_t IAP_STATUS;
\r
923 /*----------------------------------------------------------------------------*/
\r
924 /*---------------------- eNVM Special Function Registers ---------------------*/
\r
925 /*----------------------------------------------------------------------------*/
\r
928 __IO uint32_t STATUS;
\r
929 __IO uint32_t CONTROL;
\r
930 __IO uint32_t ENABLE;
\r
931 uint32_t RESERVED0;
\r
932 __IO uint32_t CONFIG_0;
\r
933 __IO uint32_t CONFIG_1;
\r
934 __IO uint32_t PAGE_STATUS_0;
\r
935 __IO uint32_t PAGE_STATUS_1;
\r
936 __IO uint32_t SEGMENT;
\r
937 __IO uint32_t ENVM_SELECT;
\r
940 /*----------------------------------------------------------------------------*/
\r
941 /*---------------------- eNVM Special Function Registers ---------------------*/
\r
942 /*----------------------------------------------------------------------------*/
\r
945 __IO uint32_t MSSIRQ_EN0;
\r
946 __IO uint32_t MSSIRQ_EN1;
\r
947 __IO uint32_t MSSIRQ_EN2;
\r
948 __IO uint32_t MSSIRQ_EN3;
\r
949 __IO uint32_t MSSIRQ_EN4;
\r
950 __IO uint32_t MSSIRQ_EN5;
\r
951 __IO uint32_t MSSIRQ_EN6;
\r
952 __IO uint32_t MSSIRQ_EN7;
\r
953 __I uint32_t MSSIRQ_SRC0;
\r
954 __I uint32_t MSSIRQ_SRC1;
\r
955 __I uint32_t MSSIRQ_SRC2;
\r
956 __I uint32_t MSSIRQ_SRC3;
\r
957 __I uint32_t MSSIRQ_SRC4;
\r
958 __I uint32_t MSSIRQ_SRC5;
\r
959 __I uint32_t MSSIRQ_SRC6;
\r
960 __I uint32_t MSSIRQ_SRC7;
\r
961 __IO uint32_t FIIC_MR;
\r
962 } MSS_IRQ_CTRL_TypeDef;
\r
964 /*----------------------------------------------------------------------------*/
\r
965 /*------------------------------ System Registers ----------------------------*/
\r
966 /*----------------------------------------------------------------------------*/
\r
969 __IO uint32_t ESRAM_CR;
\r
970 __IO uint32_t ENVM_CR;
\r
971 __IO uint32_t ENVM_REMAP_SYS_CR;
\r
972 __IO uint32_t ENVM_REMAP_FAB_CR;
\r
973 __IO uint32_t FAB_PROT_SIZE_CR;
\r
974 __IO uint32_t FAB_PROT_BASE_CR;
\r
975 __IO uint32_t AHB_MATRIX_CR;
\r
976 __IO uint32_t MSS_SR;
\r
977 __IO uint32_t CLR_MSS_SR;
\r
978 __IO uint32_t EFROM_CR;
\r
979 __IO uint32_t IAP_CR;
\r
980 __IO uint32_t SOFT_IRQ_CR;
\r
981 __IO uint32_t SOFT_RST_CR;
\r
982 __IO uint32_t DEVICE_SR;
\r
983 __IO uint32_t SYSTICK_CR;
\r
984 __IO uint32_t EMC_MUX_CR;
\r
985 __IO uint32_t EMC_CS_0_CR;
\r
986 __IO uint32_t EMC_CS_1_CR;
\r
987 __IO uint32_t MSS_CLK_CR;
\r
988 __IO uint32_t MSS_CCC_DIV_CR;
\r
989 __IO uint32_t MSS_CCC_MUX_CR;
\r
990 __IO uint32_t MSS_CCC_PLL_CR;
\r
991 __IO uint32_t MSS_CCC_DLY_CR;
\r
992 __IO uint32_t MSS_CCC_SR;
\r
993 __IO uint32_t MSS_RCOSC_CR;
\r
994 __IO uint32_t VRPSM_CR;
\r
995 __IO uint32_t RESERVED;
\r
996 __IO uint32_t FAB_IF_CR;
\r
997 __IO uint32_t FAB_APB_HIWORD_DR;
\r
998 __IO uint32_t LOOPBACK_CR;
\r
999 __IO uint32_t MSS_IO_BANK_CR;
\r
1000 __IO uint32_t GPIN_SOURCE_CR;
\r
1001 __IO uint32_t TEST_SR;
\r
1002 __IO uint32_t RED_REP_ADDR0;
\r
1003 __I uint32_t RED_REP_LOW_LOCS0;
\r
1004 __I uint32_t RED_REP_HIGH_LOCS0;
\r
1005 __IO uint32_t RED_REP_ADDR1;
\r
1006 __I uint32_t RED_REP_LOW_LOCS1;
\r
1007 __I uint32_t RED_REP_HIGH_LOCS1;
\r
1008 __IO uint32_t FABRIC_CR;
\r
1009 uint32_t RESERVED1[24];
\r
1010 __IO uint32_t IOMUX_CR[83];
\r
1013 #define SYSREG_ENVM_SOFTRESET_MASK (uint32_t)0x00000001
\r
1014 #define SYSREG_ESRAM0_SOFTRESET_MASK (uint32_t)0x00000002
\r
1015 #define SYSREG_ESRAM1_SOFTRESET_MASK (uint32_t)0x00000004
\r
1016 #define SYSREG_EMC_SOFTRESET_MASK (uint32_t)0x00000008
\r
1017 #define SYSREG_MAC_SOFTRESET_MASK (uint32_t)0x00000010
\r
1018 #define SYSREG_PDMA_SOFTRESET_MASK (uint32_t)0x00000020
\r
1019 #define SYSREG_TIMER_SOFTRESET_MASK (uint32_t)0x00000040
\r
1020 #define SYSREG_UART0_SOFTRESET_MASK (uint32_t)0x00000080
\r
1021 #define SYSREG_UART1_SOFTRESET_MASK (uint32_t)0x00000100
\r
1022 #define SYSREG_SPI0_SOFTRESET_MASK (uint32_t)0x00000200
\r
1023 #define SYSREG_SPI1_SOFTRESET_MASK (uint32_t)0x00000400
\r
1024 #define SYSREG_I2C0_SOFTRESET_MASK (uint32_t)0x00000800
\r
1025 #define SYSREG_I2C1_SOFTRESET_MASK (uint32_t)0x00001000
\r
1026 #define SYSREG_ACE_SOFTRESET_MASK (uint32_t)0x00002000
\r
1027 #define SYSREG_GPIO_SOFTRESET_MASK (uint32_t)0x00004000
\r
1028 #define SYSREG_IAP_SOFTRESET_MASK (uint32_t)0x00008000
\r
1029 #define SYSREG_EXT_SOFTRESET_MASK (uint32_t)0x00010000
\r
1030 #define SYSREG_FPGA_SOFTRESET_MASK (uint32_t)0x00020000
\r
1031 #define SYSREG_F2M_RESET_ENABLE_MASK (uint32_t)0x00040000
\r
1032 #define SYSREG_PADRESET_ENABLE_MASK (uint32_t)0x00080000
\r
1034 /******************************************************************************/
\r
1035 /* Peripheral memory map */
\r
1036 /******************************************************************************/
\r
1037 #define UART0_BASE 0x40000000U
\r
1038 #define SPI0_BASE 0x40001000U
\r
1039 #define I2C0_BASE 0x40002000U
\r
1040 #define MAC_BASE 0x40003000U
\r
1041 #define PDMA_BASE 0x40004000U
\r
1042 #define TIMER_BASE 0x40005000U
\r
1043 #define WATCHDOG_BASE 0x40006000U
\r
1044 #define H2F_IRQ_CTRL_BASE 0x40007000U
\r
1045 #define UART1_BASE 0x40010000U
\r
1046 #define SPI1_BASE 0x40011000U
\r
1047 #define I2C1_BASE 0x40012000U
\r
1048 #define GPIO_BASE 0x40013000U
\r
1049 #define RTC_BASE 0x40014100U
\r
1050 #define FROM_BASE 0x40015000U
\r
1051 #define IAP_BASE 0x40016000U
\r
1052 #define ACE_BASE 0x40020000U
\r
1053 #define FPGA_FABRIC_RAM_BASE 0x40040000U
\r
1054 #define FPGA_FABRIC_BASE 0x40050000U
\r
1055 #define ENVM_BASE 0x60000000U
\r
1056 #define ENVM_REGS_BASE 0x60100000U
\r
1057 #define SYSREG_BASE 0xE0042000U
\r
1059 /******************************************************************************/
\r
1060 /* bitband address calcualtion macro */
\r
1061 /******************************************************************************/
\r
1062 #define BITBAND_ADDRESS(X) ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5))
\r
1064 /******************************************************************************/
\r
1065 /* Peripheral declaration */
\r
1066 /******************************************************************************/
\r
1067 #define UART0 ((UART_TypeDef *) UART0_BASE)
\r
1068 #define UART0_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART0_BASE))
\r
1069 #define SPI0 ((SPI_TypeDef *) SPI0_BASE)
\r
1070 #define SPI0_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI0_BASE))
\r
1071 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
\r
1072 #define I2C0_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE))
\r
1073 #define MAC ((MAC_TypeDef *) MAC_BASE)
\r
1074 #define PDMA ((PDMA_TypeDef *) PDMA_BASE)
\r
1075 #define TIMER ((TIMER_TypeDef *) TIMER_BASE)
\r
1076 #define TIMER_BITBAND ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE))
\r
1077 #define WATCHDOG ((WATCHDOG_TypeDef *) WATCHDOG_BASE)
\r
1078 #define MSS_IRQ_CTRL ((MSS_IRQ_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE)
\r
1079 #define UART1 ((UART_TypeDef *) UART1_BASE)
\r
1080 #define UART1_BITBAND ((UART_BitBand_TypeDef *) BITBAND_ADDRESS(UART1_BASE))
\r
1081 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
\r
1082 #define SPI1_BITBAND ((SPI_BitBand_TypeDef *) BITBAND_ADDRESS(SPI1_BASE))
\r
1083 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
\r
1084 #define I2C1_BITBAND ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE))
\r
1085 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
\r
1086 #define GPIO_BITBAND ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE))
\r
1087 #define RTC ((RTC_TypeDef *) RTC_BASE)
\r
1088 #define FROM ((void *) FROM_BASE)
\r
1089 #define IAP ((IAP_TypeDef *) IAP_BASE)
\r
1090 #define ACE ((ACE_TypeDef *) ACE_BASE)
\r
1091 #define FPGA_FABRIC_RAM ((void *) FPGA_FABRIC_RAM_BASE)
\r
1092 #define FPGA_FABRIC ((void *) FPGA_FABRIC_BASE)
\r
1093 #define ENVM ((void *) ENVM_BASE)
\r
1094 #define ENVM_REGS ((NVM_TypeDef *) ENVM_REGS_BASE)
\r
1095 #define SYSREG ((SYSREG_TypeDef *) SYSREG_BASE)
\r
1097 #ifdef __cplusplus
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1101 #endif /* __A2FXXXM3_H__ */
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