git.sur5r.net Git - freertos/blob - Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/drivers/mss_ace/ace_sse.c

   1 /*******************************************************************************\r
   2  * (c) Copyright 2009 Actel Corporation.  All rights reserved.\r
   3  * \r
   4  * SVN $Revision: 2905 $\r
   5  * SVN $Date: 2010-08-20 14:03:28 +0100 (Fri, 20 Aug 2010) $\r
   6  */\r
   7 #include "mss_ace.h"\r
   8 #include "mss_ace_configurator.h"\r
   9 #include "../../drivers_config/mss_ace/ace_handles.h"\r
  10 #include "../../drivers_config/mss_ace/ace_config.h"\r
  11 \r
  12 #include "../../CMSIS/a2fxxxm3.h"\r
  13 #include "../../CMSIS/mss_assert.h"\r
  14 #include <string.h>\r
  15 \r
  16 #ifdef __cplusplus\r
  17 extern "C" {\r
  18 #endif \r
  19 \r
  20 #define SSE_START       1uL\r
  21 #define SSE_STOP        0uL\r
  22 \r
  23 #define NB_OF_ANALOG_BLOCKS     3u\r
  24 #define SEE_RAM_WORD_SIZE       512\r
  25 \r
  26 #define TS_ENABLE_MASK          0x01u\r
  27 #define PPE_ENABLE_MASK         0x01u\r
  28 #define ADC_RESET_MASK          0x10u\r
  29 #define ADC_FIFO_CLR_MASK       0x04u\r
  30 #define PDMA_DATAOUT_CLR_MASK   0x04u\r
  31 \r
  32 \r
  33 /*-------------------------------------------------------------------------*//**\r
  34  *\r
  35  */\r
  36 extern ace_procedure_desc_t g_sse_sequences_desc_table[ACE_NB_OF_SSE_PROCEDURES];\r
  37  \r
  38 /*-------------------------------------------------------------------------*//**\r
  39  *\r
  40  */\r
  41 sse_sequence_handle_t\r
  42 ACE_get_sse_seq_handle\r
  43 (\r
  44     const uint8_t * p_sz_sequence_name\r
  45 )\r
  46 {\r
  47     uint16_t seq_idx;\r
  48     sse_sequence_handle_t handle = INVALID_SSE_SEQ_HANDLE;\r
  49     \r
  50     for ( seq_idx = 0u;  seq_idx < (uint32_t)ACE_NB_OF_SSE_PROCEDURES; ++seq_idx )\r
  51     {\r
  52         if ( g_sse_sequences_desc_table[seq_idx].p_sz_proc_name != 0 )\r
  53         {\r
  54             int32_t diff;\r
  55             diff = strncmp( (const char *)p_sz_sequence_name, (const char *)g_sse_sequences_desc_table[seq_idx].p_sz_proc_name, MAX_PROCEDURE_NAME_LENGTH );\r
  56             if ( 0 == diff )\r
  57             {\r
  58                 /* channel name found. */\r
  59                 handle = seq_idx;\r
  60                 break;\r
  61             }\r
  62         }\r
  63     }\r
  64     return handle;\r
  65 }\r
  66 \r
  67 /*-------------------------------------------------------------------------*//**\r
  68  *\r
  69  */\r
  70 static uint32_t volatile * const sse_pc_ctrl_lut[NB_OF_ANALOG_BLOCKS] =\r
  71 {\r
  72     &ACE->PC0_CTRL,\r
  73     &ACE->PC1_CTRL,\r
  74     &ACE->PC2_CTRL\r
  75 };\r
  76 \r
  77 static uint32_t volatile * const sse_pc_lo_lut[NB_OF_ANALOG_BLOCKS] =\r
  78 {\r
  79     &ACE->PC0_LO,\r
  80     &ACE->PC1_LO,\r
  81     &ACE->PC2_LO\r
  82 };\r
  83 \r
  84 static uint32_t volatile * const sse_pc_hi_lut[NB_OF_ANALOG_BLOCKS] =\r
  85 {\r
  86     &ACE->PC0_HI,\r
  87     &ACE->PC1_HI,\r
  88     &ACE->PC2_HI\r
  89 };\r
  90 \r
  91 /*-------------------------------------------------------------------------*//**\r
  92  *\r
  93  */\r
  94 void ACE_load_sse\r
  95 (\r
  96     sse_sequence_handle_t  sequence\r
  97 )\r
  98 {\r
  99     ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );\r
 100     \r
 101     if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
 102     {\r
 103         uint16_t i;\r
 104         uint16_t offset;\r
 105         const uint16_t * p_ucode;\r
 106         \r
 107         ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
 108         \r
 109         if ( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS )\r
 110         {\r
 111             /* Stop relevant program counter. */\r
 112             *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;\r
 113             \r
 114             /* Load microcode into SEE RAM.*/\r
 115             p_ucode = g_sse_sequences_desc_table[sequence].sse_ucode;\r
 116             offset = g_sse_sequences_desc_table[sequence].sse_load_offset;\r
 117             \r
 118             for ( i = 0u; i < g_sse_sequences_desc_table[sequence].sse_ucode_length; ++i )\r
 119             {\r
 120                 ACE->SSE_RAM_DATA[offset + i] = (uint32_t)*p_ucode;\r
 121                 ++p_ucode;\r
 122             }\r
 123         }\r
 124     }\r
 125 }\r
 126 \r
 127 \r
 128 /*-------------------------------------------------------------------------*//**\r
 129  *\r
 130  */\r
 131 void ACE_start_sse\r
 132 (\r
 133     sse_sequence_handle_t  sequence\r
 134 )\r
 135 {\r
 136     ASSERT( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES );\r
 137     \r
 138     if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
 139     {\r
 140         uint16_t pc;\r
 141         \r
 142         ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
 143         ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );\r
 144     \r
 145         pc = g_sse_sequences_desc_table[sequence].sse_load_offset;\r
 146         \r
 147         if ( pc < 256u )\r
 148         {\r
 149             *sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;\r
 150         }\r
 151         else\r
 152         {\r
 153             *sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;\r
 154         }\r
 155         \r
 156         *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
 157         \r
 158         /* Enable Sample Sequencing Engine in case it was not done as part of\r
 159          * system boot. */\r
 160         ACE->SSE_TS_CTRL |= TS_ENABLE_MASK;\r
 161     }\r
 162 }\r
 163 \r
 164 /*-------------------------------------------------------------------------*//**\r
 165  *\r
 166  */\r
 167 void ACE_restart_sse\r
 168 (\r
 169     sse_sequence_handle_t  sequence\r
 170 )\r
 171 {\r
 172     ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
 173     ASSERT( g_sse_sequences_desc_table[sequence].sse_pc_id < NB_OF_ANALOG_BLOCKS );\r
 174     ASSERT( g_sse_sequences_desc_table[sequence].sse_load_offset < SEE_RAM_WORD_SIZE );\r
 175     \r
 176     if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
 177     {\r
 178         uint16_t pc;\r
 179         \r
 180         pc = g_sse_sequences_desc_table[sequence].sse_loop_pc;\r
 181         \r
 182         if ( pc < 256u )\r
 183         {\r
 184             *sse_pc_lo_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc;\r
 185         }\r
 186         else\r
 187         {\r
 188             *sse_pc_hi_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = pc - 256;\r
 189         }\r
 190         \r
 191         *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
 192     }\r
 193 }\r
 194 \r
 195 /*-------------------------------------------------------------------------*//**\r
 196  *\r
 197  */\r
 198 void ACE_stop_sse\r
 199 (\r
 200     sse_sequence_handle_t  sequence\r
 201 )\r
 202 {\r
 203     ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
 204     \r
 205     if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
 206     {\r
 207         /* Stop relevant program counter. */\r
 208         *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_STOP;\r
 209     }\r
 210 }\r
 211 \r
 212 /*-------------------------------------------------------------------------*//**\r
 213  *\r
 214  */\r
 215 void ACE_resume_sse\r
 216 (\r
 217     sse_sequence_handle_t  sequence\r
 218 )\r
 219 {\r
 220     ASSERT( sequence < ACE_NB_OF_SSE_PROCEDURES );\r
 221     \r
 222     if ( sequence < (sse_sequence_handle_t)ACE_NB_OF_SSE_PROCEDURES )\r
 223     {\r
 224         *sse_pc_ctrl_lut[g_sse_sequences_desc_table[sequence].sse_pc_id] = SSE_START;\r
 225     }\r
 226 }\r
 227 \r
 228 /*-------------------------------------------------------------------------*//**\r
 229  *\r
 230  */\r
 231 void ACE_enable_sse_irq\r
 232 (\r
 233         sse_irq_id_t sse_irq_id\r
 234 )\r
 235 {\r
 236     ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
 237     \r
 238     ACE->SSE_IRQ_EN |= 1uL << (uint32_t)sse_irq_id;\r
 239 }\r
 240 \r
 241 /*-------------------------------------------------------------------------*//**\r
 242  *\r
 243  */\r
 244 void ACE_disable_sse_irq\r
 245 (\r
 246         sse_irq_id_t sse_irq_id\r
 247 )\r
 248 {\r
 249     ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
 250     \r
 251     ACE->SSE_IRQ_EN &= (uint32_t)~(1uL << (uint32_t)sse_irq_id);\r
 252 }\r
 253 \r
 254 /*-------------------------------------------------------------------------*//**\r
 255  *\r
 256  */\r
 257 void ACE_clear_sse_irq\r
 258 (\r
 259         sse_irq_id_t sse_irq_id\r
 260 )\r
 261 {\r
 262     ASSERT( sse_irq_id < NB_OF_SSE_FLAG_IRQS );\r
 263     \r
 264     ACE->SSE_IRQ_CLR |= 1uL << (uint32_t)sse_irq_id;\r
 265 }\r
 266 \r
 267 /*-------------------------------------------------------------------------*//**\r
 268  *\r
 269  */\r
 270 void ACE_clear_sample_pipeline(void)\r
 271 {\r
 272     uint32_t saved_sse_ctrl;\r
 273     uint32_t saved_ppe_ctrl;\r
 274     \r
 275     /* Pause the Sample Sequencing Engine. */\r
 276     saved_sse_ctrl = ACE->SSE_TS_CTRL;\r
 277     ACE->SSE_TS_CTRL = ACE->SSE_TS_CTRL & ~((uint32_t)TS_ENABLE_MASK);\r
 278     \r
 279     /* Pause the Post Processing Engine. */\r
 280     saved_ppe_ctrl = ACE->PPE_CTRL;\r
 281     ACE->PPE_CTRL = ACE->PPE_CTRL & ~((uint32_t)PPE_ENABLE_MASK);\r
 282     \r
 283     /* Reset the ADCs */\r
 284     ACE->ADC0_MISC_CTRL |= ADC_RESET_MASK;\r
 285     ACE->ADC1_MISC_CTRL |= ADC_RESET_MASK;\r
 286     ACE->ADC2_MISC_CTRL |= ADC_RESET_MASK;\r
 287     \r
 288     /* Clear ADC FIFOs */\r
 289     ACE->ADC0_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
 290     ACE->ADC1_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
 291     ACE->ADC2_FIFO_CTRL |= ADC_FIFO_CLR_MASK;\r
 292     \r
 293     /* clear DMA FIFOs */\r
 294     ACE->PPE_PDMA_CTRL |= PDMA_DATAOUT_CLR_MASK;\r
 295     \r
 296     /* Unpause the Post Processing Engine. */\r
 297     ACE->PPE_CTRL = saved_ppe_ctrl;\r
 298     \r
 299     /* Unpause the Sample Sequencing Engine. */\r
 300     ACE->SSE_TS_CTRL = saved_sse_ctrl;\r
 301 }\r
 302 \r
 303 #ifdef __cplusplus\r
 304 }\r
 305 #endif\r
 306 \r