1 /***************************************************************************//**
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3 * SmartFusion MSS Ethernet MAC internal defines header file.
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5 * (c) Copyright 2007 Actel Corporation
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7 * SVN $Revision: 2299 $
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8 * SVN $Date: 2010-02-24 21:21:12 +0000 (Wed, 24 Feb 2010) $
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9 *******************************************************************************/
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10 #ifndef __MSS_ETHERNET_MAC_DESC_H
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11 #define __MSS_ETHERNET_MAC_DESC_H 1
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17 /*******************************************************************************
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18 * Receive descriptor bits
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21 /***************************************************************************//**
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23 * 1 - Core10/100 owns the descriptor. <br>
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24 * 0 - The host owns the descriptor. <br>
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25 * Core10/100 will clear this bit when it completes a current frame reception or
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26 * when the data buffers associated with a given descriptor are already full.
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28 #define RDES0_OWN 0x80000000UL
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30 /***************************************************************************//**
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32 * When set, indicates that a received frame did not pass the address recognition process.
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33 * This bit is valid only for the last descriptor of the frame (RDES0.8 set), when the CSR6.30 (receive all) bit
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34 * is set and the frame is at least 64 bytes long.
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36 #define RDES0_FF 0x40000000UL
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38 /***************************************************************************//**
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40 * Indicates the length, in bytes, of the data transferred into a host memory for a given frame
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41 * This bit is valid only when RDES0.8 (last descriptor) is set and RDES0.14 (descriptor error) is cleared.
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43 #define RDES0_FL_MASK 0x00003FFFUL
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44 #define RDES0_FL_OFFSET 16
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46 /***************************************************************************//**
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48 * This bit is a logical OR of the following bits:
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49 * RDES0.1 - CRC error
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50 * RDES0.6 - Collision seen
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51 * RDES0.7 - Frame too long
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52 * RDES0.11 - Runt frame
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53 * RDES0.14 - Descriptor error
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54 * This bit is valid only when RDES0.8 (last descriptor) is set.
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56 #define RDES0_ES 0x00008000UL
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58 /***************************************************************************//**
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60 * Set by Core10/100 when no receive buffer was available when trying to store the received data.
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61 * This bit is valid only when RDES0.8 (last descriptor) is set.
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63 #define RDES0_DE 0x00004000UL
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65 /***************************************************************************//**
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67 * When set, indicates that the frame is damaged by a collision or by a premature termination before the end
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68 * of a collision window.
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69 * This bit is valid only when RDES0.8 (last descriptor) is set.
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71 #define RDES0_RF 0x00000800UL
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73 /***************************************************************************//**
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75 * When set, indicates that the frame has a multicast address.
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76 * This bit is valid only when RDES0.8 (last descriptor) is set.
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78 #define RDES0_MF 0x00000400UL
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80 /***************************************************************************//**
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82 * When set, indicates that this is the first descriptor of a frame.
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84 #define RDES0_FS 0x00000200UL
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86 /***************************************************************************//**
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88 * When set, indicates that this is the last descriptor of a frame.
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90 #define RDES0_LS 0x00000100UL
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92 /***************************************************************************//**
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94 * When set, indicates that a current frame is longer than maximum size of 1,518 bytes, as specified by 802.3.
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95 * TL (frame too long) in the receive descriptor has been set when the received frame is longer than
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96 * 1,518 bytes. This flag is valid in all receive descriptors when multiple descriptors are used for one frame.
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98 #define RDES0_TL 0x00000080UL
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100 /***************************************************************************//**
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102 * When set, indicates that a late collision was seen (collision after 64 bytes following SFD).
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103 * This bit is valid only when RDES0.8 (last descriptor) is set.
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105 #define RDES0_CS 0x00000040UL
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107 /***************************************************************************//**
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109 * When set, indicates that the frame has a length field larger than 1,500 (Ethernet-type frame). When
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110 * cleared, indicates an 802.3-type frame.
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111 * This bit is valid only when RDES0.8 (last descriptor) is set.
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112 * Additionally, FT is invalid for runt frames shorter than 14 bytes.
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114 #define RDES0_FT 0x00000020UL
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116 /***************************************************************************//**
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117 * Report on MII error.
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118 * When set, indicates that an error has been detected by a physical layer chip connected through the MII
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120 * This bit is valid only when RDES0.8 (last descriptor) is set.
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122 #define RDES0_RE 0x00000008UL
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124 /***************************************************************************//**
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126 * When set, indicates that the frame was not byte-aligned.
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127 * This bit is valid only when RDES0.8 (last descriptor) is set.
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129 #define RDES0_DB 0x00000004UL
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131 /***************************************************************************//**
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133 * When set, indicates that a CRC error has occurred in the received frame.
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134 * This bit is valid only when RDES0.8 (last descriptor) is set.
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135 * Additionally, CE is not valid when the received frame is a runt frame.
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137 #define RDES0_CE 0x00000002UL
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139 /***************************************************************************//**
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140 * This bit is reset for frames with a legal length.
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142 #define RDES0_ZERO 0x00000001UL
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144 /***************************************************************************//**
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145 * Receive end of ring.
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146 * When set, indicates that this is the last descriptor in the receive descriptor ring. Core10/100 returns to the
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147 * first descriptor in the ring, as specified by CSR3 (start of receive list address).
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149 #define RDES1_RER 0x02000000UL
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151 /***************************************************************************//**
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152 * Second address chained.
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153 * When set, indicates that the second buffer's address points to the next descriptor and not to the data buffer.
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154 * Note that RER takes precedence over RCH.
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156 #define RDES1_RCH 0x01000000UL
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158 /***************************************************************************//**
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160 * Indicates the size, in bytes, of memory space used by the second data buffer. This number must be a
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161 * multiple of four. If it is 0, Core10/100 ignores the second data buffer and fetches the next data descriptor.
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162 * This number is valid only when RDES1.24 (second address chained) is cleared.
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164 #define RDES1_RBS2_MASK 0x7FF
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165 #define RDES1_RBS2_OFFSET 11
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167 /***************************************************************************//**
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169 * Indicates the size, in bytes, of memory space used by the first data buffer. This number must be a multiple of
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170 * four. If it is 0, Core10/100 ignores the first data buffer and uses the second data buffer.
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172 #define RDES1_RBS1_MASK 0x7FF
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173 #define RDES1_RBS1_OFFSET 0
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176 /*******************************************************************************
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177 * Transmit descriptor bits
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180 /***************************************************************************//**
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182 * 1 - Core10/100 owns the descriptor.
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183 * 0 - The host owns the descriptor.
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184 * Core10/100 will clear this bit when it completes a current frame transmission or when the data buffers
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185 * associated with a given descriptor are empty.
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187 #define TDES0_OWN 0x80000000uL
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189 /***************************************************************************//**
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191 * This bit is a logical OR of the following bits:
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192 * TDES0.1 - Underflow error
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193 * TDES0.8 - Excessive collision error
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194 * TDES0.9 - Late collision
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195 * TDES0.10 - No carrier
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196 * TDES0.11 - Loss of carrier
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197 * This bit is valid only when TDES1.30 (last descriptor) is set.
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199 #define TDES0_ES ((uint32_t)1 << 15)
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201 /***************************************************************************//**
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203 * When set, indicates a loss of the carrier during a transmission.
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204 * This bit is valid only when TDES1.30 (last descriptor) is set.
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206 #define TDES0_LO ((uint32_t)1 << 11)
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208 /***************************************************************************//**
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210 * When set, indicates that the carrier was not asserted by an external transceiver during the transmission.
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211 * This bit is valid only when TDES1.30 (last descriptor) is set.
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213 #define TDES0_NC ((uint32_t)1 << 10)
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215 /***************************************************************************//**
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217 * When set, indicates that a collision was detected after transmitting 64 bytes.
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218 * This bit is not valid when TDES0.1 (underflow error) is set.
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219 * This bit is valid only when TDES1.30 (last descriptor) is set.
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221 #define TDES0_LC ((uint32_t)1 << 9)
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223 /***************************************************************************//**
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224 * Excessive collisions.
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225 * When set, indicates that the transmission was aborted after 16 retries.
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226 * This bit is valid only when TDES1.30 (last descriptor) is set.
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228 #define TDES0_EC ((uint32_t)1 << 8)
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230 /***************************************************************************//**
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232 * This field indicates the number of collisions that occurred before the end of a frame transmission.
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233 * This value is not valid when TDES0.8 (excessive collisions bit) is set.
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234 * This bit is valid only when TDES1.30 (last descriptor) is set.
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236 #define TDES0_CC_MASK 0xFu
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237 #define TDES0_CC_OFFSET 3u
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239 /***************************************************************************//**
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241 * When set, indicates that the FIFO was empty during the frame transmission.
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242 * This bit is valid only when TDES1.30 (last descriptor) is set.
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244 #define TDES0_UF ((uint32_t)1 << 1)
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246 /***************************************************************************//**
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248 * When set, indicates that the frame was deferred before transmission. Deferring occurs if the carrier is detected
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249 * when the transmission is ready to start.
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250 * This bit is valid only when TDES1.30 (last descriptor) is set.
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252 #define TDES0_DE (1)
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254 /***************************************************************************//**
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255 * Interrupt on completion.
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256 * Setting this flag instructs Core10/100 to set CSR5.0 (transmit interrupt) immediately after processing a
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258 * This bit is valid when TDES1.30 (last descriptor) is set or for a setup packet.
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260 #define TDES1_IC ((uint32_t)1 << 31)
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262 /***************************************************************************//**
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264 * When set, indicates the last descriptor of the frame.
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266 #define TDES1_LS ((uint32_t)1 << 30)
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268 /***************************************************************************//**
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269 * First descriptor.
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270 * When set, indicates the first descriptor of the frame.
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272 #define TDES1_FS ((uint32_t)1 << 29)
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274 /***************************************************************************//**
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276 * This bit, together with TDES0.22 (FT0), controls a current filtering mode.
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277 * This bit is valid only for the setup frames.
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279 #define TDES1_FT1 ((uint32_t)1 << 28)
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281 /***************************************************************************//**
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283 * When set, indicates that this is a setup frame descriptor.
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285 #define TDES1_SET ((uint32_t)1 << 27)
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287 /***************************************************************************//**
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289 * When set, Core10/100 does not append the CRC value at the end of the frame. The exception is when the
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290 * frame is shorter than 64 bytes and automatic byte padding is enabled. In that case, the CRC field is added,
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291 * despite the state of the AC flag.
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293 #define TDES1_AC ((uint32_t)1 << 26)
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295 /***************************************************************************//**
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296 * Transmit end of ring.
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297 * When set, indicates the last descriptor in the descriptor ring.
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299 #define TDES1_TER ((uint32_t)1 << 25)
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301 /***************************************************************************//**
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302 * Second address chained.
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303 * When set, indicates that the second descriptor's address points to the next descriptor and not to the data
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305 * This bit is valid only when TDES1.25 (transmit end of ring) is reset.
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307 #define TDES1_TCH ((uint32_t)1 << 24)
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309 /***************************************************************************//**
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310 * Disabled padding.
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311 * When set, automatic byte padding is disabled. Core10/100 normally appends the PAD field after the INFO
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312 * field when the size of an actual frame is less than 64 bytes. After padding bytes, the CRC field is also
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313 * inserted, despite the state of the AC flag. When DPD is set, no padding bytes are appended.
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315 #define TDES1_DPD ((uint32_t)1 << 23)
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317 /***************************************************************************//**
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319 * This bit, together with TDES0.28 (FT1), controls the current filtering mode.
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320 * This bit is valid only when the TDES1.27 (SET) bit is set.
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322 #define TDES1_FT0 ((uint32_t)1 << 22)
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324 /***************************************************************************//**
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326 * Indicates the size, in bytes, of memory space used by the second data buffer. If it is zero, Core10/100 ignores
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327 * the second data buffer and fetches the next data descriptor.
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328 * This bit is valid only when TDES1.24 (second address chained) is cleared.
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330 #define TDES1_TBS2_MASK 0x7FF
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331 #define TDES1_TBS2_OFFSET 11u
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333 /***************************************************************************//**
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335 * Indicates the size, in bytes, of memory space used by the first data buffer. If it is 0, Core10/100 ignores the
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336 * first data buffer and uses the second data buffer.
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338 #define TDES1_TBS1_MASK 0x7FF
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339 #define TDES1_TBS1_OFFSET 0u
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345 #endif /* __MSS_ETHERNET_MAC_DESC_H */
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