1 //*****************************************************************************
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3 // hw_nvic.h - Macros used when accessing the NVIC hardware.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 523 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_NVIC_H__
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29 #define __HW_NVIC_H__
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31 //*****************************************************************************
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33 // The following define the addresses of the NVIC registers.
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35 //*****************************************************************************
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36 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
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37 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
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38 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
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39 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
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40 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
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41 #define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
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42 #define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
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43 #define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
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44 #define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
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45 #define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
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46 #define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
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47 #define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
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48 #define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
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49 #define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
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50 #define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
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51 #define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
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52 #define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
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53 #define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
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54 #define NVIC_CPUID 0xE000ED00 // CPUID Base Register
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55 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
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56 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
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57 #define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
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58 #define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
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59 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
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60 #define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
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61 #define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
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62 #define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
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63 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
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64 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
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65 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
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66 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
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67 #define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
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68 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
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69 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
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70 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
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71 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
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72 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
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73 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
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74 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
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75 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
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76 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
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77 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
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78 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
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80 //*****************************************************************************
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82 // The following define the bit fields in the NVIC_INT_TYPE register.
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84 //*****************************************************************************
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85 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
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86 #define NVIC_INT_TYPE_LINES_S 0
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88 //*****************************************************************************
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90 // The following define the bit fields in the NVIC_ST_CTRL register.
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92 //*****************************************************************************
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93 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
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94 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
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95 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
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96 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
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98 //*****************************************************************************
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100 // The following define the bit fields in the NVIC_ST_RELOAD register.
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102 //*****************************************************************************
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103 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
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104 #define NVIC_ST_RELOAD_S 0
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106 //*****************************************************************************
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108 // The following define the bit fields in the NVIC_ST_CURRENT register.
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110 //*****************************************************************************
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111 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
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112 #define NVIC_ST_CURRENT_S 0
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114 //*****************************************************************************
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116 // The following define the bit fields in the NVIC_ST_CAL register.
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118 //*****************************************************************************
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119 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
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120 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
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121 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
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122 #define NVIC_ST_CAL_ONEMS_S 0
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124 //*****************************************************************************
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126 // The following define the bit fields in the NVIC_EN0 register.
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128 //*****************************************************************************
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129 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
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130 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
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131 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
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132 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
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133 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
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134 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
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135 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
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136 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
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137 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
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138 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
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139 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
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140 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
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141 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
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142 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
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143 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
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144 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
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145 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
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146 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
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147 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
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148 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
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149 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
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150 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
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151 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
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152 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
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153 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
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154 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
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155 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
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156 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
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157 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
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158 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
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159 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
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160 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
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162 //*****************************************************************************
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164 // The following define the bit fields in the NVIC_DIS0 register.
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166 //*****************************************************************************
\r
167 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
\r
168 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
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169 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
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170 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
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171 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
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172 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
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173 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
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174 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
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175 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
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176 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
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177 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
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178 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
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179 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
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180 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
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181 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
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182 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
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183 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
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184 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
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185 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
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186 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
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187 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
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188 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
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189 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
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190 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
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191 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
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192 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
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193 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
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194 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
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195 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
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196 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
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197 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
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198 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
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200 //*****************************************************************************
\r
202 // The following define the bit fields in the NVIC_PEND0 register.
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204 //*****************************************************************************
\r
205 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
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206 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
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207 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
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208 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
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209 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
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210 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
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211 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
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212 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
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213 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
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214 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
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215 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
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216 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
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217 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
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218 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
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219 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
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220 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
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221 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
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222 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
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223 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
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224 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
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225 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
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226 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
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227 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
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228 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
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229 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
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230 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
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231 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
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232 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
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233 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
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234 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
\r
235 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
\r
236 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
\r
238 //*****************************************************************************
\r
240 // The following define the bit fields in the NVIC_UNPEND0 register.
\r
242 //*****************************************************************************
\r
243 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
\r
244 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
\r
245 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
\r
246 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
\r
247 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
\r
248 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
\r
249 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
\r
250 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
\r
251 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
\r
252 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
\r
253 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
\r
254 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
\r
255 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
\r
256 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
\r
257 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
\r
258 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
\r
259 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
\r
260 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
\r
261 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
\r
262 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
\r
263 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
\r
264 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
\r
265 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
\r
266 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
\r
267 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
\r
268 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
\r
269 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
\r
270 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
\r
271 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
\r
272 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
\r
273 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
\r
274 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
\r
276 //*****************************************************************************
\r
278 // The following define the bit fields in the NVIC_ACTIVE0 register.
\r
280 //*****************************************************************************
\r
281 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
\r
282 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
\r
283 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
\r
284 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
\r
285 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
\r
286 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
\r
287 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
\r
288 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
\r
289 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
\r
290 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
\r
291 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
\r
292 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
\r
293 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
\r
294 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
\r
295 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
\r
296 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
\r
297 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
\r
298 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
\r
299 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
\r
300 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
\r
301 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
\r
302 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
\r
303 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
\r
304 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
\r
305 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
\r
306 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
\r
307 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
\r
308 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
\r
309 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
\r
310 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
\r
311 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
\r
312 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
\r
314 //*****************************************************************************
\r
316 // The following define the bit fields in the NVIC_PRI0 register.
\r
318 //*****************************************************************************
\r
319 #define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
\r
320 #define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
\r
321 #define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
\r
322 #define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
\r
323 #define NVIC_PRI0_INT3_S 24
\r
324 #define NVIC_PRI0_INT2_S 16
\r
325 #define NVIC_PRI0_INT1_S 8
\r
326 #define NVIC_PRI0_INT0_S 0
\r
328 //*****************************************************************************
\r
330 // The following define the bit fields in the NVIC_PRI1 register.
\r
332 //*****************************************************************************
\r
333 #define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
\r
334 #define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
\r
335 #define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
\r
336 #define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
\r
337 #define NVIC_PRI1_INT7_S 24
\r
338 #define NVIC_PRI1_INT6_S 16
\r
339 #define NVIC_PRI1_INT5_S 8
\r
340 #define NVIC_PRI1_INT4_S 0
\r
342 //*****************************************************************************
\r
344 // The following define the bit fields in the NVIC_PRI2 register.
\r
346 //*****************************************************************************
\r
347 #define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
\r
348 #define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
\r
349 #define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
\r
350 #define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
\r
351 #define NVIC_PRI2_INT11_S 24
\r
352 #define NVIC_PRI2_INT10_S 16
\r
353 #define NVIC_PRI2_INT9_S 8
\r
354 #define NVIC_PRI2_INT8_S 0
\r
356 //*****************************************************************************
\r
358 // The following define the bit fields in the NVIC_PRI3 register.
\r
360 //*****************************************************************************
\r
361 #define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
\r
362 #define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
\r
363 #define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
\r
364 #define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
\r
365 #define NVIC_PRI3_INT15_S 24
\r
366 #define NVIC_PRI3_INT14_S 16
\r
367 #define NVIC_PRI3_INT13_S 8
\r
368 #define NVIC_PRI3_INT12_S 0
\r
370 //*****************************************************************************
\r
372 // The following define the bit fields in the NVIC_PRI4 register.
\r
374 //*****************************************************************************
\r
375 #define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
\r
376 #define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
\r
377 #define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
\r
378 #define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
\r
379 #define NVIC_PRI4_INT19_S 24
\r
380 #define NVIC_PRI4_INT18_S 16
\r
381 #define NVIC_PRI4_INT17_S 8
\r
382 #define NVIC_PRI4_INT16_S 0
\r
384 //*****************************************************************************
\r
386 // The following define the bit fields in the NVIC_PRI5 register.
\r
388 //*****************************************************************************
\r
389 #define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
\r
390 #define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
\r
391 #define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
\r
392 #define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
\r
393 #define NVIC_PRI5_INT23_S 24
\r
394 #define NVIC_PRI5_INT22_S 16
\r
395 #define NVIC_PRI5_INT21_S 8
\r
396 #define NVIC_PRI5_INT20_S 0
\r
398 //*****************************************************************************
\r
400 // The following define the bit fields in the NVIC_PRI6 register.
\r
402 //*****************************************************************************
\r
403 #define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
\r
404 #define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
\r
405 #define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
\r
406 #define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
\r
407 #define NVIC_PRI6_INT27_S 24
\r
408 #define NVIC_PRI6_INT26_S 16
\r
409 #define NVIC_PRI6_INT25_S 8
\r
410 #define NVIC_PRI6_INT24_S 0
\r
412 //*****************************************************************************
\r
414 // The following define the bit fields in the NVIC_PRI7 register.
\r
416 //*****************************************************************************
\r
417 #define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
\r
418 #define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
\r
419 #define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
\r
420 #define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
\r
421 #define NVIC_PRI7_INT31_S 24
\r
422 #define NVIC_PRI7_INT30_S 16
\r
423 #define NVIC_PRI7_INT29_S 8
\r
424 #define NVIC_PRI7_INT28_S 0
\r
426 //*****************************************************************************
\r
428 // The following define the bit fields in the NVIC_CPUID register.
\r
430 //*****************************************************************************
\r
431 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
\r
432 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant
\r
433 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
\r
434 #define NVIC_CPUID_REV_M 0x0000000F // Revision
\r
436 //*****************************************************************************
\r
438 // The following define the bit fields in the NVIC_INT_CTRL register.
\r
440 //*****************************************************************************
\r
441 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
\r
442 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
\r
443 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
\r
444 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
\r
445 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
\r
446 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
\r
447 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
\r
448 #define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
\r
449 #define NVIC_INT_CTRL_VEC_PEN_S 12
\r
450 #define NVIC_INT_CTRL_VEC_ACT_S 0
\r
452 //*****************************************************************************
\r
454 // The following define the bit fields in the NVIC_VTABLE register.
\r
456 //*****************************************************************************
\r
457 #define NVIC_VTABLE_BASE 0x20000000 // Vector table base
\r
458 #define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
\r
459 #define NVIC_VTABLE_OFFSET_S 8
\r
461 //*****************************************************************************
\r
463 // The following define the bit fields in the NVIC_APINT register.
\r
465 //*****************************************************************************
\r
466 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
\r
467 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
\r
468 #define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
\r
469 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
\r
470 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
\r
471 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
\r
472 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
\r
473 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
\r
474 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
\r
475 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
\r
476 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
\r
477 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
\r
478 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
\r
479 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
\r
480 #define NVIC_APINT_VECT_RESET 0x00000001 // System reset
\r
482 //*****************************************************************************
\r
484 // The following define the bit fields in the NVIC_SYS_CTRL register.
\r
486 //*****************************************************************************
\r
487 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
\r
488 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
\r
489 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
\r
491 //*****************************************************************************
\r
493 // The following define the bit fields in the NVIC_CFG_CTRL register.
\r
495 //*****************************************************************************
\r
496 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
\r
497 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
\r
498 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
\r
499 #define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
\r
500 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
\r
501 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
\r
503 //*****************************************************************************
\r
505 // The following define the bit fields in the NVIC_SYS_PRI1 register.
\r
507 //*****************************************************************************
\r
508 #define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
\r
509 #define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
\r
510 #define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
\r
511 #define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
\r
512 #define NVIC_SYS_PRI1_USAGE_S 16
\r
513 #define NVIC_SYS_PRI1_BUS_S 8
\r
514 #define NVIC_SYS_PRI1_MEM_S 0
\r
516 //*****************************************************************************
\r
518 // The following define the bit fields in the NVIC_SYS_PRI2 register.
\r
520 //*****************************************************************************
\r
521 #define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
\r
522 #define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
\r
523 #define NVIC_SYS_PRI2_SVC_S 24
\r
525 //*****************************************************************************
\r
527 // The following define the bit fields in the NVIC_SYS_PRI3 register.
\r
529 //*****************************************************************************
\r
530 #define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
\r
531 #define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
\r
532 #define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
\r
533 #define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
\r
534 #define NVIC_SYS_PRI3_TICK_S 24
\r
535 #define NVIC_SYS_PRI3_PENDSV_S 16
\r
536 #define NVIC_SYS_PRI3_DEBUG_S 0
\r
538 //*****************************************************************************
\r
540 // The following define the bit fields in the NVIC_SYS_HND_CTRL register.
\r
542 //*****************************************************************************
\r
543 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
\r
544 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
\r
545 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
\r
546 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
\r
547 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
\r
548 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
\r
549 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
\r
550 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
\r
551 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
\r
552 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
\r
553 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
\r
554 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
\r
556 //*****************************************************************************
\r
558 // The following define the bit fields in the NVIC_FAULT_STAT register.
\r
560 //*****************************************************************************
\r
561 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
\r
562 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
\r
563 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
\r
564 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
\r
565 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
\r
566 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
\r
567 #define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
\r
568 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
\r
569 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
\r
570 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
\r
571 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
\r
572 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
\r
573 #define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
\r
574 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
\r
575 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
\r
576 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
\r
577 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
\r
579 //*****************************************************************************
\r
581 // The following define the bit fields in the NVIC_HFAULT_STAT register.
\r
583 //*****************************************************************************
\r
584 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
\r
585 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
\r
586 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
\r
588 //*****************************************************************************
\r
590 // The following define the bit fields in the NVIC_DEBUG_STAT register.
\r
592 //*****************************************************************************
\r
593 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
\r
594 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
\r
595 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
\r
596 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
\r
597 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
\r
599 //*****************************************************************************
\r
601 // The following define the bit fields in the NVIC_MM_ADDR register.
\r
603 //*****************************************************************************
\r
604 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
\r
605 #define NVIC_MM_ADDR_S 0
\r
607 //*****************************************************************************
\r
609 // The following define the bit fields in the NVIC_FAULT_ADDR register.
\r
611 //*****************************************************************************
\r
612 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
\r
613 #define NVIC_FAULT_ADDR_S 0
\r
615 //*****************************************************************************
\r
617 // The following define the bit fields in the NVIC_EXC_STACK register.
\r
619 //*****************************************************************************
\r
620 #define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack
\r
622 //*****************************************************************************
\r
624 // The following define the bit fields in the NVIC_EXC_NUM register.
\r
626 //*****************************************************************************
\r
627 #define NVIC_EXC_NUM_M 0x000003FF // Exception number
\r
628 #define NVIC_EXC_NUM_S 0
\r
630 //*****************************************************************************
\r
632 // The following define the bit fields in the NVIC_COPRO register.
\r
634 //*****************************************************************************
\r
635 #define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask
\r
636 #define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied
\r
637 #define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess
\r
638 #define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access
\r
639 #define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask
\r
640 #define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied
\r
641 #define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess
\r
642 #define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access
\r
643 #define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask
\r
644 #define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied
\r
645 #define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess
\r
646 #define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access
\r
647 #define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask
\r
648 #define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied
\r
649 #define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess
\r
650 #define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access
\r
651 #define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask
\r
652 #define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied
\r
653 #define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess
\r
654 #define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access
\r
655 #define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask
\r
656 #define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied
\r
657 #define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess
\r
658 #define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access
\r
659 #define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask
\r
660 #define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied
\r
661 #define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess
\r
662 #define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access
\r
663 #define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask
\r
664 #define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied
\r
665 #define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess
\r
666 #define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access
\r
667 #define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask
\r
668 #define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied
\r
669 #define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess
\r
670 #define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access
\r
671 #define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask
\r
672 #define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied
\r
673 #define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess
\r
674 #define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access
\r
675 #define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask
\r
676 #define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied
\r
677 #define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess
\r
678 #define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access
\r
679 #define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask
\r
680 #define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied
\r
681 #define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess
\r
682 #define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access
\r
683 #define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask
\r
684 #define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied
\r
685 #define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess
\r
686 #define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access
\r
687 #define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask
\r
688 #define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied
\r
689 #define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess
\r
690 #define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access
\r
691 #define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask
\r
692 #define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied
\r
693 #define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess
\r
694 #define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access
\r
695 #define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask
\r
696 #define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied
\r
697 #define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess
\r
698 #define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access
\r
700 //*****************************************************************************
\r
702 // The following define the bit fields in the NVIC_MPU_TYPE register.
\r
704 //*****************************************************************************
\r
705 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
\r
706 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
\r
707 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
\r
708 #define NVIC_MPU_TYPE_IREGION_S 16
\r
709 #define NVIC_MPU_TYPE_DREGION_S 8
\r
711 //*****************************************************************************
\r
713 // The following define the bit fields in the NVIC_MPU_CTRL register.
\r
715 //*****************************************************************************
\r
716 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
\r
717 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
\r
719 //*****************************************************************************
\r
721 // The following define the bit fields in the NVIC_MPU_NUMBER register.
\r
723 //*****************************************************************************
\r
724 #define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
\r
725 #define NVIC_MPU_NUMBER_S 0
\r
727 //*****************************************************************************
\r
729 // The following define the bit fields in the NVIC_MPU_BASE register.
\r
731 //*****************************************************************************
\r
732 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address
\r
733 #define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
\r
734 #define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
\r
735 #define NVIC_MPU_BASE_ADDR_S 8
\r
736 #define NVIC_MPU_BASE_REGION_S 0
\r
738 //*****************************************************************************
\r
740 // The following define the bit fields in the NVIC_MPU_ATTR register.
\r
742 //*****************************************************************************
\r
743 #define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes
\r
744 #define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable
\r
745 #define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size
\r
747 //*****************************************************************************
\r
749 // The following define the bit fields in the NVIC_DBG_CTRL register.
\r
751 //*****************************************************************************
\r
752 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
\r
753 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
\r
754 #define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
\r
755 #define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
\r
756 #define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
\r
757 #define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
\r
758 #define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
\r
759 #define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
\r
760 #define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
\r
761 #define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
\r
762 #define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
\r
763 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
\r
764 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
\r
765 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
\r
766 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
\r
768 //*****************************************************************************
\r
770 // The following define the bit fields in the NVIC_DBG_XFER register.
\r
772 //*****************************************************************************
\r
773 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
\r
774 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
\r
775 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
\r
776 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
\r
777 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
\r
778 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
\r
779 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
\r
780 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
\r
781 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
\r
782 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
\r
783 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
\r
784 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
\r
785 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
\r
786 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
\r
787 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
\r
788 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
\r
789 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
\r
790 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
\r
791 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
\r
792 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
\r
793 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
\r
794 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
\r
795 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
\r
797 //*****************************************************************************
\r
799 // The following define the bit fields in the NVIC_DBG_DATA register.
\r
801 //*****************************************************************************
\r
802 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
\r
803 #define NVIC_DBG_DATA_S 0
\r
805 //*****************************************************************************
\r
807 // The following define the bit fields in the NVIC_DBG_INT register.
\r
809 //*****************************************************************************
\r
810 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
\r
811 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
\r
812 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
\r
813 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
\r
814 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
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815 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
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816 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
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817 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
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818 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
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819 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
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820 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
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822 //*****************************************************************************
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824 // The following define the bit fields in the NVIC_SW_TRIG register.
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826 //*****************************************************************************
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827 #define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
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828 #define NVIC_SW_TRIG_INTID_S 0
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830 #endif // __HW_NVIC_H__
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