1 //*****************************************************************************
\r
3 // hw_sysctl.h - Macros used when accessing the system control hardware.
\r
5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
\r
7 // Software License Agreement
\r
9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
\r
10 // exclusively on LMI's Stellaris Family of microcontroller products.
\r
12 // The software is owned by LMI and/or its suppliers, and is protected under
\r
13 // applicable copyright laws. All rights are reserved. Any use in violation
\r
14 // of the foregoing restrictions may subject the user to criminal sanctions
\r
15 // under applicable laws, as well as to civil liability for the breach of the
\r
16 // terms and conditions of this license.
\r
18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
24 // This is part of revision 523 of the Stellaris Driver Library.
\r
26 //*****************************************************************************
\r
28 #ifndef __HW_SYSCTL_H__
\r
29 #define __HW_SYSCTL_H__
\r
31 //*****************************************************************************
\r
33 // The following define the offsets of the system control registers.
\r
35 //*****************************************************************************
\r
36 #define SYSCTL_DID0 0x400fe000 // Device identification register 0
\r
37 #define SYSCTL_DID1 0x400fe004 // Device identification register 1
\r
38 #define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
\r
39 #define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
\r
40 #define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
\r
41 #define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
\r
42 #define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
\r
43 #define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
\r
44 #define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
\r
45 #define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
\r
46 #define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
\r
47 #define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
\r
48 #define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
\r
49 #define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
\r
50 #define SYSCTL_MISC 0x400fe058 // Interrupt status register
\r
51 #define SYSCTL_RESC 0x400fe05c // Reset cause register
\r
52 #define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
\r
53 #define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
\r
54 #define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
\r
55 #define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
\r
56 #define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
\r
57 #define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
\r
58 #define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
\r
59 #define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
\r
60 #define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
\r
61 #define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
\r
62 #define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
\r
63 #define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
\r
64 #define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
\r
66 //*****************************************************************************
\r
68 // The following define the bit fields in the SYSCTL_DID0 register.
\r
70 //*****************************************************************************
\r
71 #define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
\r
72 #define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
\r
73 #define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
\r
74 #define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
\r
75 #define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
\r
76 #define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
\r
78 //*****************************************************************************
\r
80 // The following define the bit fields in the SYSCTL_DID1 register.
\r
82 //*****************************************************************************
\r
83 #define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
\r
84 #define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
\r
85 #define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
\r
86 #define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
\r
87 #define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
\r
88 #define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
\r
89 #define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
\r
90 #define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
\r
91 #define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
\r
92 #define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
\r
93 #define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
\r
94 #define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
\r
95 #define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
\r
96 #define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
\r
97 #define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
\r
98 #define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
\r
99 #define SYSCTL_DID1_PRTNO_SHIFT 16
\r
101 //*****************************************************************************
\r
103 // The following define the bit fields in the SYSCTL_DC0 register.
\r
105 //*****************************************************************************
\r
106 #define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
\r
107 #define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM
\r
108 #define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
\r
109 #define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash
\r
111 //*****************************************************************************
\r
113 // The following define the bit fields in the SYSCTL_DC1 register.
\r
115 //*****************************************************************************
\r
116 #define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
\r
117 #define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
\r
118 #define SYSCTL_DC1_PLL 0x00000010 // PLL present
\r
119 #define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
\r
120 #define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
\r
121 #define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
\r
122 #define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
\r
124 //*****************************************************************************
\r
126 // The following define the bit fields in the SYSCTL_DC2 register.
\r
128 //*****************************************************************************
\r
129 #define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
\r
130 #define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
\r
131 #define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
\r
132 #define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
\r
133 #define SYSCTL_DC2_I2C 0x00001000 // I2C present
\r
134 #define SYSCTL_DC2_SSI 0x00000010 // SSI present
\r
135 #define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
\r
137 //*****************************************************************************
\r
139 // The following define the bit fields in the SYSCTL_DC3 register.
\r
141 //*****************************************************************************
\r
142 #define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
\r
143 #define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
\r
144 #define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
\r
145 #define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
\r
146 #define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
\r
147 #define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
\r
148 #define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
\r
150 //*****************************************************************************
\r
152 // The following define the bit fields in the SYSCTL_DC4 register.
\r
154 //*****************************************************************************
\r
155 #define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
\r
156 #define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
\r
157 #define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
\r
159 //*****************************************************************************
\r
161 // The following define the bit fields in the SYSCTL_PBORCTL register.
\r
163 //*****************************************************************************
\r
164 #define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
\r
165 #define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
\r
166 #define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
\r
167 #define SYSCTL_PBORCTL_BOR_SH 2
\r
169 //*****************************************************************************
\r
171 // The following define the bit fields in the SYSCTL_LDOPCTL register.
\r
173 //*****************************************************************************
\r
174 #define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
\r
175 #define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
\r
176 #define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
\r
177 #define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
\r
178 #define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
\r
179 #define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
\r
180 #define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
\r
181 #define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
\r
182 #define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
\r
183 #define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
\r
184 #define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
\r
185 #define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
\r
187 //*****************************************************************************
\r
189 // The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
\r
190 // SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
\r
192 //*****************************************************************************
\r
193 #define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
\r
195 //*****************************************************************************
\r
197 // The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
\r
198 // SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
\r
200 //*****************************************************************************
\r
201 #define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
\r
202 #define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
\r
203 #define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
\r
204 #define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
\r
205 #define SYSCTL_SET1_I2C 0x00001000 // I2C module
\r
206 #define SYSCTL_SET1_SSI 0x00000010 // SSI module
\r
207 #define SYSCTL_SET1_UART0 0x00000001 // UART module 0
\r
209 //*****************************************************************************
\r
211 // The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
\r
212 // SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
\r
214 //*****************************************************************************
\r
215 #define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
\r
216 #define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
\r
217 #define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
\r
219 //*****************************************************************************
\r
221 // The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
\r
222 // SYSCTL_IMS registers.
\r
224 //*****************************************************************************
\r
225 #define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
\r
226 #define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
\r
227 #define SYSCTL_INT_BOSC_FAIL 0x00000010 // Boot oscillator failure int
\r
228 #define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
\r
229 #define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
\r
230 #define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
\r
231 #define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
\r
233 //*****************************************************************************
\r
235 // The following define the bit fields in the SYSCTL_RESC register.
\r
237 //*****************************************************************************
\r
238 #define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
\r
239 #define SYSCTL_RESC_SW 0x00000010 // Software reset
\r
240 #define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
\r
241 #define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
\r
242 #define SYSCTL_RESC_POR 0x00000002 // Power on reset
\r
243 #define SYSCTL_RESC_EXT 0x00000001 // External reset
\r
245 //*****************************************************************************
\r
247 // The following define the bit fields in the SYSCTL_RCC register.
\r
249 //*****************************************************************************
\r
250 #define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
\r
251 #define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
\r
252 #define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
\r
253 #define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
\r
254 #define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
\r
255 #define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
\r
256 #define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
\r
257 #define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
\r
258 #define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
\r
259 #define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
\r
260 #define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
\r
261 #define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
\r
262 #define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
\r
263 #define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
\r
264 #define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
\r
265 #define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
\r
266 #define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
\r
267 #define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
\r
268 #define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
\r
269 #define SYSCTL_RCC_OE 0x00001000 // PLL output enable
\r
270 #define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
\r
271 #define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
\r
272 #define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
\r
273 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
\r
274 #define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
\r
275 #define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
\r
276 #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
\r
277 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
\r
278 #define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
\r
279 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
\r
280 #define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
\r
281 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
\r
282 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
\r
283 #define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
\r
284 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
\r
285 #define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
\r
286 #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
\r
287 #define SYSCTL_RCC_OSCSRC_BOOT 0x00000010 // Use the boot oscillator
\r
288 #define SYSCTL_RCC_OSCSRC_BOOT4 0x00000020 // Use the boot oscillator / 4
\r
289 #define SYSCTL_RCC_BOSCVER 0x00000008 // Boot osc. verification timer en
\r
290 #define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
\r
291 #define SYSCTL_RCC_BOSCDIS 0x00000002 // Boot oscillator disable
\r
292 #define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
\r
293 #define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
\r
294 #define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
\r
295 #define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
\r
297 //*****************************************************************************
\r
299 // The following define the bit fields in the SYSCTL_PLLCFG register.
\r
301 //*****************************************************************************
\r
302 #define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
\r
303 #define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
\r
304 #define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
\r
305 #define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
\r
306 #define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
\r
307 #define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
\r
308 #define SYSCTL_PLLCFG_F_SHIFT 5
\r
309 #define SYSCTL_PLLCFG_R_SHIFT 0
\r
311 //*****************************************************************************
\r
313 // The following define the bit fields in the SYSCTL_CLKVCLR register.
\r
315 //*****************************************************************************
\r
316 #define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
\r
318 //*****************************************************************************
\r
320 // The following define the bit fields in the SYSCTL_LDOARST register.
\r
322 //*****************************************************************************
\r
323 #define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
\r
325 #endif // __HW_SYSCTL_H__
\r