1 //*****************************************************************************
\r
3 // startup.c - Boot code for Stellaris.
\r
5 // Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
\r
7 // Software License Agreement
\r
9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
\r
10 // exclusively on LMI's microcontroller products.
\r
12 // The software is owned by LMI and/or its suppliers, and is protected under
\r
13 // applicable copyright laws. All rights are reserved. Any use in violation
\r
14 // of the foregoing restrictions may subject the user to criminal sanctions
\r
15 // under applicable laws, as well as to civil liability for the breach of the
\r
16 // terms and conditions of this license.
\r
18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
24 // This is part of revision 1392 of the Stellaris Peripheral Driver Library.
\r
26 //*****************************************************************************
\r
28 //*****************************************************************************
\r
30 // Forward declaration of the default fault handlers.
\r
32 //*****************************************************************************
\r
33 void ResetISR(void);
\r
34 static void NmiSR(void);
\r
35 static void FaultISR(void);
\r
36 static void IntDefaultHandler(void);
\r
38 //*****************************************************************************
\r
40 // The entry point for the application.
\r
42 //*****************************************************************************
\r
43 extern int main(void);
\r
44 extern void xPortPendSVHandler(void);
\r
45 extern void xPortSysTickHandler(void);
\r
46 extern void Timer0IntHandler(void);
\r
48 //*****************************************************************************
\r
50 // Reserve space for the system stack.
\r
52 //*****************************************************************************
\r
54 #define STACK_SIZE 64
\r
56 static unsigned long pulStack[STACK_SIZE];
\r
58 //*****************************************************************************
\r
60 // The minimal vector table for a Cortex M3. Note that the proper constructs
\r
61 // must be placed on this to ensure that it ends up at physical address
\r
64 //*****************************************************************************
\r
65 __attribute__ ((section(".isr_vector")))
\r
66 void (* const g_pfnVectors[])(void) =
\r
68 (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
\r
69 // The initial stack pointer
\r
70 ResetISR, // The reset handler
\r
71 NmiSR, // The NMI handler
\r
72 FaultISR, // The hard fault handler
\r
73 IntDefaultHandler, // The MPU fault handler
\r
74 IntDefaultHandler, // The bus fault handler
\r
75 IntDefaultHandler, // The usage fault handler
\r
80 IntDefaultHandler, // SVCall handler
\r
81 IntDefaultHandler, // Debug monitor handler
\r
83 xPortPendSVHandler, // The PendSV handler
\r
84 xPortSysTickHandler, // The SysTick handler
\r
85 IntDefaultHandler, // GPIO Port A
\r
86 IntDefaultHandler, // GPIO Port B
\r
87 IntDefaultHandler, // GPIO Port C
\r
88 IntDefaultHandler, // GPIO Port D
\r
89 IntDefaultHandler, // GPIO Port E
\r
90 IntDefaultHandler, // UART0 Rx and Tx
\r
91 IntDefaultHandler, // UART1 Rx and Tx
\r
92 IntDefaultHandler, // SSI Rx and Tx
\r
93 IntDefaultHandler, // I2C Master and Slave
\r
94 IntDefaultHandler, // PWM Fault
\r
95 IntDefaultHandler, // PWM Generator 0
\r
96 IntDefaultHandler, // PWM Generator 1
\r
97 IntDefaultHandler, // PWM Generator 2
\r
98 IntDefaultHandler, // Quadrature Encoder
\r
99 IntDefaultHandler, // ADC Sequence 0
\r
100 IntDefaultHandler, // ADC Sequence 1
\r
101 IntDefaultHandler, // ADC Sequence 2
\r
102 IntDefaultHandler, // ADC Sequence 3
\r
103 IntDefaultHandler, // Watchdog timer
\r
104 Timer0IntHandler, // Timer 0 subtimer A
\r
105 IntDefaultHandler, // Timer 0 subtimer B
\r
106 IntDefaultHandler, // Timer 1 subtimer A
\r
107 IntDefaultHandler, // Timer 1 subtimer B
\r
108 IntDefaultHandler, // Timer 2 subtimer A
\r
109 IntDefaultHandler, // Timer 2 subtimer B
\r
110 IntDefaultHandler, // Analog Comparator 0
\r
111 IntDefaultHandler, // Analog Comparator 1
\r
112 IntDefaultHandler, // Analog Comparator 2
\r
113 IntDefaultHandler, // System Control (PLL, OSC, BO)
\r
114 IntDefaultHandler, // FLASH Control
\r
115 IntDefaultHandler, // GPIO Port F
\r
116 IntDefaultHandler, // GPIO Port G
\r
117 IntDefaultHandler, // GPIO Port H
\r
118 IntDefaultHandler, // UART2 Rx and Tx
\r
119 IntDefaultHandler, // SSI1 Rx and Tx
\r
120 IntDefaultHandler, // Timer 3 subtimer A
\r
121 IntDefaultHandler, // Timer 3 subtimer B
\r
122 IntDefaultHandler, // I2C1 Master and Slave
\r
123 IntDefaultHandler, // Quadrature Encoder 1
\r
124 IntDefaultHandler, // CAN0
\r
125 IntDefaultHandler, // CAN1
\r
127 IntDefaultHandler, // Ethernet
\r
128 IntDefaultHandler // Hibernate
\r
131 //*****************************************************************************
\r
133 // The following are constructs created by the linker, indicating where the
\r
134 // the "data" and "bss" segments reside in memory. The initializers for the
\r
135 // for the "data" segment resides immediately following the "text" segment.
\r
137 //*****************************************************************************
\r
138 extern unsigned long _etext;
\r
139 extern unsigned long _data;
\r
140 extern unsigned long _edata;
\r
141 extern unsigned long _bss;
\r
142 extern unsigned long _ebss;
\r
144 //*****************************************************************************
\r
146 // This is the code that gets called when the processor first starts execution
\r
147 // following a reset event. Only the absolutely necessary set is performed,
\r
148 // after which the application supplied main() routine is called. Any fancy
\r
149 // actions (such as making decisions based on the reset cause register, and
\r
150 // resetting the bits in that register) are left solely in the hands of the
\r
153 //*****************************************************************************
\r
157 unsigned long *pulSrc, *pulDest;
\r
160 // Copy the data segment initializers from flash to SRAM.
\r
163 for(pulDest = &_data; pulDest < &_edata; )
\r
165 *pulDest++ = *pulSrc++;
\r
169 // Zero fill the bss segment.
\r
171 for(pulDest = &_bss; pulDest < &_ebss; )
\r
177 // Call the application's entry point.
\r
182 //*****************************************************************************
\r
184 // This is the code that gets called when the processor receives a NMI. This
\r
185 // simply enters an infinite loop, preserving the system state for examination
\r
188 //*****************************************************************************
\r
193 // Enter an infinite loop.
\r
200 //*****************************************************************************
\r
202 // This is the code that gets called when the processor receives a fault
\r
203 // interrupt. This simply enters an infinite loop, preserving the system state
\r
204 // for examination by a debugger.
\r
206 //*****************************************************************************
\r
211 // Enter an infinite loop.
\r
218 //*****************************************************************************
\r
220 // This is the code that gets called when the processor receives an unexpected
\r
221 // interrupt. This simply enters an infinite loop, preserving the system state
\r
222 // for examination by a debugger.
\r
224 //*****************************************************************************
\r
226 IntDefaultHandler(void)
\r
229 // Go into an infinite loop.
\r