1 //*****************************************************************************
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3 // hw_nvic.h - Macros used when accessing the NVIC hardware.
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5 // Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 1408 of the Stellaris Peripheral Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_NVIC_H__
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29 #define __HW_NVIC_H__
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31 //*****************************************************************************
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33 // The following define the addresses of the NVIC registers.
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35 //*****************************************************************************
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36 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.
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37 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.
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38 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
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39 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
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40 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.
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41 #define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register
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42 #define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register
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43 #define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.
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44 #define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg.
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45 #define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register
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46 #define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg.
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47 #define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.
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48 #define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg.
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49 #define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register
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50 #define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register
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51 #define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
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52 #define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register
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53 #define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register
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54 #define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register
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55 #define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register
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56 #define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register
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57 #define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register
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58 #define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register
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59 #define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register
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60 #define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register
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61 #define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register
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62 #define NVIC_CPUID 0xE000ED00 // CPUID Base Register
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63 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register
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64 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register
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65 #define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.
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66 #define NVIC_SYS_CTRL 0xE000ED10 // System Control Register
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67 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register
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68 #define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
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69 #define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
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70 #define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
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71 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
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72 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.
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73 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register
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74 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
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75 #define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register
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76 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register
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77 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register
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78 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register
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79 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register
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80 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register
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81 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.
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82 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.
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83 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
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84 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
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85 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
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86 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.
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88 //*****************************************************************************
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90 // The following define the bit fields in the NVIC_INT_TYPE register.
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92 //*****************************************************************************
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93 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
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94 #define NVIC_INT_TYPE_LINES_S 0
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96 //*****************************************************************************
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98 // The following define the bit fields in the NVIC_ST_CTRL register.
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100 //*****************************************************************************
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101 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag
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102 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
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103 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable
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104 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode
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106 //*****************************************************************************
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108 // The following define the bit fields in the NVIC_ST_RELOAD register.
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110 //*****************************************************************************
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111 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value
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112 #define NVIC_ST_RELOAD_S 0
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114 //*****************************************************************************
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116 // The following define the bit fields in the NVIC_ST_CURRENT register.
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118 //*****************************************************************************
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119 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value
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120 #define NVIC_ST_CURRENT_S 0
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122 //*****************************************************************************
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124 // The following define the bit fields in the NVIC_ST_CAL register.
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126 //*****************************************************************************
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127 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
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128 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
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129 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
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130 #define NVIC_ST_CAL_ONEMS_S 0
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132 //*****************************************************************************
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134 // The following define the bit fields in the NVIC_EN0 register.
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136 //*****************************************************************************
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137 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
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138 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
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139 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
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140 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
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141 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
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142 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
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143 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
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144 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
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145 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
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146 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
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147 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
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148 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
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149 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
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150 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
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151 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
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152 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
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153 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
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154 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
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155 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
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156 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
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157 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
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158 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
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159 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
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160 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
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161 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
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162 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
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163 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
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164 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
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165 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
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166 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
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167 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
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168 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
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170 //*****************************************************************************
\r
172 // The following define the bit fields in the NVIC_EN1 register.
\r
174 //*****************************************************************************
\r
175 #define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable
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176 #define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable
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177 #define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable
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178 #define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable
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179 #define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable
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180 #define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
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181 #define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
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182 #define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
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183 #define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
\r
184 #define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
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185 #define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
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186 #define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
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187 #define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
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188 #define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
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189 #define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
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190 #define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
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191 #define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
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192 #define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
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193 #define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
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194 #define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
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195 #define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
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196 #define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
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197 #define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
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198 #define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
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199 #define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
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200 #define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
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201 #define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
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202 #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
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204 //*****************************************************************************
\r
206 // The following define the bit fields in the NVIC_DIS0 register.
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208 //*****************************************************************************
\r
209 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
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210 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
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211 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
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212 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
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213 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
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214 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
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215 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
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216 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
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217 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
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218 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
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219 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
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220 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
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221 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
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222 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
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223 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
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224 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
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225 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
\r
226 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
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227 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
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228 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
\r
229 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
\r
230 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
\r
231 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
\r
232 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
\r
233 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
\r
234 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
\r
235 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
\r
236 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
\r
237 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
\r
238 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
\r
239 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
\r
240 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
\r
242 //*****************************************************************************
\r
244 // The following define the bit fields in the NVIC_DIS1 register.
\r
246 //*****************************************************************************
\r
247 #define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable
\r
248 #define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable
\r
249 #define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable
\r
250 #define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable
\r
251 #define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
\r
252 #define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
\r
253 #define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
\r
254 #define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
\r
255 #define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
\r
256 #define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
\r
257 #define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
\r
258 #define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
\r
259 #define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
\r
260 #define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
\r
261 #define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
\r
262 #define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
\r
263 #define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
\r
264 #define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
\r
265 #define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
\r
266 #define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
\r
267 #define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
\r
268 #define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
\r
269 #define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
\r
270 #define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
\r
271 #define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
\r
272 #define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
\r
273 #define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
\r
274 #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
\r
276 //*****************************************************************************
\r
278 // The following define the bit fields in the NVIC_PEND0 register.
\r
280 //*****************************************************************************
\r
281 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
\r
282 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
\r
283 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
\r
284 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
\r
285 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
\r
286 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
\r
287 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
\r
288 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
\r
289 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
\r
290 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
\r
291 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
\r
292 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
\r
293 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
\r
294 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
\r
295 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
\r
296 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
\r
297 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
\r
298 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
\r
299 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
\r
300 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
\r
301 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
\r
302 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
\r
303 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
\r
304 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
\r
305 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
\r
306 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
\r
307 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
\r
308 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
\r
309 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
\r
310 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
\r
311 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
\r
312 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
\r
314 //*****************************************************************************
\r
316 // The following define the bit fields in the NVIC_PEND1 register.
\r
318 //*****************************************************************************
\r
319 #define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend
\r
320 #define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend
\r
321 #define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend
\r
322 #define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend
\r
323 #define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
\r
324 #define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
\r
325 #define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
\r
326 #define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
\r
327 #define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
\r
328 #define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
\r
329 #define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
\r
330 #define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
\r
331 #define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
\r
332 #define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
\r
333 #define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
\r
334 #define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
\r
335 #define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
\r
336 #define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
\r
337 #define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
\r
338 #define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
\r
339 #define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
\r
340 #define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
\r
341 #define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
\r
342 #define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
\r
343 #define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
\r
344 #define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
\r
345 #define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
\r
346 #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
\r
348 //*****************************************************************************
\r
350 // The following define the bit fields in the NVIC_UNPEND0 register.
\r
352 //*****************************************************************************
\r
353 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
\r
354 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
\r
355 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
\r
356 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
\r
357 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
\r
358 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
\r
359 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
\r
360 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
\r
361 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
\r
362 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
\r
363 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
\r
364 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
\r
365 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
\r
366 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
\r
367 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
\r
368 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
\r
369 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
\r
370 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
\r
371 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
\r
372 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
\r
373 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
\r
374 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
\r
375 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
\r
376 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
\r
377 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
\r
378 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
\r
379 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
\r
380 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
\r
381 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
\r
382 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
\r
383 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
\r
384 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
\r
386 //*****************************************************************************
\r
388 // The following define the bit fields in the NVIC_UNPEND1 register.
\r
390 //*****************************************************************************
\r
391 #define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend
\r
392 #define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend
\r
393 #define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend
\r
394 #define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend
\r
395 #define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
\r
396 #define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
\r
397 #define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
\r
398 #define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
\r
399 #define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
\r
400 #define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
\r
401 #define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
\r
402 #define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
\r
403 #define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
\r
404 #define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
\r
405 #define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
\r
406 #define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
\r
407 #define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
\r
408 #define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
\r
409 #define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
\r
410 #define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
\r
411 #define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
\r
412 #define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
\r
413 #define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
\r
414 #define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
\r
415 #define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
\r
416 #define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
\r
417 #define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
\r
418 #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
\r
420 //*****************************************************************************
\r
422 // The following define the bit fields in the NVIC_ACTIVE0 register.
\r
424 //*****************************************************************************
\r
425 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
\r
426 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
\r
427 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
\r
428 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
\r
429 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
\r
430 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
\r
431 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
\r
432 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
\r
433 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
\r
434 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
\r
435 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
\r
436 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
\r
437 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
\r
438 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
\r
439 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
\r
440 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
\r
441 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
\r
442 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
\r
443 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
\r
444 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
\r
445 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
\r
446 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
\r
447 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
\r
448 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
\r
449 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
\r
450 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
\r
451 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
\r
452 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
\r
453 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
\r
454 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
\r
455 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
\r
456 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
\r
458 //*****************************************************************************
\r
460 // The following define the bit fields in the NVIC_ACTIVE1 register.
\r
462 //*****************************************************************************
\r
463 #define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active
\r
464 #define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active
\r
465 #define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active
\r
466 #define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active
\r
467 #define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
\r
468 #define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
\r
469 #define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
\r
470 #define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
\r
471 #define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
\r
472 #define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
\r
473 #define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
\r
474 #define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
\r
475 #define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
\r
476 #define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
\r
477 #define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
\r
478 #define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
\r
479 #define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
\r
480 #define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
\r
481 #define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
\r
482 #define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
\r
483 #define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
\r
484 #define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
\r
485 #define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
\r
486 #define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
\r
487 #define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
\r
488 #define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
\r
489 #define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
\r
490 #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
\r
492 //*****************************************************************************
\r
494 // The following define the bit fields in the NVIC_PRI0 register.
\r
496 //*****************************************************************************
\r
497 #define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask
\r
498 #define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask
\r
499 #define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask
\r
500 #define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask
\r
501 #define NVIC_PRI0_INT3_S 24
\r
502 #define NVIC_PRI0_INT2_S 16
\r
503 #define NVIC_PRI0_INT1_S 8
\r
504 #define NVIC_PRI0_INT0_S 0
\r
506 //*****************************************************************************
\r
508 // The following define the bit fields in the NVIC_PRI1 register.
\r
510 //*****************************************************************************
\r
511 #define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask
\r
512 #define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask
\r
513 #define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask
\r
514 #define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask
\r
515 #define NVIC_PRI1_INT7_S 24
\r
516 #define NVIC_PRI1_INT6_S 16
\r
517 #define NVIC_PRI1_INT5_S 8
\r
518 #define NVIC_PRI1_INT4_S 0
\r
520 //*****************************************************************************
\r
522 // The following define the bit fields in the NVIC_PRI2 register.
\r
524 //*****************************************************************************
\r
525 #define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask
\r
526 #define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask
\r
527 #define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask
\r
528 #define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask
\r
529 #define NVIC_PRI2_INT11_S 24
\r
530 #define NVIC_PRI2_INT10_S 16
\r
531 #define NVIC_PRI2_INT9_S 8
\r
532 #define NVIC_PRI2_INT8_S 0
\r
534 //*****************************************************************************
\r
536 // The following define the bit fields in the NVIC_PRI3 register.
\r
538 //*****************************************************************************
\r
539 #define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask
\r
540 #define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask
\r
541 #define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask
\r
542 #define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask
\r
543 #define NVIC_PRI3_INT15_S 24
\r
544 #define NVIC_PRI3_INT14_S 16
\r
545 #define NVIC_PRI3_INT13_S 8
\r
546 #define NVIC_PRI3_INT12_S 0
\r
548 //*****************************************************************************
\r
550 // The following define the bit fields in the NVIC_PRI4 register.
\r
552 //*****************************************************************************
\r
553 #define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask
\r
554 #define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask
\r
555 #define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask
\r
556 #define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask
\r
557 #define NVIC_PRI4_INT19_S 24
\r
558 #define NVIC_PRI4_INT18_S 16
\r
559 #define NVIC_PRI4_INT17_S 8
\r
560 #define NVIC_PRI4_INT16_S 0
\r
562 //*****************************************************************************
\r
564 // The following define the bit fields in the NVIC_PRI5 register.
\r
566 //*****************************************************************************
\r
567 #define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask
\r
568 #define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask
\r
569 #define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask
\r
570 #define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask
\r
571 #define NVIC_PRI5_INT23_S 24
\r
572 #define NVIC_PRI5_INT22_S 16
\r
573 #define NVIC_PRI5_INT21_S 8
\r
574 #define NVIC_PRI5_INT20_S 0
\r
576 //*****************************************************************************
\r
578 // The following define the bit fields in the NVIC_PRI6 register.
\r
580 //*****************************************************************************
\r
581 #define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask
\r
582 #define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask
\r
583 #define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask
\r
584 #define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask
\r
585 #define NVIC_PRI6_INT27_S 24
\r
586 #define NVIC_PRI6_INT26_S 16
\r
587 #define NVIC_PRI6_INT25_S 8
\r
588 #define NVIC_PRI6_INT24_S 0
\r
590 //*****************************************************************************
\r
592 // The following define the bit fields in the NVIC_PRI7 register.
\r
594 //*****************************************************************************
\r
595 #define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask
\r
596 #define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask
\r
597 #define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask
\r
598 #define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask
\r
599 #define NVIC_PRI7_INT31_S 24
\r
600 #define NVIC_PRI7_INT30_S 16
\r
601 #define NVIC_PRI7_INT29_S 8
\r
602 #define NVIC_PRI7_INT28_S 0
\r
604 //*****************************************************************************
\r
606 // The following define the bit fields in the NVIC_PRI8 register.
\r
608 //*****************************************************************************
\r
609 #define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask
\r
610 #define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask
\r
611 #define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask
\r
612 #define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask
\r
613 #define NVIC_PRI8_INT35_S 24
\r
614 #define NVIC_PRI8_INT34_S 16
\r
615 #define NVIC_PRI8_INT33_S 8
\r
616 #define NVIC_PRI8_INT32_S 0
\r
618 //*****************************************************************************
\r
620 // The following define the bit fields in the NVIC_PRI9 register.
\r
622 //*****************************************************************************
\r
623 #define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask
\r
624 #define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask
\r
625 #define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask
\r
626 #define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask
\r
627 #define NVIC_PRI9_INT39_S 24
\r
628 #define NVIC_PRI9_INT38_S 16
\r
629 #define NVIC_PRI9_INT37_S 8
\r
630 #define NVIC_PRI9_INT36_S 0
\r
632 //*****************************************************************************
\r
634 // The following define the bit fields in the NVIC_PRI10 register.
\r
636 //*****************************************************************************
\r
637 #define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask
\r
638 #define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask
\r
639 #define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask
\r
640 #define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask
\r
641 #define NVIC_PRI10_INT43_S 24
\r
642 #define NVIC_PRI10_INT42_S 16
\r
643 #define NVIC_PRI10_INT41_S 8
\r
644 #define NVIC_PRI10_INT40_S 0
\r
646 //*****************************************************************************
\r
648 // The following define the bit fields in the NVIC_CPUID register.
\r
650 //*****************************************************************************
\r
651 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer
\r
652 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant
\r
653 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number
\r
654 #define NVIC_CPUID_REV_M 0x0000000F // Revision
\r
656 //*****************************************************************************
\r
658 // The following define the bit fields in the NVIC_INT_CTRL register.
\r
660 //*****************************************************************************
\r
661 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI
\r
662 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV
\r
663 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV
\r
664 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling
\r
665 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending
\r
666 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception
\r
667 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base
\r
668 #define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception
\r
669 #define NVIC_INT_CTRL_VEC_PEN_S 12
\r
670 #define NVIC_INT_CTRL_VEC_ACT_S 0
\r
672 //*****************************************************************************
\r
674 // The following define the bit fields in the NVIC_VTABLE register.
\r
676 //*****************************************************************************
\r
677 #define NVIC_VTABLE_BASE 0x20000000 // Vector table base
\r
678 #define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset
\r
679 #define NVIC_VTABLE_OFFSET_S 8
\r
681 //*****************************************************************************
\r
683 // The following define the bit fields in the NVIC_APINT register.
\r
685 //*****************************************************************************
\r
686 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask
\r
687 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
\r
688 #define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess
\r
689 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group
\r
690 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
\r
691 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
\r
692 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
\r
693 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
\r
694 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
\r
695 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
\r
696 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
\r
697 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
\r
698 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request
\r
699 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info
\r
700 #define NVIC_APINT_VECT_RESET 0x00000001 // System reset
\r
702 //*****************************************************************************
\r
704 // The following define the bit fields in the NVIC_SYS_CTRL register.
\r
706 //*****************************************************************************
\r
707 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend
\r
708 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable
\r
709 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit
\r
711 //*****************************************************************************
\r
713 // The following define the bit fields in the NVIC_CFG_CTRL register.
\r
715 //*****************************************************************************
\r
716 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault
\r
717 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0
\r
718 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access
\r
719 #define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger
\r
720 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger
\r
721 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control
\r
723 //*****************************************************************************
\r
725 // The following define the bit fields in the NVIC_SYS_PRI1 register.
\r
727 //*****************************************************************************
\r
728 #define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler
\r
729 #define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler
\r
730 #define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler
\r
731 #define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler
\r
732 #define NVIC_SYS_PRI1_USAGE_S 16
\r
733 #define NVIC_SYS_PRI1_BUS_S 8
\r
734 #define NVIC_SYS_PRI1_MEM_S 0
\r
736 //*****************************************************************************
\r
738 // The following define the bit fields in the NVIC_SYS_PRI2 register.
\r
740 //*****************************************************************************
\r
741 #define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler
\r
742 #define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers
\r
743 #define NVIC_SYS_PRI2_SVC_S 24
\r
745 //*****************************************************************************
\r
747 // The following define the bit fields in the NVIC_SYS_PRI3 register.
\r
749 //*****************************************************************************
\r
750 #define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler
\r
751 #define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler
\r
752 #define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler
\r
753 #define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler
\r
754 #define NVIC_SYS_PRI3_TICK_S 24
\r
755 #define NVIC_SYS_PRI3_PENDSV_S 16
\r
756 #define NVIC_SYS_PRI3_DEBUG_S 0
\r
758 //*****************************************************************************
\r
760 // The following define the bit fields in the NVIC_SYS_HND_CTRL register.
\r
762 //*****************************************************************************
\r
763 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable
\r
764 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable
\r
765 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable
\r
766 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended
\r
767 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended
\r
768 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active
\r
769 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active
\r
770 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active
\r
771 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active
\r
772 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active
\r
773 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active
\r
774 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active
\r
776 //*****************************************************************************
\r
778 // The following define the bit fields in the NVIC_FAULT_STAT register.
\r
780 //*****************************************************************************
\r
781 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault
\r
782 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault
\r
783 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault
\r
784 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault
\r
785 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault
\r
786 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault
\r
787 #define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid
\r
788 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault
\r
789 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault
\r
790 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error
\r
791 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error
\r
792 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault
\r
793 #define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid
\r
794 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation
\r
795 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation
\r
796 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation
\r
797 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation
\r
799 //*****************************************************************************
\r
801 // The following define the bit fields in the NVIC_HFAULT_STAT register.
\r
803 //*****************************************************************************
\r
804 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event
\r
805 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler
\r
806 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault
\r
808 //*****************************************************************************
\r
810 // The following define the bit fields in the NVIC_DEBUG_STAT register.
\r
812 //*****************************************************************************
\r
813 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
\r
814 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
\r
815 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
\r
816 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
\r
817 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
\r
819 //*****************************************************************************
\r
821 // The following define the bit fields in the NVIC_MM_ADDR register.
\r
823 //*****************************************************************************
\r
824 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address
\r
825 #define NVIC_MM_ADDR_S 0
\r
827 //*****************************************************************************
\r
829 // The following define the bit fields in the NVIC_FAULT_ADDR register.
\r
831 //*****************************************************************************
\r
832 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address
\r
833 #define NVIC_FAULT_ADDR_S 0
\r
835 //*****************************************************************************
\r
837 // The following define the bit fields in the NVIC_EXC_STACK register.
\r
839 //*****************************************************************************
\r
840 #define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack
\r
842 //*****************************************************************************
\r
844 // The following define the bit fields in the NVIC_EXC_NUM register.
\r
846 //*****************************************************************************
\r
847 #define NVIC_EXC_NUM_M 0x000003FF // Exception number
\r
848 #define NVIC_EXC_NUM_S 0
\r
850 //*****************************************************************************
\r
852 // The following define the bit fields in the NVIC_COPRO register.
\r
854 //*****************************************************************************
\r
855 #define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask
\r
856 #define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied
\r
857 #define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess
\r
858 #define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access
\r
859 #define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask
\r
860 #define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied
\r
861 #define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess
\r
862 #define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access
\r
863 #define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask
\r
864 #define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied
\r
865 #define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess
\r
866 #define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access
\r
867 #define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask
\r
868 #define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied
\r
869 #define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess
\r
870 #define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access
\r
871 #define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask
\r
872 #define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied
\r
873 #define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess
\r
874 #define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access
\r
875 #define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask
\r
876 #define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied
\r
877 #define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess
\r
878 #define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access
\r
879 #define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask
\r
880 #define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied
\r
881 #define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess
\r
882 #define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access
\r
883 #define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask
\r
884 #define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied
\r
885 #define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess
\r
886 #define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access
\r
887 #define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask
\r
888 #define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied
\r
889 #define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess
\r
890 #define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access
\r
891 #define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask
\r
892 #define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied
\r
893 #define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess
\r
894 #define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access
\r
895 #define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask
\r
896 #define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied
\r
897 #define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess
\r
898 #define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access
\r
899 #define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask
\r
900 #define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied
\r
901 #define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess
\r
902 #define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access
\r
903 #define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask
\r
904 #define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied
\r
905 #define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess
\r
906 #define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access
\r
907 #define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask
\r
908 #define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied
\r
909 #define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess
\r
910 #define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access
\r
911 #define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask
\r
912 #define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied
\r
913 #define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess
\r
914 #define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access
\r
915 #define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask
\r
916 #define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied
\r
917 #define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess
\r
918 #define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access
\r
920 //*****************************************************************************
\r
922 // The following define the bit fields in the NVIC_MPU_TYPE register.
\r
924 //*****************************************************************************
\r
925 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions
\r
926 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions
\r
927 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU
\r
928 #define NVIC_MPU_TYPE_IREGION_S 16
\r
929 #define NVIC_MPU_TYPE_DREGION_S 8
\r
931 //*****************************************************************************
\r
933 // The following define the bit fields in the NVIC_MPU_CTRL register.
\r
935 //*****************************************************************************
\r
936 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults
\r
937 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable
\r
939 //*****************************************************************************
\r
941 // The following define the bit fields in the NVIC_MPU_NUMBER register.
\r
943 //*****************************************************************************
\r
944 #define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access
\r
945 #define NVIC_MPU_NUMBER_S 0
\r
947 //*****************************************************************************
\r
949 // The following define the bit fields in the NVIC_MPU_BASE register.
\r
951 //*****************************************************************************
\r
952 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address
\r
953 #define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid
\r
954 #define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number
\r
955 #define NVIC_MPU_BASE_ADDR_S 8
\r
956 #define NVIC_MPU_BASE_REGION_S 0
\r
958 //*****************************************************************************
\r
960 // The following define the bit fields in the NVIC_MPU_ATTR register.
\r
962 //*****************************************************************************
\r
963 #define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes
\r
964 #define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable
\r
965 #define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size
\r
967 //*****************************************************************************
\r
969 // The following define the bit fields in the NVIC_DBG_CTRL register.
\r
971 //*****************************************************************************
\r
972 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
\r
973 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
\r
974 #define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor
\r
975 #define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request
\r
976 #define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable
\r
977 #define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core
\r
978 #define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping
\r
979 #define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt
\r
980 #define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available
\r
981 #define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up
\r
982 #define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core
\r
983 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
\r
984 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
\r
985 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
\r
986 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
\r
988 //*****************************************************************************
\r
990 // The following define the bit fields in the NVIC_DBG_XFER register.
\r
992 //*****************************************************************************
\r
993 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
\r
994 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
\r
995 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
\r
996 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
\r
997 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
\r
998 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
\r
999 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
\r
1000 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
\r
1001 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
\r
1002 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
\r
1003 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
\r
1004 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
\r
1005 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
\r
1006 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
\r
1007 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
\r
1008 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
\r
1009 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
\r
1010 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
\r
1011 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
\r
1012 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
\r
1013 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
\r
1014 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
\r
1015 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
\r
1017 //*****************************************************************************
\r
1019 // The following define the bit fields in the NVIC_DBG_DATA register.
\r
1021 //*****************************************************************************
\r
1022 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
\r
1023 #define NVIC_DBG_DATA_S 0
\r
1025 //*****************************************************************************
\r
1027 // The following define the bit fields in the NVIC_DBG_INT register.
\r
1029 //*****************************************************************************
\r
1030 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
\r
1031 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
\r
1032 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
\r
1033 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
\r
1034 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
\r
1035 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
\r
1036 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
\r
1037 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
\r
1038 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
\r
1039 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
\r
1040 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
\r
1042 //*****************************************************************************
\r
1044 // The following define the bit fields in the NVIC_SW_TRIG register.
\r
1046 //*****************************************************************************
\r
1047 #define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger
\r
1048 #define NVIC_SW_TRIG_INTID_S 0
\r
1050 #endif // __HW_NVIC_H__
\r