1 //*****************************************************************************
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3 // hw_can.h - Defines and macros used when accessing the can.
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5 // Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 1408 of the Stellaris Peripheral Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_CAN_H__
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29 #define __HW_CAN_H__
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31 //*****************************************************************************
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33 // The following define the offsets of the can registers.
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35 //*****************************************************************************
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36 #define CAN_O_CTL 0x00000000 // Control register
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37 #define CAN_O_STS 0x00000004 // Status register
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38 #define CAN_O_ERR 0x00000008 // Error register
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39 #define CAN_O_BIT 0x0000000C // Bit Timing register
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40 #define CAN_O_INT 0x00000010 // Interrupt register
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41 #define CAN_O_TST 0x00000014 // Test register
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42 #define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
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43 #define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
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44 #define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
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45 #define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
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46 #define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
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47 #define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
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48 #define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
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49 #define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
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50 #define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
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51 #define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
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52 #define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
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53 #define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
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54 #define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
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55 #define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
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56 #define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
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57 #define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
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58 #define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
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59 #define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
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60 #define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
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61 #define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
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62 #define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
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63 #define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
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64 #define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
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65 #define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
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66 #define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
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67 #define CAN_O_NWDA1 0x00000120 // New Data 1 register
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68 #define CAN_O_NWDA2 0x00000124 // New Data 2 register
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69 #define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
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70 #define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
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71 #define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
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72 #define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
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74 //*****************************************************************************
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76 // The following define the reset values of the can registers.
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78 //*****************************************************************************
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79 #define CAN_RV_CTL 0x00000001
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80 #define CAN_RV_STS 0x00000000
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81 #define CAN_RV_ERR 0x00000000
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82 #define CAN_RV_BIT 0x00002301
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83 #define CAN_RV_INT 0x00000000
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84 #define CAN_RV_TST 0x00000000
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85 #define CAN_RV_BRPE 0x00000000
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86 #define CAN_RV_IF1CRQ 0x00000001
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87 #define CAN_RV_IF1CMSK 0x00000000
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88 #define CAN_RV_IF1MSK1 0x0000FFFF
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89 #define CAN_RV_IF1MSK2 0x0000FFFF
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90 #define CAN_RV_IF1ARB1 0x00000000
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91 #define CAN_RV_IF1ARB2 0x00000000
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92 #define CAN_RV_IF1MCTL 0x00000000
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93 #define CAN_RV_IF1DA1 0x00000000
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94 #define CAN_RV_IF1DA2 0x00000000
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95 #define CAN_RV_IF1DB1 0x00000000
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96 #define CAN_RV_IF1DB2 0x00000000
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97 #define CAN_RV_IF2CRQ 0x00000001
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98 #define CAN_RV_IF2CMSK 0x00000000
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99 #define CAN_RV_IF2MSK1 0x0000FFFF
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100 #define CAN_RV_IF2MSK2 0x0000FFFF
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101 #define CAN_RV_IF2ARB1 0x00000000
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102 #define CAN_RV_IF2ARB2 0x00000000
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103 #define CAN_RV_IF2MCTL 0x00000000
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104 #define CAN_RV_IF2DA1 0x00000000
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105 #define CAN_RV_IF2DA2 0x00000000
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106 #define CAN_RV_IF2DB1 0x00000000
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107 #define CAN_RV_IF2DB2 0x00000000
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108 #define CAN_RV_TXRQ1 0x00000000
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109 #define CAN_RV_TXRQ2 0x00000000
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110 #define CAN_RV_NWDA1 0x00000000
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111 #define CAN_RV_NWDA2 0x00000000
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112 #define CAN_RV_MSGINT1 0x00000000
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113 #define CAN_RV_MSGINT2 0x00000000
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114 #define CAN_RV_MSGVAL1 0x00000000
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115 #define CAN_RV_MSGVAL2 0x00000000
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117 //*****************************************************************************
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119 // The following define the bit fields in the CAN_CTL register.
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121 //*****************************************************************************
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122 #define CAN_CTL_TEST 0x00000080 // Test mode enable
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123 #define CAN_CTL_CCE 0x00000040 // Configuration change enable
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124 #define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
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125 #define CAN_CTL_EIE 0x00000008 // Error interrupt enable
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126 #define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
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127 #define CAN_CTL_IE 0x00000002 // Module interrupt enable
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128 #define CAN_CTL_INIT 0x00000001 // Initialization
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130 //*****************************************************************************
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132 // The following define the bit fields in the CAN_STS register.
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134 //*****************************************************************************
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135 #define CAN_STS_BOFF 0x00000080 // Bus Off status
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136 #define CAN_STS_EWARN 0x00000040 // Error Warning status
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137 #define CAN_STS_EPASS 0x00000020 // Error Passive status
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138 #define CAN_STS_RXOK 0x00000010 // Received Message Successful
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139 #define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
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140 #define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
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141 #define CAN_STS_LEC_NONE 0x00000000 // No error
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142 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
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143 #define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
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144 #define CAN_STS_LEC_ACK 0x00000003 // Ack error
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145 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
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146 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
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147 #define CAN_STS_LEC_CRC 0x00000006 // CRC error
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149 //*****************************************************************************
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151 // The following define the bit fields in the CAN_ERR register.
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153 //*****************************************************************************
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154 #define CAN_ERR_RP 0x00008000 // Receive error passive status
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155 #define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
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156 #define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
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157 #define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
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158 #define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
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160 //*****************************************************************************
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162 // The following define the bit fields in the CAN_BIT register.
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164 //*****************************************************************************
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165 #define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
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166 #define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
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167 #define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
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168 #define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
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170 //*****************************************************************************
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172 // The following define the bit fields in the CAN_INT register.
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174 //*****************************************************************************
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175 #define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
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176 #define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
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177 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
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179 //*****************************************************************************
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181 // The following define the bit fields in the CAN_TST register.
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183 //*****************************************************************************
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184 #define CAN_TST_RX 0x00000080 // CAN_RX pin status
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185 #define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
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186 #define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
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187 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
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188 #define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
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189 #define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
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190 #define CAN_TST_LBACK 0x00000010 // Loop back mode
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191 #define CAN_TST_SILENT 0x00000008 // Silent mode
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192 #define CAN_TST_BASIC 0x00000004 // Basic mode
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194 //*****************************************************************************
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196 // The following define the bit fields in the CAN_BRPE register.
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198 //*****************************************************************************
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199 #define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
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201 //*****************************************************************************
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203 // The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ
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205 // Note: All bits may not be available in all registers
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207 //*****************************************************************************
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208 #define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
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209 #define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
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211 //*****************************************************************************
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213 // The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK
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215 // Note: All bits may not be available in all registers
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217 //*****************************************************************************
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218 #define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
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219 #define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
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220 #define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
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221 #define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
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222 #define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
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223 #define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
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224 #define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
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225 #define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
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226 #define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
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228 //*****************************************************************************
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230 // The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1
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232 // Note: All bits may not be available in all registers
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234 //*****************************************************************************
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235 #define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
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237 //*****************************************************************************
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239 // The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2
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241 // Note: All bits may not be available in all registers
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243 //*****************************************************************************
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244 #define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
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245 #define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
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246 #define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
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248 //*****************************************************************************
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250 // The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1
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252 // Note: All bits may not be available in all registers
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254 //*****************************************************************************
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255 #define CAN_IFARB1_ID 0x0000FFFF // Identifier
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257 //*****************************************************************************
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259 // The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2
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261 // Note: All bits may not be available in all registers
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263 //*****************************************************************************
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264 #define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
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265 #define CAN_IFARB2_XTD 0x00004000 // Extended identifier
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266 #define CAN_IFARB2_DIR 0x00002000 // Message direction
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267 #define CAN_IFARB2_ID 0x00001FFF // Message identifier
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269 //*****************************************************************************
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271 // The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL
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273 // Note: All bits may not be available in all registers
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275 //*****************************************************************************
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276 #define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
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277 #define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
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278 #define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
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279 #define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
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280 #define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
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281 #define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
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282 #define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
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283 #define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
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284 #define CAN_IFMCTL_EOB 0x00000080 // End of buffer
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285 #define CAN_IFMCTL_DLC 0x0000000F // Data length code
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287 //*****************************************************************************
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289 // The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1
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291 // Note: All bits may not be available in all registers
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293 //*****************************************************************************
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294 #define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
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296 //*****************************************************************************
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298 // The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2
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300 // Note: All bits may not be available in all registers
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302 //*****************************************************************************
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303 #define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
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305 //*****************************************************************************
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307 // The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1
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309 // Note: All bits may not be available in all registers
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311 //*****************************************************************************
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312 #define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
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314 //*****************************************************************************
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316 // The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2
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318 // Note: All bits may not be available in all registers
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320 //*****************************************************************************
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321 #define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
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323 //*****************************************************************************
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325 // The following define the bit fields in the CAN_TXRQ1 register.
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327 //*****************************************************************************
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328 #define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
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330 //*****************************************************************************
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332 // The following define the bit fields in the CAN_TXRQ2 register.
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334 //*****************************************************************************
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335 #define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
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337 //*****************************************************************************
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339 // The following define the bit fields in the CAN_NWDA1 register.
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341 //*****************************************************************************
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342 #define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
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344 //*****************************************************************************
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346 // The following define the bit fields in the CAN_NWDA2 register.
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348 //*****************************************************************************
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349 #define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
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351 //*****************************************************************************
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353 // The following define the bit fields in the CAN_MSGINT1 register.
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355 //*****************************************************************************
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356 #define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
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358 //*****************************************************************************
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360 // The following define the bit fields in the CAN_MSGINT2 register.
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362 //*****************************************************************************
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363 #define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
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365 //*****************************************************************************
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367 // The following define the bit fields in the CAN_MSGVAL1 register.
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369 //*****************************************************************************
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370 #define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
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372 //*****************************************************************************
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374 // The following define the bit fields in the CAN_MSGVAL2 register.
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376 //*****************************************************************************
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377 #define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
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379 #endif // __HW_CAN_H__
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