1 //*****************************************************************************
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3 // startup.c - Boot code for Stellaris.
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5 // Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 1392 of the Stellaris Peripheral Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 // Forward declaration of the default fault handlers.
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32 //*****************************************************************************
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33 void ResetISR(void);
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34 static void NmiSR(void);
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35 static void FaultISR(void);
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36 static void IntDefaultHandler(void);
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38 //*****************************************************************************
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40 // The entry point for the application.
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42 //*****************************************************************************
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43 extern int main(void);
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44 extern void xPortPendSVHandler(void);
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45 extern void xPortSysTickHandler(void);
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46 extern void vEMAC_ISR(void);
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47 extern void Timer0IntHandler(void);
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49 //*****************************************************************************
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51 // Reserve space for the system stack.
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53 //*****************************************************************************
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55 #define STACK_SIZE 64
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57 static unsigned long pulStack[STACK_SIZE];
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59 //*****************************************************************************
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61 // The minimal vector table for a Cortex M3. Note that the proper constructs
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62 // must be placed on this to ensure that it ends up at physical address
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65 //*****************************************************************************
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66 __attribute__ ((section(".isr_vector")))
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67 void (* const g_pfnVectors[])(void) =
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69 (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
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70 // The initial stack pointer
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71 ResetISR, // The reset handler
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72 NmiSR, // The NMI handler
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73 FaultISR, // The hard fault handler
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74 IntDefaultHandler, // The MPU fault handler
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75 IntDefaultHandler, // The bus fault handler
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76 IntDefaultHandler, // The usage fault handler
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81 IntDefaultHandler, // SVCall handler
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82 IntDefaultHandler, // Debug monitor handler
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84 xPortPendSVHandler, // The PendSV handler
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85 xPortSysTickHandler, // The SysTick handler
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86 IntDefaultHandler, // GPIO Port A
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87 IntDefaultHandler, // GPIO Port B
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88 IntDefaultHandler, // GPIO Port C
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89 IntDefaultHandler, // GPIO Port D
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90 IntDefaultHandler, // GPIO Port E
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91 IntDefaultHandler, // UART0 Rx and Tx
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92 IntDefaultHandler, // UART1 Rx and Tx
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93 IntDefaultHandler, // SSI Rx and Tx
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94 IntDefaultHandler, // I2C Master and Slave
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95 IntDefaultHandler, // PWM Fault
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96 IntDefaultHandler, // PWM Generator 0
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97 IntDefaultHandler, // PWM Generator 1
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98 IntDefaultHandler, // PWM Generator 2
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99 IntDefaultHandler, // Quadrature Encoder
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100 IntDefaultHandler, // ADC Sequence 0
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101 IntDefaultHandler, // ADC Sequence 1
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102 IntDefaultHandler, // ADC Sequence 2
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103 IntDefaultHandler, // ADC Sequence 3
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104 IntDefaultHandler, // Watchdog timer
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105 Timer0IntHandler, // Timer 0 subtimer A
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106 IntDefaultHandler, // Timer 0 subtimer B
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107 IntDefaultHandler, // Timer 1 subtimer A
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108 IntDefaultHandler, // Timer 1 subtimer B
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109 IntDefaultHandler, // Timer 2 subtimer A
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110 IntDefaultHandler, // Timer 2 subtimer B
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111 IntDefaultHandler, // Analog Comparator 0
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112 IntDefaultHandler, // Analog Comparator 1
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113 IntDefaultHandler, // Analog Comparator 2
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114 IntDefaultHandler, // System Control (PLL, OSC, BO)
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115 IntDefaultHandler, // FLASH Control
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116 IntDefaultHandler, // GPIO Port F
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117 IntDefaultHandler, // GPIO Port G
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118 IntDefaultHandler, // GPIO Port H
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119 IntDefaultHandler, // UART2 Rx and Tx
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120 IntDefaultHandler, // SSI1 Rx and Tx
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121 IntDefaultHandler, // Timer 3 subtimer A
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122 IntDefaultHandler, // Timer 3 subtimer B
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123 IntDefaultHandler, // I2C1 Master and Slave
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124 IntDefaultHandler, // Quadrature Encoder 1
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125 IntDefaultHandler, // CAN0
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126 IntDefaultHandler, // CAN1
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128 vEMAC_ISR, // Ethernet
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129 IntDefaultHandler // Hibernate
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132 //*****************************************************************************
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134 // The following are constructs created by the linker, indicating where the
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135 // the "data" and "bss" segments reside in memory. The initializers for the
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136 // for the "data" segment resides immediately following the "text" segment.
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138 //*****************************************************************************
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139 extern unsigned long _etext;
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140 extern unsigned long _data;
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141 extern unsigned long _edata;
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142 extern unsigned long _bss;
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143 extern unsigned long _ebss;
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145 //*****************************************************************************
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147 // This is the code that gets called when the processor first starts execution
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148 // following a reset event. Only the absolutely necessary set is performed,
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149 // after which the application supplied main() routine is called. Any fancy
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150 // actions (such as making decisions based on the reset cause register, and
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151 // resetting the bits in that register) are left solely in the hands of the
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154 //*****************************************************************************
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158 unsigned long *pulSrc, *pulDest;
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161 // Copy the data segment initializers from flash to SRAM.
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164 for(pulDest = &_data; pulDest < &_edata; )
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166 *pulDest++ = *pulSrc++;
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170 // Zero fill the bss segment.
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172 for(pulDest = &_bss; pulDest < &_ebss; )
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178 // Call the application's entry point.
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183 //*****************************************************************************
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185 // This is the code that gets called when the processor receives a NMI. This
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186 // simply enters an infinite loop, preserving the system state for examination
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189 //*****************************************************************************
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194 // Enter an infinite loop.
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201 //*****************************************************************************
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203 // This is the code that gets called when the processor receives a fault
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204 // interrupt. This simply enters an infinite loop, preserving the system state
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205 // for examination by a debugger.
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207 //*****************************************************************************
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212 // Enter an infinite loop.
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219 //*****************************************************************************
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221 // This is the code that gets called when the processor receives an unexpected
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222 // interrupt. This simply enters an infinite loop, preserving the system state
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223 // for examination by a debugger.
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225 //*****************************************************************************
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227 IntDefaultHandler(void)
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230 // Go into an infinite loop.
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237 //*****************************************************************************
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239 // A dummy printf function to satisfy the calls to printf from uip. This
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240 // avoids pulling in the run-time library.
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242 //*****************************************************************************
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244 uipprintf(const char *fmt, ...)
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