1 //*****************************************************************************
\r
3 // hw_sysctl.h - Macros used when accessing the system control hardware.
\r
5 // Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
\r
7 // Software License Agreement
\r
9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
\r
10 // exclusively on LMI's microcontroller products.
\r
12 // The software is owned by LMI and/or its suppliers, and is protected under
\r
13 // applicable copyright laws. All rights are reserved. Any use in violation
\r
14 // of the foregoing restrictions may subject the user to criminal sanctions
\r
15 // under applicable laws, as well as to civil liability for the breach of the
\r
16 // terms and conditions of this license.
\r
18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
24 // This is part of revision 1408 of the Stellaris Peripheral Driver Library.
\r
26 //*****************************************************************************
\r
28 #ifndef __HW_SYSCTL_H__
\r
29 #define __HW_SYSCTL_H__
\r
31 //*****************************************************************************
\r
33 // The following define the addresses of the system control registers.
\r
35 //*****************************************************************************
\r
36 #define SYSCTL_DID0 0x400fe000 // Device identification register 0
\r
37 #define SYSCTL_DID1 0x400fe004 // Device identification register 1
\r
38 #define SYSCTL_DC0 0x400fe008 // Device capabilities register 0
\r
39 #define SYSCTL_DC1 0x400fe010 // Device capabilities register 1
\r
40 #define SYSCTL_DC2 0x400fe014 // Device capabilities register 2
\r
41 #define SYSCTL_DC3 0x400fe018 // Device capabilities register 3
\r
42 #define SYSCTL_DC4 0x400fe01C // Device capabilities register 4
\r
43 #define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register
\r
44 #define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register
\r
45 #define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0
\r
46 #define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1
\r
47 #define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2
\r
48 #define SYSCTL_RIS 0x400fe050 // Raw interrupt status register
\r
49 #define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register
\r
50 #define SYSCTL_MISC 0x400fe058 // Interrupt status register
\r
51 #define SYSCTL_RESC 0x400fe05c // Reset cause register
\r
52 #define SYSCTL_RCC 0x400fe060 // Run-mode clock config register
\r
53 #define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register
\r
54 #define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2
\r
55 #define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0
\r
56 #define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1
\r
57 #define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2
\r
58 #define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0
\r
59 #define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1
\r
60 #define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2
\r
61 #define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0
\r
62 #define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1
\r
63 #define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2
\r
64 #define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg
\r
65 #define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register
\r
66 #define SYSCTL_LDOARST 0x400fe160 // LDO reset control register
\r
67 #define SYSCTL_USER0 0x400fe1e0 // NV User Register 0
\r
68 #define SYSCTL_USER1 0x400fe1e4 // NV User Register 1
\r
70 //*****************************************************************************
\r
72 // The following define the bit fields in the SYSCTL_DID0 register.
\r
74 //*****************************************************************************
\r
75 #define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
\r
76 #define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0
\r
77 #define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1
\r
78 #define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
\r
79 #define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // LM3Snnn Sandstorm Device
\r
80 #define SYSCTL_DID0_CLASS_FURY 0x00010000 // LM3Snnnn Fury Device
\r
81 #define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
\r
82 #define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
\r
83 #define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
\r
84 #define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
\r
85 #define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
\r
86 #define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0
\r
87 #define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1
\r
88 #define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2
\r
89 #define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
\r
90 #define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
\r
91 #define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
\r
93 //*****************************************************************************
\r
95 // The following define the bit fields in the SYSCTL_DID1 register.
\r
97 //*****************************************************************************
\r
98 #define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
\r
99 #define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
\r
100 #define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
\r
101 #define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
\r
102 #define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
\r
103 #define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
\r
104 #define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
\r
105 #define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
\r
106 #define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
\r
107 #define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
\r
108 #define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
\r
109 #define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
\r
110 #define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
\r
111 #define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
\r
112 #define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
\r
113 #define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
\r
114 #define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
\r
115 #define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
\r
116 #define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
\r
117 #define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
\r
118 #define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
\r
119 #define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
\r
120 #define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
\r
121 #define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
\r
122 #define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
\r
123 #define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
\r
124 #define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
\r
125 #define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
\r
126 #define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
\r
127 #define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
\r
128 #define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
\r
129 #define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
\r
130 #define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
\r
131 #define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
\r
132 #define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
\r
133 #define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
\r
134 #define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
\r
135 #define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
\r
136 #define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
\r
137 #define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
\r
138 #define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
\r
139 #define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
\r
140 #define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
\r
141 #define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
\r
142 #define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
\r
143 #define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
\r
144 #define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
\r
145 #define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
\r
146 #define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
\r
147 #define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
\r
148 #define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
\r
149 #define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
\r
150 #define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
\r
151 #define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
\r
152 #define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
\r
153 #define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
\r
154 #define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package
\r
155 #define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
\r
156 #define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)
\r
157 #define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)
\r
158 #define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
\r
159 #define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC
\r
160 #define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP
\r
161 #define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant
\r
162 #define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
\r
163 #define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)
\r
164 #define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)
\r
165 #define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified
\r
166 #define SYSCTL_DID1_PRTNO_SHIFT 16
\r
168 //*****************************************************************************
\r
170 // The following define the bit fields in the SYSCTL_DC0 register.
\r
172 //*****************************************************************************
\r
173 #define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
\r
174 #define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
\r
175 #define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
\r
176 #define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
\r
177 #define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
\r
178 #define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
\r
179 #define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
\r
180 #define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
\r
181 #define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash
\r
182 #define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash
\r
183 #define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash
\r
184 #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash
\r
185 #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash
\r
186 #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash
\r
187 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash
\r
189 //*****************************************************************************
\r
191 // The following define the bit fields in the SYSCTL_DC1 register.
\r
193 //*****************************************************************************
\r
194 #define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present
\r
195 #define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present
\r
196 #define SYSCTL_DC1_PWM 0x00100000 // PWM module present
\r
197 #define SYSCTL_DC1_ADC 0x00010000 // ADC module present
\r
198 #define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
\r
199 #define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
\r
200 #define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC
\r
201 #define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC
\r
202 #define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC
\r
203 #define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
\r
204 #define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present
\r
205 #define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present
\r
206 #define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present
\r
207 #define SYSCTL_DC1_PLL 0x00000010 // PLL present
\r
208 #define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
\r
209 #define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present
\r
210 #define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present
\r
211 #define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present
\r
213 //*****************************************************************************
\r
215 // The following define the bit fields in the SYSCTL_DC2 register.
\r
217 //*****************************************************************************
\r
218 #define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present
\r
219 #define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present
\r
220 #define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present
\r
221 #define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present
\r
222 #define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present
\r
223 #define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present
\r
224 #define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present
\r
225 #define SYSCTL_DC2_I2C1 0x00002000 // I2C 1 present
\r
226 #define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present
\r
228 #define SYSCTL_DC2_I2C 0x00001000 // I2C present
\r
230 #define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present
\r
231 #define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present
\r
233 #define SYSCTL_DC2_QEI 0x00000100 // QEI present
\r
235 #define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present
\r
236 #define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present
\r
238 #define SYSCTL_DC2_SSI 0x00000010 // SSI present
\r
240 #define SYSCTL_DC2_UART2 0x00000004 // UART 2 present
\r
241 #define SYSCTL_DC2_UART1 0x00000002 // UART 1 present
\r
242 #define SYSCTL_DC2_UART0 0x00000001 // UART 0 present
\r
244 //*****************************************************************************
\r
246 // The following define the bit fields in the SYSCTL_DC3 register.
\r
248 //*****************************************************************************
\r
249 #define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present
\r
250 #define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present
\r
251 #define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present
\r
252 #define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present
\r
253 #define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present
\r
254 #define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present
\r
255 #define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present
\r
256 #define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present
\r
257 #define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present
\r
258 #define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present
\r
259 #define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present
\r
260 #define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present
\r
261 #define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present
\r
262 #define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present
\r
263 #define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present
\r
264 #define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
\r
265 #define SYSCTL_DC3_C2O 0x00004000 // C2o pin present
\r
266 #define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present
\r
267 #define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present
\r
268 #define SYSCTL_DC3_C1O 0x00000800 // C1o pin present
\r
269 #define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present
\r
270 #define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present
\r
271 #define SYSCTL_DC3_C0O 0x00000100 // C0o pin present
\r
272 #define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present
\r
273 #define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present
\r
274 #define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present
\r
275 #define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present
\r
276 #define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present
\r
277 #define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present
\r
278 #define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present
\r
279 #define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present
\r
281 //*****************************************************************************
\r
283 // The following define the bit fields in the SYSCTL_DC4 register.
\r
285 //*****************************************************************************
\r
286 #define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
\r
287 #define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present
\r
288 #define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present
\r
289 #define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present
\r
290 #define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present
\r
291 #define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present
\r
292 #define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present
\r
293 #define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present
\r
294 #define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present
\r
296 //*****************************************************************************
\r
298 // The following define the bit fields in the SYSCTL_PBORCTL register.
\r
300 //*****************************************************************************
\r
301 #define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
\r
302 #define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset
\r
303 #define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise
\r
304 #define SYSCTL_PBORCTL_BOR_SH 2
\r
306 //*****************************************************************************
\r
308 // The following define the bit fields in the SYSCTL_LDOPCTL register.
\r
310 //*****************************************************************************
\r
311 #define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
\r
312 #define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V
\r
313 #define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V
\r
314 #define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V
\r
315 #define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V
\r
316 #define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V
\r
317 #define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V
\r
318 #define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V
\r
319 #define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V
\r
320 #define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V
\r
321 #define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V
\r
322 #define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V
\r
324 //*****************************************************************************
\r
326 // The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,
\r
327 // SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
\r
329 //*****************************************************************************
\r
330 #define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module
\r
331 #define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module
\r
332 #define SYSCTL_SET0_PWM 0x00100000 // PWM module
\r
333 #define SYSCTL_SET0_ADC 0x00010000 // ADC module
\r
334 #define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
\r
335 #define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
\r
336 #define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
\r
337 #define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
\r
338 #define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
\r
339 #define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
\r
340 #define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
\r
342 //*****************************************************************************
\r
344 // The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,
\r
345 // SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
\r
347 //*****************************************************************************
\r
348 #define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
\r
349 #define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
\r
350 #define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
\r
351 #define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
\r
352 #define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
\r
353 #define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
\r
354 #define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
\r
355 #define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1
\r
356 #define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
\r
358 #define SYSCTL_SET1_I2C 0x00001000 // I2C module
\r
360 #define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
\r
361 #define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
\r
363 #define SYSCTL_SET1_QEI 0x00000100 // QEI module
\r
365 #define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
\r
366 #define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
\r
368 #define SYSCTL_SET1_SSI 0x00000010 // SSI module
\r
370 #define SYSCTL_SET1_UART2 0x00000004 // UART module 2
\r
371 #define SYSCTL_SET1_UART1 0x00000002 // UART module 1
\r
372 #define SYSCTL_SET1_UART0 0x00000001 // UART module 0
\r
374 //*****************************************************************************
\r
376 // The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,
\r
377 // SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
\r
379 //*****************************************************************************
\r
380 #define SYSCTL_SET2_ETH 0x50000000 // ETH module
\r
381 #define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
\r
382 #define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
\r
383 #define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
\r
384 #define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
\r
385 #define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
\r
386 #define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
\r
387 #define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
\r
388 #define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
\r
390 //*****************************************************************************
\r
392 // The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and
\r
393 // SYSCTL_IMS registers.
\r
395 //*****************************************************************************
\r
396 #define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
\r
397 #define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
\r
398 #define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
\r
399 #define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
\r
400 #define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
\r
401 #define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
\r
402 #define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
\r
404 //*****************************************************************************
\r
406 // The following define the bit fields in the SYSCTL_RESC register.
\r
408 //*****************************************************************************
\r
409 #define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset
\r
410 #define SYSCTL_RESC_SW 0x00000010 // Software reset
\r
411 #define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
\r
412 #define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset
\r
413 #define SYSCTL_RESC_POR 0x00000002 // Power on reset
\r
414 #define SYSCTL_RESC_EXT 0x00000001 // External reset
\r
416 //*****************************************************************************
\r
418 // The following define the bit fields in the SYSCTL_RCC register.
\r
420 //*****************************************************************************
\r
421 #define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating
\r
422 #define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
\r
423 #define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
\r
424 #define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
\r
425 #define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
\r
426 #define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
\r
427 #define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
\r
428 #define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
\r
429 #define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
\r
430 #define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
\r
431 #define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
\r
432 #define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
\r
433 #define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
\r
434 #define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
\r
435 #define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
\r
436 #define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
\r
437 #define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
\r
438 #define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
\r
439 #define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
\r
440 #define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
\r
441 #define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
\r
442 #define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
\r
443 #define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
\r
444 #define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
\r
445 #define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
\r
446 #define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
\r
447 #define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down
\r
448 #define SYSCTL_RCC_OE 0x00001000 // PLL output enable
\r
449 #define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass
\r
450 #define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable
\r
451 #define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
\r
452 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal
\r
453 #define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal
\r
454 #define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal
\r
455 #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal
\r
456 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal
\r
457 #define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal
\r
458 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal
\r
459 #define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal
\r
460 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal
\r
461 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal
\r
462 #define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal
\r
463 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal
\r
464 #define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
\r
465 #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator
\r
466 #define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator
\r
467 #define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4
\r
468 #define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en
\r
469 #define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en
\r
470 #define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable
\r
471 #define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable
\r
472 #define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
\r
473 #define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
\r
474 #define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
\r
475 #define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
\r
477 //*****************************************************************************
\r
479 // The following define the bit fields in the SYSCTL_PLLCFG register.
\r
481 //*****************************************************************************
\r
482 #define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
\r
483 #define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1
\r
484 #define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2
\r
485 #define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4
\r
486 #define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
\r
487 #define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
\r
488 #define SYSCTL_PLLCFG_F_SHIFT 5
\r
489 #define SYSCTL_PLLCFG_R_SHIFT 0
\r
491 //*****************************************************************************
\r
493 // The following define the bit fields in the SYSCTL_RCC2 register.
\r
495 //*****************************************************************************
\r
496 #define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
\r
497 #define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
\r
498 #define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
\r
499 #define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
\r
500 #define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
\r
501 #define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
\r
502 #define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
\r
503 #define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
\r
504 #define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
\r
505 #define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
\r
506 #define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
\r
507 #define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
\r
508 #define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
\r
509 #define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
\r
510 #define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
\r
511 #define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
\r
512 #define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
\r
513 #define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
\r
514 #define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
\r
515 #define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
\r
516 #define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
\r
517 #define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
\r
518 #define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
\r
519 #define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
\r
520 #define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
\r
521 #define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
\r
522 #define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
\r
523 #define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
\r
524 #define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
\r
525 #define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
\r
526 #define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
\r
527 #define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
\r
528 #define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
\r
529 #define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
\r
530 #define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
\r
531 #define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
\r
532 #define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
\r
533 #define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
\r
534 #define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
\r
535 #define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
\r
536 #define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
\r
537 #define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
\r
538 #define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
\r
539 #define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
\r
540 #define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
\r
541 #define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
\r
542 #define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
\r
543 #define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
\r
544 #define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
\r
545 #define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
\r
546 #define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
\r
547 #define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
\r
548 #define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
\r
549 #define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
\r
550 #define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
\r
551 #define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
\r
552 #define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
\r
553 #define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
\r
554 #define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
\r
555 #define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
\r
556 #define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
\r
557 #define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
\r
558 #define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
\r
559 #define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
\r
560 #define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
\r
561 #define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down
\r
562 #define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass
\r
563 #define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
\r
564 #define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator
\r
565 #define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator
\r
566 #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4
\r
567 #define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.
\r
568 #define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.
\r
570 //*****************************************************************************
\r
572 // The following define the bit fields in the SYSCTL_DSLPCLKCFG register.
\r
574 //*****************************************************************************
\r
575 #define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override
\r
576 #define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
\r
577 #define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
\r
578 #define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
\r
579 #define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
\r
580 #define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
\r
581 #define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
\r
582 #define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
\r
583 #define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
\r
584 #define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
\r
585 #define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
\r
586 #define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
\r
587 #define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
\r
588 #define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
\r
589 #define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
\r
590 #define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
\r
591 #define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
\r
592 #define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
\r
593 #define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
\r
594 #define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
\r
595 #define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
\r
596 #define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
\r
597 #define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
\r
598 #define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
\r
599 #define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
\r
600 #define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
\r
601 #define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
\r
602 #define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
\r
603 #define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
\r
604 #define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
\r
605 #define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
\r
606 #define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
\r
607 #define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
\r
608 #define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
\r
609 #define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
\r
610 #define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
\r
611 #define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
\r
612 #define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
\r
613 #define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
\r
614 #define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
\r
615 #define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
\r
616 #define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
\r
617 #define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
\r
618 #define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
\r
619 #define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
\r
620 #define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
\r
621 #define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
\r
622 #define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
\r
623 #define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
\r
624 #define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
\r
625 #define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
\r
626 #define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
\r
627 #define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
\r
628 #define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
\r
629 #define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
\r
630 #define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
\r
631 #define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
\r
632 #define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
\r
633 #define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
\r
634 #define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
\r
635 #define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
\r
636 #define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
\r
637 #define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
\r
638 #define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
\r
639 #define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
\r
640 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override
\r
641 #define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator
\r
642 #define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.
\r
643 #define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.
\r
645 //*****************************************************************************
\r
647 // The following define the bit fields in the SYSCTL_CLKVCLR register.
\r
649 //*****************************************************************************
\r
650 #define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
\r
652 //*****************************************************************************
\r
654 // The following define the bit fields in the SYSCTL_LDOARST register.
\r
656 //*****************************************************************************
\r
657 #define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
\r
659 #endif // __HW_SYSCTL_H__
\r
projects / freertos / blob