1 //*****************************************************************************
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3 // hw_hibernate.h - Defines and Macros for the Hibernation module.
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5 // Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 1408 of the Stellaris Peripheral Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_HIBERNATE_H__
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29 #define __HW_HIBERNATE_H__
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31 //*****************************************************************************
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33 // The following define the addresses of the hibernation module registers.
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35 //*****************************************************************************
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36 #define HIB_RTCC 0x400fc000 // Hibernate RTC counter
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37 #define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0
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38 #define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1
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39 #define HIB_RTCLD 0x400fc00C // Hibernate RTC load
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40 #define HIB_CTL 0x400fc010 // Hibernate RTC control
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41 #define HIB_IM 0x400fc014 // Hibernate interrupt mask
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42 #define HIB_RIS 0x400fc018 // Hibernate raw interrupt status
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43 #define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat
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44 #define HIB_IC 0x400fc020 // Hibernate interrupt clear
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45 #define HIB_RTCT 0x400fc024 // Hibernate RTC trim
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46 #define HIB_DATA 0x400fc030 // Hibernate data area
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47 #define HIB_DATA_END 0x400fc130 // end of data area, exclusive
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49 //*****************************************************************************
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51 // The following define the bit fields in the Hibernate RTC counter register.
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53 //*****************************************************************************
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54 #define HIB_RTCC_MASK 0xffffffff // RTC counter mask
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56 //*****************************************************************************
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58 // The following define the bit fields in the Hibernate RTC match 0 register.
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60 //*****************************************************************************
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61 #define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask
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63 //*****************************************************************************
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65 // The following define the bit fields in the Hibernate RTC match 1 register.
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67 //*****************************************************************************
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68 #define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask
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70 //*****************************************************************************
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72 // The following define the bit fields in the Hibernate RTC load register.
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74 //*****************************************************************************
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75 #define HIB_RTCLD_MASK 0xffffffff // RTC load mask
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77 //*****************************************************************************
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79 // The following define the bit fields in the Hibernate control register
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81 //*****************************************************************************
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82 #define HIB_CTL_VABORT 0x00000080 // low bat abort
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83 #define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator
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84 #define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect
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85 #define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin
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86 #define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match
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87 #define HIB_CTL_CLKSEL 0x00000004 // clock input selection
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88 #define HIB_CTL_HIBREQ 0x00000002 // request hibernation
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89 #define HIB_CTL_RTCEN 0x00000001 // RTC enable
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91 //*****************************************************************************
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93 // The following define the bit fields in the Hibernate interrupt mask reg.
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95 //*****************************************************************************
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96 #define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt
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97 #define HIB_IM_LOWBAT 0x00000004 // low battery interrupt
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98 #define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt
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99 #define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt
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101 //*****************************************************************************
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103 // The following define the bit fields in the Hibernate raw interrupt status.
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105 //*****************************************************************************
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106 #define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt
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107 #define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt
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108 #define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt
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109 #define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
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111 //*****************************************************************************
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113 // The following define the bit fields in the Hibernate masked int status.
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115 //*****************************************************************************
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116 #define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt
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117 #define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt
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118 #define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt
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119 #define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
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121 //*****************************************************************************
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123 // The following define the bit fields in the Hibernate interrupt clear reg.
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125 //*****************************************************************************
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126 #define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt
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127 #define HIB_IC_LOWBAT 0x00000004 // low battery interrupt
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128 #define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt
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129 #define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt
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131 //*****************************************************************************
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133 // The following define the bit fields in the Hibernate RTC trim register.
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135 //*****************************************************************************
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136 #define HIB_RTCT_MASK 0x0000ffff // RTC trim mask
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138 //*****************************************************************************
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140 // The following define the bit fields in the Hibernate data register.
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142 //*****************************************************************************
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143 #define HIB_DATA_MASK 0xffffffff // NV memory data mask
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145 #endif // __HW_HIBERNATE_H__
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