1 //*****************************************************************************
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3 // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_PWM_H__
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29 #define __HW_PWM_H__
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31 //*****************************************************************************
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33 // PWM Module Register Offsets.
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35 //*****************************************************************************
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36 #define PWM_O_CTL 0x00000000 // PWM Master Control register
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37 #define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register
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38 #define PWM_O_ENABLE 0x00000008 // PWM Output Enable register
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39 #define PWM_O_INVERT 0x0000000C // PWM Output Inversion register
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40 #define PWM_O_FAULT 0x00000010 // PWM Output Fault register
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41 #define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register
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42 #define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.
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43 #define PWM_O_ISC 0x0000001C // PWM Interrupt Status register
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44 #define PWM_O_STATUS 0x00000020 // PWM Status register
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46 //*****************************************************************************
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48 // The following define the bit fields in the PWM Master Control register.
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50 //*****************************************************************************
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51 #define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
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52 #define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
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53 #define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
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55 //*****************************************************************************
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57 // The following define the bit fields in the PWM Time Base Sync register.
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59 //*****************************************************************************
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60 #define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter
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61 #define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter
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62 #define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter
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64 //*****************************************************************************
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66 // The following define the bit fields in the PWM Output Enable register.
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68 //*****************************************************************************
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69 #define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable
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70 #define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable
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71 #define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable
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72 #define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable
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73 #define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable
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74 #define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable
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76 //*****************************************************************************
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78 // The following define the bit fields in the PWM Inversion register.
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80 //*****************************************************************************
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81 #define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert
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82 #define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert
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83 #define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert
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84 #define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert
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85 #define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert
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86 #define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert
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88 //*****************************************************************************
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90 // The following define the bit fields in the PWM Fault register.
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92 //*****************************************************************************
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93 #define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault
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94 #define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault
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95 #define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault
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96 #define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault
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97 #define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault
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98 #define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault
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100 //*****************************************************************************
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102 // PWM Interrupt Register bit definitions.
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104 //*****************************************************************************
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105 #define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
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107 //*****************************************************************************
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109 // The following define the bit fields in the PWM Status register.
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111 //*****************************************************************************
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112 #define PWM_STATUS_FAULT 0x00000001 // Fault status
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114 //*****************************************************************************
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116 // PWM Generator standard offsets.
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118 //*****************************************************************************
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119 #define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
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120 #define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
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121 #define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
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123 #define PWM_O_X_CTL 0x00000000 // Gen Control Reg
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124 #define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
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125 #define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
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126 #define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
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127 #define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
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128 #define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
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129 #define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
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130 #define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
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131 #define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
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132 #define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
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133 #define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
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134 #define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
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135 #define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
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137 //*****************************************************************************
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139 // PWM_X Control Register bit definitions.
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141 //*****************************************************************************
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142 #define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block
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143 #define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down
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144 #define PWM_X_CTL_DEBUG 0x00000004 // Debug mode
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145 #define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg
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146 #define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg
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147 #define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg
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149 //*****************************************************************************
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151 // PWM_X Interrupt/Trigger Enable Register bit definitions.
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153 //*****************************************************************************
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154 #define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0
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155 #define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD
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156 #define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U
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157 #define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D
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158 #define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U
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159 #define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D
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160 #define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0
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161 #define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD
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162 #define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U
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163 #define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D
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164 #define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U
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165 #define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D
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167 //*****************************************************************************
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169 // PWM_X Raw Interrupt Status Register bit definitions.
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171 //*****************************************************************************
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172 #define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int
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173 #define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int
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174 #define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int
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175 #define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int
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176 #define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int
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177 #define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int
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179 //*****************************************************************************
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181 // PWM_X Interrupt Status Register bit definitions.
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183 //*****************************************************************************
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184 #define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
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185 #define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
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186 #define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
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187 #define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
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188 #define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
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189 #define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
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191 //*****************************************************************************
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193 // PWM_X Generator A/B Control Register bit definitions.
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195 //*****************************************************************************
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196 #define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
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197 #define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
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198 #define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
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199 #define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
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200 #define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
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201 #define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
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203 //*****************************************************************************
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205 // PWM_X Generator A/B Control Register action definitions.
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207 //*****************************************************************************
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208 #define PWM_GEN_ACT_NONE 0x0 // Do nothing
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209 #define PWM_GEN_ACT_INV 0x1 // Invert the output signal
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210 #define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero
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211 #define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one
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212 #define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
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213 #define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
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214 #define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
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215 #define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
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216 #define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
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217 #define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
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219 //*****************************************************************************
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221 // PWM_X Dead Band Control Register bit definitions.
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223 //*****************************************************************************
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224 #define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
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226 //*****************************************************************************
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228 // PWM Register reset values.
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230 //*****************************************************************************
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231 #define PWM_RV_CTL 0x00000000 // Master control of the PWM module
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232 #define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
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233 #define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM
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235 #define PWM_RV_INVERT 0x00000000 // Inversion control for
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237 #define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
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239 #define PWM_RV_INTEN 0x00000000 // Interrupt enable
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240 #define PWM_RV_RIS 0x00000000 // Raw interrupt status
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241 #define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
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242 #define PWM_RV_STATUS 0x00000000 // Status
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243 #define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
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245 #define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
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246 #define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
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247 #define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
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248 #define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
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249 #define PWM_RV_X_COUNT 0x00000000 // The current counter value
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250 #define PWM_RV_X_CMPA 0x00000000 // The comparator A value
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251 #define PWM_RV_X_CMPB 0x00000000 // The comparator B value
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252 #define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
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253 #define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
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254 #define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
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255 #define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
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257 #define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
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260 #endif // __HW_PWM_H__
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