1 //*****************************************************************************
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3 // hw_qei.h - Macros used when accessing the QEI hardware.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 #ifndef __HW_QEI_H__
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29 #define __HW_QEI_H__
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31 //*****************************************************************************
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33 // The following define the offsets of the QEI registers.
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35 //*****************************************************************************
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36 #define QEI_O_CTL 0x00000000 // Configuration and control reg.
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37 #define QEI_O_STAT 0x00000004 // Status register
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38 #define QEI_O_POS 0x00000008 // Current position register
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39 #define QEI_O_MAXPOS 0x0000000C // Maximum position register
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40 #define QEI_O_LOAD 0x00000010 // Velocity timer load register
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41 #define QEI_O_TIME 0x00000014 // Velocity timer register
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42 #define QEI_O_COUNT 0x00000018 // Velocity pulse count register
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43 #define QEI_O_SPEED 0x0000001C // Velocity speed register
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44 #define QEI_O_INTEN 0x00000020 // Interrupt enable register
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45 #define QEI_O_RIS 0x00000024 // Raw interrupt status register
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46 #define QEI_O_ISC 0x00000028 // Interrupt status register
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48 //*****************************************************************************
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50 // The following define the bit fields in the QEI_CTL register.
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52 //*****************************************************************************
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53 #define QEI_CTL_STALLEN 0x00001000 // Stall enable
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54 #define QEI_CTL_INVI 0x00000800 // Invert Index input
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55 #define QEI_CTL_INVB 0x00000400 // Invert PhB input
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56 #define QEI_CTL_INVA 0x00000200 // Invert PhA input
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57 #define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask
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58 #define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1
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59 #define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2
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60 #define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4
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61 #define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8
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62 #define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16
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63 #define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32
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64 #define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64
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65 #define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128
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66 #define QEI_CTL_VELEN 0x00000020 // Velocity enable
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67 #define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode
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68 #define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode
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69 #define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode
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70 #define QEI_CTL_SWAP 0x00000002 // Swap input signals
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71 #define QEI_CTL_ENABLE 0x00000001 // QEI enable
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73 //*****************************************************************************
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75 // The following define the bit fields in the QEI_STAT register.
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77 //*****************************************************************************
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78 #define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation
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79 #define QEI_STAT_ERROR 0x00000001 // Signalling error detected
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81 //*****************************************************************************
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83 // The following define the bit fields in the QEI_POS register.
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85 //*****************************************************************************
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86 #define QEI_POS_M 0xFFFFFFFF // Current encoder position
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89 //*****************************************************************************
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91 // The following define the bit fields in the QEI_MAXPOS register.
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93 //*****************************************************************************
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94 #define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position
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95 #define QEI_MAXPOS_S 0
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97 //*****************************************************************************
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99 // The following define the bit fields in the QEI_LOAD register.
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101 //*****************************************************************************
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102 #define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value
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103 #define QEI_LOAD_S 0
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105 //*****************************************************************************
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107 // The following define the bit fields in the QEI_TIME register.
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109 //*****************************************************************************
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110 #define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value
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111 #define QEI_TIME_S 0
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113 //*****************************************************************************
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115 // The following define the bit fields in the QEI_COUNT register.
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117 //*****************************************************************************
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118 #define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count
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119 #define QEI_COUNT_S 0
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121 //*****************************************************************************
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123 // The following define the bit fields in the QEI_SPEED register.
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125 //*****************************************************************************
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126 #define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count
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127 #define QEI_SPEED_S 0
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129 //*****************************************************************************
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131 // The following define the bit fields in the QEI_INTEN register.
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133 //*****************************************************************************
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134 #define QEI_INTEN_ERROR 0x00000008 // Phase error detected
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135 #define QEI_INTEN_DIR 0x00000004 // Direction change
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136 #define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired
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137 #define QEI_INTEN_INDEX 0x00000001 // Index pulse detected
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139 //*****************************************************************************
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141 // The following define the bit fields in the QEI_RIS register.
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143 //*****************************************************************************
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144 #define QEI_RIS_ERROR 0x00000008 // Phase error detected
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145 #define QEI_RIS_DIR 0x00000004 // Direction change
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146 #define QEI_RIS_TIMER 0x00000002 // Velocity timer expired
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147 #define QEI_RIS_INDEX 0x00000001 // Index pulse detected
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149 //*****************************************************************************
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151 // The following define the bit fields in the QEI_ISC register.
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153 //*****************************************************************************
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154 #define QEI_INT_ERROR 0x00000008 // Phase error detected
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155 #define QEI_INT_DIR 0x00000004 // Direction change
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156 #define QEI_INT_TIMER 0x00000002 // Velocity timer expired
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157 #define QEI_INT_INDEX 0x00000001 // Index pulse detected
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159 //*****************************************************************************
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161 // The following define the reset values for the QEI registers.
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163 //*****************************************************************************
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164 #define QEI_RV_CTL 0x00000000 // Configuration and control reg.
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165 #define QEI_RV_STAT 0x00000000 // Status register
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166 #define QEI_RV_POS 0x00000000 // Current position register
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167 #define QEI_RV_MAXPOS 0x00000000 // Maximum position register
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168 #define QEI_RV_LOAD 0x00000000 // Velocity timer load register
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169 #define QEI_RV_TIME 0x00000000 // Velocity timer register
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170 #define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
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171 #define QEI_RV_SPEED 0x00000000 // Velocity speed register
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172 #define QEI_RV_INTEN 0x00000000 // Interrupt enable register
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173 #define QEI_RV_RIS 0x00000000 // Raw interrupt status register
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174 #define QEI_RV_ISC 0x00000000 // Interrupt status register
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176 #endif // __HW_QEI_H__
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