1 //*****************************************************************************
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3 // i2c.c - Driver for Inter-IC (I2C) bus block.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 //! \addtogroup i2c_api
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33 //*****************************************************************************
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35 #include "../hw_i2c.h"
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36 #include "../hw_ints.h"
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37 #include "../hw_memmap.h"
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38 #include "../hw_types.h"
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41 #include "interrupt.h"
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44 //*****************************************************************************
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46 //! Initializes the I2C Master block.
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48 //! \param ulBase base address of the I2C Master module
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49 //! \param bFast set up for fast data transfers
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51 //! This function initializes operation of the I2C Master block. Upon
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52 //! successful initialization of the I2C block, this function will have
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53 //! set the bus speed for the master, and will have enabled the I2C Master
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56 //! If the parameter \e bFast is \b true, then the master block will be
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57 //! set up to transfer data at 400 kbps; otherwise, it will be set up to
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58 //! transfer data at 100 kbps.
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60 //! The I2C clocking is dependent upon the system clock rate returned by
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61 //! SysCtlClockGet(); if it does not return the correct system clock rate then
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62 //! the I2C clock rate will be incorrect.
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66 //*****************************************************************************
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67 #if defined(GROUP_masterinit) || defined(BUILD_ALL) || defined(DOXYGEN)
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69 I2CMasterInit(unsigned long ulBase, tBoolean bFast)
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71 unsigned long ulSysClk;
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72 unsigned long ulSCLFreq;
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73 unsigned long ulTPR;
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76 // Check the arguments.
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78 ASSERT(ulBase == I2C_MASTER_BASE);
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81 // Must enable the device before doing anything else.
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83 I2CMasterEnable(ulBase);
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86 // Get the system clock speed.
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88 ulSysClk = SysCtlClockGet();
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91 // Get the desired SCL speed.
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95 ulSCLFreq = I2C_SCL_FAST;
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99 ulSCLFreq = I2C_SCL_STANDARD;
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103 // Compute the clock divider that achieves the fastest speed less than or
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104 // equal to the desired speed. The numerator is biases to favor a larger
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105 // clock divider so that the resulting clock is always less than or equal
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106 // to the desired clock, never greater.
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108 ulTPR = (((ulSysClk + (2 * I2C_MASTER_TPR_SCL * ulSCLFreq) - 1) /
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109 (2 * I2C_MASTER_TPR_SCL * ulSCLFreq)) - 1);
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110 HWREG(ulBase + I2C_MASTER_O_TPR) = ulTPR;
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114 //*****************************************************************************
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116 //! Initializes the I2C Slave block.
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118 //! \param ulBase base address of the I2C Slave module
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119 //! \param ucSlaveAddr 7-bit slave address
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121 //! This function initializes operation of the I2C Slave block. Upon
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122 //! successful initialization of the I2C blocks, this function will have
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123 //! set the slave address and have enabled the I2C Slave block.
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125 //! The parameter \e ucSlaveAddr is the value that will be compared
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126 //! against the slave address sent by an I2C master.
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130 //*****************************************************************************
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131 #if defined(GROUP_slaveinit) || defined(BUILD_ALL) || defined(DOXYGEN)
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133 I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
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136 // Check the arguments.
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138 ASSERT(ulBase == I2C_SLAVE_BASE);
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139 ASSERT(!(ucSlaveAddr & 0x80));
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142 // Must enable the device before doing anything else.
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144 I2CSlaveEnable(ulBase);
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147 // Set up the slave address.
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149 HWREG(ulBase + I2C_SLAVE_O_OAR) = ucSlaveAddr;
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153 //*****************************************************************************
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155 //! Enables the I2C Master block.
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157 //! \param ulBase base address of the I2C Master module
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159 //! This will enable operation of the I2C Master block.
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163 //*****************************************************************************
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164 #if defined(GROUP_masterenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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166 I2CMasterEnable(unsigned long ulBase)
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169 // Check the arguments.
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171 ASSERT(ulBase == I2C_MASTER_BASE);
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174 // Enable the master block.
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176 HWREG(ulBase + I2C_MASTER_O_CR) |= I2C_MASTER_CR_MFE;
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180 //*****************************************************************************
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182 //! Enables the I2C Slave block.
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184 //! \param ulBase base address of the I2C Slave module
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186 //! This will enable operation of the I2C Slave block.
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190 //*****************************************************************************
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191 #if defined(GROUP_slaveenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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193 I2CSlaveEnable(unsigned long ulBase)
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196 // Check the arguments.
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198 ASSERT(ulBase == I2C_SLAVE_BASE);
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201 // Enable the clock to the slave block.
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203 HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) |= I2C_MASTER_CR_SFE;
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206 // Enable the slave.
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208 HWREG(ulBase + I2C_SLAVE_O_CSR) = I2C_SLAVE_CSR_DA;
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212 //*****************************************************************************
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214 //! Disables the I2C master block.
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216 //! \param ulBase base address of the I2C Master module
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218 //! This will disable operation of the I2C master block.
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222 //*****************************************************************************
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223 #if defined(GROUP_masterdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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225 I2CMasterDisable(unsigned long ulBase)
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228 // Check the arguments.
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230 ASSERT(ulBase == I2C_MASTER_BASE);
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233 // Disable the master block.
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235 HWREG(ulBase + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_MFE);
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239 //*****************************************************************************
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241 //! Disables the I2C slave block.
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243 //! \param ulBase base address of the I2C Slave module
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245 //! This will disable operation of the I2C slave block.
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249 //*****************************************************************************
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250 #if defined(GROUP_slavedisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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252 I2CSlaveDisable(unsigned long ulBase)
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255 // Check the arguments.
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257 ASSERT(ulBase == I2C_SLAVE_BASE);
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260 // Disable the slave.
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262 HWREG(ulBase + I2C_SLAVE_O_CSR) = 0;
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265 // Disable the clock to the slave block.
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267 HWREG(ulBase - I2C_O_SLAVE + I2C_MASTER_O_CR) &= ~(I2C_MASTER_CR_SFE);
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271 //*****************************************************************************
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273 //! Registers an interrupt handler for the I2C module
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275 //! \param ulBase base address of the I2C module
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276 //! \param pfnHandler is a pointer to the function to be called when the
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277 //! synchronous serial interface interrupt occurs.
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279 //! This sets the handler to be called when an I2C interrupt occurs. This
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280 //! will enable the global interrupt in the interrupt controller; specific I2C
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281 //! interrupts must be enabled via I2CMasterIntEnable() and
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282 //! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
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283 //! responsibility to clear the interrupt source via I2CMasterIntClear() and
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284 //! I2CSlaveIntClear().
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286 //! \sa IntRegister() for important information about registering interrupt
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291 //*****************************************************************************
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292 #if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
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294 I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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297 // Check the arguments.
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299 ASSERT(ulBase == I2C_MASTER_BASE);
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302 // Register the interrupt handler, returning an error if an error occurs.
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304 IntRegister(INT_I2C, pfnHandler);
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307 // Enable the I2C interrupt.
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309 IntEnable(INT_I2C);
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313 //*****************************************************************************
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315 //! Unregisters an interrupt handler for the I2C module.
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317 //! \param ulBase base address of the I2C module
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319 //! This function will clear the handler to be called when an I2C
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320 //! interrupt occurs. This will also mask off the interrupt in the interrupt
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321 //! controller so that the interrupt handler no longer is called.
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323 //! \sa IntRegister() for important information about registering interrupt
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328 //*****************************************************************************
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329 #if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
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331 I2CIntUnregister(unsigned long ulBase)
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334 // Check the arguments.
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336 ASSERT(ulBase == I2C_MASTER_BASE);
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339 // Disable the interrupt.
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341 IntDisable(INT_I2C);
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344 // Unregister the interrupt handler.
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346 IntUnregister(INT_I2C);
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350 //*****************************************************************************
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352 //! Enables the I2C Master interrupt.
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354 //! \param ulBase base address of the I2C Master module
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356 //! Enables the I2C Master interrupt source.
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360 //*****************************************************************************
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361 #if defined(GROUP_masterintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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363 I2CMasterIntEnable(unsigned long ulBase)
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366 // Check the arguments.
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368 ASSERT(ulBase == I2C_MASTER_BASE);
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371 // Enable the master interrupt.
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373 HWREG(ulBase + I2C_MASTER_O_IMR) = 1;
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377 //*****************************************************************************
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379 //! Enables the I2C Slave interrupt.
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381 //! \param ulBase base address of the I2C Slave module
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383 //! Enables the I2C Slave interrupt source.
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387 //*****************************************************************************
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388 #if defined(GROUP_slaveintenable) || defined(BUILD_ALL) || defined(DOXYGEN)
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390 I2CSlaveIntEnable(unsigned long ulBase)
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393 // Check the arguments.
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395 ASSERT(ulBase == I2C_SLAVE_BASE);
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398 // Enable the slave interrupt.
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400 HWREG(ulBase + I2C_SLAVE_O_IM) = 1;
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404 //*****************************************************************************
\r
406 //! Disables the I2C Master interrupt.
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408 //! \param ulBase base address of the I2C Master module
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410 //! Disables the I2C Master interrupt source.
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414 //*****************************************************************************
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415 #if defined(GROUP_masterintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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417 I2CMasterIntDisable(unsigned long ulBase)
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420 // Check the arguments.
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422 ASSERT(ulBase == I2C_MASTER_BASE);
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425 // Disable the master interrupt.
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427 HWREG(ulBase + I2C_MASTER_O_IMR) = 0;
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431 //*****************************************************************************
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433 //! Disables the I2C Slave interrupt.
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435 //! \param ulBase base address of the I2C Slave module
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437 //! Disables the I2C Slave interrupt source.
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441 //*****************************************************************************
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442 #if defined(GROUP_slaveintdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
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444 I2CSlaveIntDisable(unsigned long ulBase)
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447 // Check the arguments.
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449 ASSERT(ulBase == I2C_SLAVE_BASE);
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452 // Disable the slave interrupt.
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454 HWREG(ulBase + I2C_SLAVE_O_IM) = 0;
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458 //*****************************************************************************
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460 //! Gets the current I2C Master interrupt status.
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462 //! \param ulBase base address of the I2C Master module
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463 //! \param bMasked is false if the raw interrupt status is requested and
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464 //! true if the masked interrupt status is requested.
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466 //! This returns the interrupt status for the I2C Master module.
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467 //! Either the raw interrupt status or the status of interrupts that are
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468 //! allowed to reflect to the processor can be returned.
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470 //! \return The current interrupt status, returned as \b true if active
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471 //! or \b false if not active.
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473 //*****************************************************************************
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474 #if defined(GROUP_masterintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
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476 I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
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479 // Check the arguments.
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481 ASSERT(ulBase == I2C_MASTER_BASE);
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484 // Return either the interrupt status or the raw interrupt status as
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489 return((HWREG(ulBase + I2C_MASTER_O_MIS)) ? true : false);
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493 return((HWREG(ulBase + I2C_MASTER_O_RIS)) ? true : false);
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498 //*****************************************************************************
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500 //! Gets the current I2C Slave interrupt status.
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502 //! \param ulBase base address of the I2C Slave module
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503 //! \param bMasked is false if the raw interrupt status is requested and
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504 //! true if the masked interrupt status is requested.
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506 //! This returns the interrupt status for the I2C Slave module.
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507 //! Either the raw interrupt status or the status of interrupts that are
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508 //! allowed to reflect to the processor can be returned.
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510 //! \return The current interrupt status, returned as \b true if active
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511 //! or \b false if not active.
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513 //*****************************************************************************
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514 #if defined(GROUP_slaveintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
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516 I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
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519 // Check the arguments.
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521 ASSERT(ulBase == I2C_SLAVE_BASE);
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524 // Return either the interrupt status or the raw interrupt status as
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529 return((HWREG(ulBase + I2C_SLAVE_O_MIS)) ? true : false);
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533 return((HWREG(ulBase + I2C_SLAVE_O_RIS)) ? true : false);
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538 //*****************************************************************************
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540 //! Clears I2C Master interrupt sources.
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542 //! \param ulBase base address of the I2C Master module
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544 //! The I2C Master interrupt source is cleared, so that it no longer asserts.
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545 //! This must be done in the interrupt handler to keep it from being called
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546 //! again immediately upon exit.
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550 //*****************************************************************************
\r
551 #if defined(GROUP_masterintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
553 I2CMasterIntClear(unsigned long ulBase)
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556 // Check the arguments.
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558 ASSERT(ulBase == I2C_MASTER_BASE);
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561 // Clear the I2C master interrupt source.
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563 HWREG(ulBase + I2C_MASTER_O_MICR) = I2C_MASTER_MICR_IC;
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566 // Workaround for I2C master interrupt clear errata for rev B Stellaris
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567 // devices. For later devices, this write is ignored and therefore
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568 // harmless (other than the slight performance hit).
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570 HWREG(ulBase + I2C_MASTER_O_MIS) = I2C_MASTER_MICR_IC;
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574 //*****************************************************************************
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576 //! Clears I2C Slave interrupt sources.
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578 //! \param ulBase base address of the I2C Slave module
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580 //! The I2C Slave interrupt source is cleared, so that it no longer asserts.
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581 //! This must be done in the interrupt handler to keep it from being called
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582 //! again immediately upon exit.
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586 //*****************************************************************************
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587 #if defined(GROUP_slaveintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
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589 I2CSlaveIntClear(unsigned long ulBase)
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592 // Check the arguments.
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594 ASSERT(ulBase == I2C_SLAVE_BASE);
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597 // Clear the I2C slave interrupt source.
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599 HWREG(ulBase + I2C_SLAVE_O_SICR) = I2C_SLAVE_SICR_IC;
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603 //*****************************************************************************
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605 //! Sets the address that the I2C Master will place on the bus.
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607 //! \param ulBase base address of the I2C Master module
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608 //! \param ucSlaveAddr 7-bit slave address
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609 //! \param bReceive flag indicating the type of communication with the slave
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611 //! This function will set the address that the I2C Master will place on the
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612 //! bus when initiating a transaction. When the parameter \e bReceive is set
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613 //! to \b true, the address will indicate that the I2C Master is initiating
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614 //! a read from the slave; otherwise the address will indicate that the I2C
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615 //! Master is initiating a write to the slave.
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619 //*****************************************************************************
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620 #if defined(GROUP_masterslaveaddrset) || defined(BUILD_ALL) || defined(DOXYGEN)
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622 I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
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626 // Check the arguments.
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628 ASSERT(ulBase == I2C_MASTER_BASE);
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629 ASSERT(!(ucSlaveAddr & 0x80));
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632 // Set the address of the slave with which the master will communicate.
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634 HWREG(ulBase + I2C_MASTER_O_SA) = (ucSlaveAddr << 1) | bReceive;
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638 //*****************************************************************************
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640 //! Indicates whether or not the I2C Master is busy.
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642 //! \param ulBase base address of the I2C Master module
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644 //! This function returns an indication of whether or not the I2C Master is
\r
645 //! busy transmitting or receiving data.
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647 //! \return Returns \b true if the I2C Master is busy; otherwise, returns
\r
650 //*****************************************************************************
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651 #if defined(GROUP_masterbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
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653 I2CMasterBusy(unsigned long ulBase)
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656 // Check the arguments.
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658 ASSERT(ulBase == I2C_MASTER_BASE);
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661 // Return the busy status.
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663 if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUSY)
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674 //*****************************************************************************
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676 //! Indicates whether or not the I2C bus is busy.
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678 //! \param ulBase base address of the I2C Master module
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680 //! This function returns an indication of whether or not the I2C bus is
\r
681 //! busy. This function can be used in a multi-master environment to
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682 //! determine if another master is currently using the bus.
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684 //! \return Returns \b true if the I2C bus is busy; otherwise, returns
\r
687 //*****************************************************************************
\r
688 #if defined(GROUP_masterbusbusy) || defined(BUILD_ALL) || defined(DOXYGEN)
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690 I2CMasterBusBusy(unsigned long ulBase)
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693 // Check the arguments.
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695 ASSERT(ulBase == I2C_MASTER_BASE);
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698 // Return the bus busy status.
\r
700 if(HWREG(ulBase + I2C_MASTER_O_CS) & I2C_MASTER_CS_BUS_BUSY)
\r
711 //*****************************************************************************
\r
713 //! Controls the state of the I2C Master module.
\r
715 //! \param ulBase base address of the I2C Master module
\r
716 //! \param ulCmd command to be issued to the I2C Master module
\r
718 //! This function is used to control the state of the Master module send and
\r
719 //! receive operations. The parameter \e ucCmd can be one of the following
\r
722 //! - I2C_MASTER_CMD_SINGLE_SEND
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723 //! - I2C_MASTER_CMD_SINGLE_RECEIVE
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724 //! - I2C_MASTER_CMD_BURST_SEND_START
\r
725 //! - I2C_MASTER_CMD_BURST_SEND_CONT
\r
726 //! - I2C_MASTER_CMD_BURST_SEND_FINISH
\r
727 //! - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
\r
728 //! - I2C_MASTER_CMD_BURST_RECEIVE_START
\r
729 //! - I2C_MASTER_CMD_BURST_RECEIVE_CONT
\r
730 //! - I2C_MASTER_CMD_BURST_RECEIVE_FINISH
\r
731 //! - I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
\r
735 //*****************************************************************************
\r
736 #if defined(GROUP_mastercontrol) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
738 I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
\r
741 // Check the arguments.
\r
743 ASSERT(ulBase == I2C_MASTER_BASE);
\r
744 ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
\r
745 (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
\r
746 (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
\r
747 (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
\r
748 (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
\r
749 (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
\r
750 (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
\r
751 (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
\r
752 (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
\r
753 (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
\r
756 // Send the command.
\r
758 HWREG(ulBase + I2C_MASTER_O_CS) = ulCmd;
\r
762 //*****************************************************************************
\r
764 //! Gets the error status of the I2C Master module.
\r
766 //! \param ulBase base address of the I2C Master module
\r
768 //! This function is used to obtain the error status of the Master module
\r
769 //! send and receive operations. It returns one of the following values:
\r
771 //! - I2C_MASTER_ERR_NONE
\r
772 //! - I2C_MASTER_ERR_ADDR_ACK
\r
773 //! - I2C_MASTER_ERR_DATA_ACK
\r
774 //! - I2C_MASTER_ERR_ARB_LOST
\r
778 //*****************************************************************************
\r
779 #if defined(GROUP_mastererr) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
781 I2CMasterErr(unsigned long ulBase)
\r
783 unsigned long ulErr;
\r
786 // Check the arguments.
\r
788 ASSERT(ulBase == I2C_MASTER_BASE);
\r
791 // Get the raw error state
\r
793 ulErr = HWREG(ulBase + I2C_MASTER_O_CS);
\r
796 // If the I2C master is busy, then all the other bit are invalid, and
\r
797 // don't have an error to report.
\r
799 if(ulErr & I2C_MASTER_CS_BUSY)
\r
801 return(I2C_MASTER_ERR_NONE);
\r
805 // Check for errors.
\r
807 if(ulErr & I2C_MASTER_CS_ERROR)
\r
809 return(ulErr & (I2C_MASTER_CS_ERR_MASK));
\r
813 return(I2C_MASTER_ERR_NONE);
\r
818 //*****************************************************************************
\r
820 //! Transmits a byte from the I2C Master.
\r
822 //! \param ulBase base address of the I2C Master module
\r
823 //! \param ucData data to be transmitted from the I2C Master
\r
825 //! This function will place the supplied data into I2C Master Data Register.
\r
829 //*****************************************************************************
\r
830 #if defined(GROUP_masterdataput) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
832 I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
\r
835 // Check the arguments.
\r
837 ASSERT(ulBase == I2C_MASTER_BASE);
\r
842 HWREG(ulBase + I2C_MASTER_O_DR) = ucData;
\r
846 //*****************************************************************************
\r
848 //! Receives a byte that has been sent to the I2C Master.
\r
850 //! \param ulBase base address of the I2C Master module
\r
852 //! This function reads a byte of data from the I2C Master Data Register.
\r
854 //! \return Returns the byte received from by the I2C Master, cast as an
\r
857 //*****************************************************************************
\r
858 #if defined(GROUP_masterdataget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
860 I2CMasterDataGet(unsigned long ulBase)
\r
863 // Check the arguments.
\r
865 ASSERT(ulBase == I2C_MASTER_BASE);
\r
870 return(HWREG(ulBase + I2C_MASTER_O_DR));
\r
874 //*****************************************************************************
\r
876 //! Gets the I2C Slave module status
\r
878 //! \param ulBase base address of the I2C Slave module
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880 //! This function will return the action requested from a master, if any. The
\r
881 //! possible values returned are:
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883 //! - I2C_SLAVE_ACT_NONE
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884 //! - I2C_SLAVE_ACT_RREQ
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885 //! - I2C_SLAVE_ACT_TREQ
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887 //! where I2C_SLAVE_ACT_NONE means that no action has been requested of the
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888 //! I2C Slave module, I2C_SLAVE_ACT_RREQ means that an I2C master has sent
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889 //! data to the I2C Slave module, and I2C_SLAVE_ACT_TREQ means that an I2C
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890 //! master has requested that the I2C Slave module send data.
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894 //*****************************************************************************
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895 #if defined(GROUP_slavestatus) || defined(BUILD_ALL) || defined(DOXYGEN)
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897 I2CSlaveStatus(unsigned long ulBase)
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900 // Check the arguments.
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902 ASSERT(ulBase == I2C_SLAVE_BASE);
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905 // Return the slave status.
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907 return(HWREG(ulBase + I2C_SLAVE_O_CSR));
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911 //*****************************************************************************
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913 //! Transmits a byte from the I2C Slave.
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915 //! \param ulBase base address of the I2C Slave module
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916 //! \param ucData data to be transmitted from the I2C Slave
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918 //! This function will place the supplied data into I2C Slave Data Register.
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922 //*****************************************************************************
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923 #if defined(GROUP_slavedataput) || defined(BUILD_ALL) || defined(DOXYGEN)
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925 I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
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928 // Check the arguments.
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930 ASSERT(ulBase == I2C_SLAVE_BASE);
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935 HWREG(ulBase + I2C_SLAVE_O_DR) = ucData;
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939 //*****************************************************************************
\r
941 //! Receives a byte that has been sent to the I2C Slave.
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943 //! \param ulBase base address of the I2C Slave module
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945 //! This function reads a byte of data from the I2C Slave Data Register.
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947 //! \return Returns the byte received from by the I2C Slave, cast as an
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950 //*****************************************************************************
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951 #if defined(GROUP_slavedataget) || defined(BUILD_ALL) || defined(DOXYGEN)
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953 I2CSlaveDataGet(unsigned long ulBase)
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956 // Check the arguments.
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958 ASSERT(ulBase == I2C_SLAVE_BASE);
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963 return(HWREG(ulBase + I2C_SLAVE_O_DR));
\r
967 //*****************************************************************************
\r
969 // Close the Doxygen group.
\r
972 //*****************************************************************************
\r