1 //*****************************************************************************
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3 // uart.c - Driver for the UART.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 //! \addtogroup uart_api
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33 //*****************************************************************************
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35 #include "../hw_ints.h"
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36 #include "../hw_memmap.h"
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37 #include "../hw_types.h"
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38 #include "../hw_uart.h"
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40 #include "interrupt.h"
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44 //*****************************************************************************
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46 //! Sets the type of parity.
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48 //! \param ulBase is the base address of the UART port.
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49 //! \param ulParity specifies the type of parity to use.
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51 //! Sets the type of parity to use for transmitting and expect when receiving.
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52 //! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
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53 //! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
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54 //! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
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55 //! parity bit; it will always be either be one or zero based on the mode.
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59 //*****************************************************************************
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60 #if defined(GROUP_paritymodeset) || defined(BUILD_ALL) || defined(DOXYGEN)
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62 UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
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65 // Check the arguments.
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67 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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68 ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
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69 (ulParity == UART_CONFIG_PAR_EVEN) ||
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70 (ulParity == UART_CONFIG_PAR_ODD) ||
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71 (ulParity == UART_CONFIG_PAR_ONE) ||
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72 (ulParity == UART_CONFIG_PAR_ZERO));
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75 // Set the parity mode.
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77 HWREG(ulBase + UART_O_LCR_H) = ((HWREG(ulBase + UART_O_LCR_H) &
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78 ~(UART_LCR_H_SPS | UART_LCR_H_EPS |
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79 UART_LCR_H_PEN)) | ulParity);
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83 //*****************************************************************************
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85 //! Gets the type of parity currently being used.
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87 //! \param ulBase is the base address of the UART port.
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89 //! \return The current parity settings, specified as one of
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90 //! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
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91 //! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
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93 //*****************************************************************************
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94 #if defined(GROUP_paritymodeget) || defined(BUILD_ALL) || defined(DOXYGEN)
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96 UARTParityModeGet(unsigned long ulBase)
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99 // Check the arguments.
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101 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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104 // Return the current parity setting.
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106 return(HWREG(ulBase + UART_O_LCR_H) &
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107 (UART_LCR_H_SPS | UART_LCR_H_EPS | UART_LCR_H_PEN));
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111 //*****************************************************************************
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113 //! Sets the configuration of a UART.
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115 //! \param ulBase is the base address of the UART port.
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116 //! \param ulBaud is the desired baud rate.
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117 //! \param ulConfig is the data format for the port (number of data bits,
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118 //! number of stop bits, and parity).
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120 //! This function will configure the UART for operation in the specified data
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121 //! format. The baud rate is provided in the \e ulBaud parameter and the
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122 //! data format in the \e ulConfig parameter.
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124 //! The \e ulConfig parameter is the logical OR of three values: the number of
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125 //! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
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126 //! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
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127 //! select from eight to five data bits per byte (respectively).
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128 //! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
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129 //! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
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130 //! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
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131 //! select the parity mode (no parity bit, even parity bit, odd parity bit,
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132 //! parity bit always one, and parity bit always zero, respectively).
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134 //! The baud rate is dependent upon the system clock rate returned by
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135 //! SysCtlClockGet(); if it does not return the correct system clock rate then
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136 //! the baud rate will be incorrect.
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140 //*****************************************************************************
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141 #if defined(GROUP_configset) || defined(BUILD_ALL) || defined(DOXYGEN)
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143 UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,
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144 unsigned long ulConfig)
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146 unsigned long ulUARTClk, ulInt, ulFrac;
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149 // Check the arguments.
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151 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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156 UARTDisable(ulBase);
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159 // Determine the UART clock rate.
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161 ulUARTClk = SysCtlClockGet();
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164 // Compute the fractional baud rate divider.
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166 ulInt = ulUARTClk / (16 * ulBaud);
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167 ulFrac = ulUARTClk % (16 * ulBaud);
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168 ulFrac = ((((2 * ulFrac * 4) / ulBaud) + 1) / 2);
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171 // Set the baud rate.
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173 HWREG(ulBase + UART_O_IBRD) = ulInt;
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174 HWREG(ulBase + UART_O_FBRD) = ulFrac;
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177 // Set parity, data length, and number of stop bits.
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179 HWREG(ulBase + UART_O_LCR_H) = ulConfig;
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182 // Clear the flags register.
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184 HWREG(ulBase + UART_O_FR) = 0;
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189 UARTEnable(ulBase);
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193 //*****************************************************************************
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195 //! Gets the current configuration of a UART.
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197 //! \param ulBase is the base address of the UART port.
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198 //! \param pulBaud is a pointer to storage for the baud rate.
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199 //! \param pulConfig is a pointer to storage for the data format.
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201 //! The baud rate and data format for the UART is determined. The returned
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202 //! baud rate is the actual baud rate; it may not be the exact baud rate
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203 //! requested or an ``official'' baud rate. The data format returned in
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204 //! \e pulConfig is enumerated the same as the \e ulConfig parameter of
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205 //! UARTConfigSet().
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207 //! The baud rate is dependent upon the system clock rate returned by
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208 //! SysCtlClockGet(); if it does not return the correct system clock rate then
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209 //! the baud rate will be computed incorrectly.
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213 //*****************************************************************************
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214 #if defined(GROUP_configget) || defined(BUILD_ALL) || defined(DOXYGEN)
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216 UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,
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217 unsigned long *pulConfig)
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220 unsigned long ulInt, ulFrac;
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223 // Check the arguments.
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225 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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228 // Compute the baud rate.
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230 ulInt = HWREG(ulBase + UART_O_IBRD);
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231 ulFrac = HWREG(ulBase + UART_O_FBRD);
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232 *pulBaud = (SysCtlClockGet() * 4) / ((64 * ulInt) + ulFrac);
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235 // Get the parity, data length, and number of stop bits.
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237 *pulConfig = (HWREG(ulBase + UART_O_LCR_H) &
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238 (UART_LCR_H_SPS | UART_LCR_H_WLEN | UART_LCR_H_STP2 |
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239 UART_LCR_H_EPS | UART_LCR_H_PEN));
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243 //*****************************************************************************
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245 //! Enables transmitting and receiving.
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247 //! \param ulBase is the base address of the UART port.
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249 //! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
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254 //*****************************************************************************
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255 #if defined(GROUP_enable) || defined(BUILD_ALL) || defined(DOXYGEN)
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257 UARTEnable(unsigned long ulBase)
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260 // Check the arguments.
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262 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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265 // Enable the FIFO.
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267 HWREG(ulBase + UART_O_LCR_H) |= UART_LCR_H_FEN;
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270 // Enable RX, TX, and the UART.
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272 HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
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277 //*****************************************************************************
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279 //! Disables transmitting and receiving.
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281 //! \param ulBase is the base address of the UART port.
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283 //! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
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284 //! transmission of the current character, and flushes the transmit FIFO.
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288 //*****************************************************************************
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289 #if defined(GROUP_disable) || defined(BUILD_ALL) || defined(DOXYGEN)
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291 UARTDisable(unsigned long ulBase)
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294 // Check the arguments.
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296 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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299 // Wait for end of TX.
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301 while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
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306 // Disable the FIFO.
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308 HWREG(ulBase + UART_O_LCR_H) &= ~(UART_LCR_H_FEN);
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311 // Disable the UART.
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313 HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
\r
318 //*****************************************************************************
\r
320 //! Determines if there are any characters in the receive FIFO.
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322 //! \param ulBase is the base address of the UART port.
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324 //! This function returns a flag indicating whether or not there is data
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325 //! available in the receive FIFO.
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327 //! \return Returns \b true if there is data in the receive FIFO, and \b false
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328 //! if there is no data in the receive FIFO.
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330 //*****************************************************************************
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331 #if defined(GROUP_charsavail) || defined(BUILD_ALL) || defined(DOXYGEN)
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333 UARTCharsAvail(unsigned long ulBase)
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336 // Check the arguments.
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338 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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341 // Return the availability of characters.
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343 return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
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347 //*****************************************************************************
\r
349 //! Determines if there is any space in the transmit FIFO.
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351 //! \param ulBase is the base address of the UART port.
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353 //! This function returns a flag indicating whether or not there is space
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354 //! available in the transmit FIFO.
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356 //! \return Returns \b true if there is space available in the transmit FIFO,
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357 //! and \b false if there is no space available in the transmit FIFO.
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359 //*****************************************************************************
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360 #if defined(GROUP_spaceavail) || defined(BUILD_ALL) || defined(DOXYGEN)
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362 UARTSpaceAvail(unsigned long ulBase)
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365 // Check the arguments.
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367 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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370 // Return the availability of space.
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372 return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
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376 //*****************************************************************************
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378 //! Receives a character from the specified port.
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380 //! \param ulBase is the base address of the UART port.
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382 //! Gets a character from the receive FIFO for the specified port.
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384 //! \return Returns the character read from the specified port, cast as a
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385 //! \e long. A \b -1 will be returned if there are no characters present in
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386 //! the receive FIFO. The UARTCharsAvail() function should be called before
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387 //! attempting to call this function.
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389 //*****************************************************************************
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390 #if defined(GROUP_charnonblockingget) || defined(BUILD_ALL) || defined(DOXYGEN)
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392 UARTCharNonBlockingGet(unsigned long ulBase)
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395 // Check the arguments.
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397 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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400 // See if there are any characters in the receive FIFO.
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402 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
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405 // Read and return the next character.
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407 return(HWREG(ulBase + UART_O_DR));
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412 // There are no characters, so return a failure.
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419 //*****************************************************************************
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421 //! Waits for a character from the specified port.
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423 //! \param ulBase is the base address of the UART port.
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425 //! Gets a character from the receive FIFO for the specified port. If there
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426 //! are no characters available, this function will wait until a character is
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427 //! received before returning.
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429 //! \return Returns the character read from the specified port, cast as an
\r
432 //*****************************************************************************
\r
433 #if defined(GROUP_charget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
435 UARTCharGet(unsigned long ulBase)
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438 // Check the arguments.
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440 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
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443 // Wait until a char is available.
\r
445 while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
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450 // Now get the char.
\r
452 return(HWREG(ulBase + UART_O_DR));
\r
456 //*****************************************************************************
\r
458 //! Sends a character to the specified port.
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460 //! \param ulBase is the base address of the UART port.
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461 //! \param ucData is the character to be transmitted.
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463 //! Writes the character \e ucData to the transmit FIFO for the specified port.
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464 //! This function does not block, so if there is no space available, then a
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465 //! \b false is returned, and the application will have to retry the function
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468 //! \return Returns \b true if the character was successfully placed in the
\r
469 //! transmit FIFO, and \b false if there was no space available in the transmit
\r
472 //*****************************************************************************
\r
473 #if defined(GROUP_charnonblockingput) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
475 UARTCharNonBlockingPut(unsigned long ulBase, unsigned char ucData)
\r
478 // Check the arguments.
\r
480 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
483 // See if there is space in the transmit FIFO.
\r
485 if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
\r
488 // Write this character to the transmit FIFO.
\r
490 HWREG(ulBase + UART_O_DR) = ucData;
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500 // There is no space in the transmit FIFO, so return a failure.
\r
507 //*****************************************************************************
\r
509 //! Waits to send a character from the specified port.
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511 //! \param ulBase is the base address of the UART port.
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512 //! \param ucData is the character to be transmitted.
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514 //! Sends the character \e ucData to the transmit FIFO for the specified port.
\r
515 //! If there is no space available in the transmit FIFO, this function will
\r
516 //! wait until there is space available before returning.
\r
520 //*****************************************************************************
\r
521 #if defined(GROUP_charput) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
523 UARTCharPut(unsigned long ulBase, unsigned char ucData)
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526 // Check the arguments.
\r
528 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
531 // Wait until space is available.
\r
533 while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
\r
540 HWREG(ulBase + UART_O_DR) = ucData;
\r
544 //*****************************************************************************
\r
546 //! Causes a BREAK to be sent.
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548 //! \param ulBase is the base address of the UART port.
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549 //! \param bBreakState controls the output level.
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551 //! Calling this function with \e bBreakState set to \b true will assert a
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552 //! break condition on the UART. Calling this function with \e bBreakState set
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553 //! to \b false will remove the break condition. For proper transmission of a
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554 //! break command, the break must be asserted for at least two complete frames.
\r
558 //*****************************************************************************
\r
559 #if defined(GROUP_breakctl) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
561 UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
\r
564 // Check the arguments.
\r
566 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
569 // Set the break condition as requested.
\r
571 HWREG(ulBase + UART_O_LCR_H) =
\r
573 (HWREG(ulBase + UART_O_LCR_H) | UART_LCR_H_BRK) :
\r
574 (HWREG(ulBase + UART_O_LCR_H) & ~(UART_LCR_H_BRK)));
\r
578 //*****************************************************************************
\r
580 //! Registers an interrupt handler for a UART interrupt.
\r
582 //! \param ulBase is the base address of the UART port.
\r
583 //! \param pfnHandler is a pointer to the function to be called when the
\r
584 //! UART interrupt occurs.
\r
586 //! This function does the actual registering of the interrupt handler. This
\r
587 //! will enable the global interrupt in the interrupt controller; specific UART
\r
588 //! interrupts must be enabled via UARTIntEnable(). It is the interrupt
\r
589 //! handler's responsibility to clear the interrupt source.
\r
591 //! \sa IntRegister() for important information about registering interrupt
\r
596 //*****************************************************************************
\r
597 #if defined(GROUP_intregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
599 UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
\r
601 unsigned long ulInt;
\r
604 // Check the arguments.
\r
606 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
609 // Determine the interrupt number based on the UART port.
\r
611 ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;
\r
614 // Register the interrupt handler.
\r
616 IntRegister(ulInt, pfnHandler);
\r
619 // Enable the UART interrupt.
\r
625 //*****************************************************************************
\r
627 //! Unregisters an interrupt handler for a UART interrupt.
\r
629 //! \param ulBase is the base address of the UART port.
\r
631 //! This function does the actual unregistering of the interrupt handler. It
\r
632 //! will clear the handler to be called when a UART interrupt occurs. This
\r
633 //! will also mask off the interrupt in the interrupt controller so that the
\r
634 //! interrupt handler no longer is called.
\r
636 //! \sa IntRegister() for important information about registering interrupt
\r
641 //*****************************************************************************
\r
642 #if defined(GROUP_intunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
644 UARTIntUnregister(unsigned long ulBase)
\r
646 unsigned long ulInt;
\r
649 // Check the arguments.
\r
651 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
654 // Determine the interrupt number based on the UART port.
\r
656 ulInt = (ulBase == UART0_BASE) ? INT_UART0 : INT_UART1;
\r
659 // Disable the interrupt.
\r
664 // Unregister the interrupt handler.
\r
666 IntUnregister(ulInt);
\r
670 //*****************************************************************************
\r
672 //! Enables individual UART interrupt sources.
\r
674 //! \param ulBase is the base address of the UART port.
\r
675 //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
\r
677 //! Enables the indicated UART interrupt sources. Only the sources that are
\r
678 //! enabled can be reflected to the processor interrupt; disabled sources have
\r
679 //! no effect on the processor.
\r
681 //! The parameter \e ulIntFlags is the logical OR of any of the following:
\r
683 //! - UART_INT_OE - Overrun Error interrupt
\r
684 //! - UART_INT_BE - Break Error interrupt
\r
685 //! - UART_INT_PE - Parity Error interrupt
\r
686 //! - UART_INT_FE - Framing Error interrupt
\r
687 //! - UART_INT_RT - Receive Timeout interrupt
\r
688 //! - UART_INT_TX - Transmit interrupt
\r
689 //! - UART_INT_RX - Receive interrupt
\r
693 //*****************************************************************************
\r
694 #if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
696 UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
\r
699 // Check the arguments.
\r
701 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
704 // Enable the specified interrupts.
\r
706 HWREG(ulBase + UART_O_IM) |= ulIntFlags;
\r
710 //*****************************************************************************
\r
712 //! Disables individual UART interrupt sources.
\r
714 //! \param ulBase is the base address of the UART port.
\r
715 //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
\r
717 //! Disables the indicated UART interrupt sources. Only the sources that are
\r
718 //! enabled can be reflected to the processor interrupt; disabled sources have
\r
719 //! no effect on the processor.
\r
721 //! The parameter \e ulIntFlags has the same definition as the same parameter
\r
722 //! to UARTIntEnable().
\r
726 //*****************************************************************************
\r
727 #if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
729 UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
\r
732 // Check the arguments.
\r
734 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
737 // Disable the specified interrupts.
\r
739 HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
\r
743 //*****************************************************************************
\r
745 //! Gets the current interrupt status.
\r
747 //! \param ulBase is the base address of the UART port.
\r
748 //! \param bMasked is false if the raw interrupt status is required and true
\r
749 //! if the masked interrupt status is required.
\r
751 //! This returns the interrupt status for the specified UART. Either the raw
\r
752 //! interrupt status or the status of interrupts that are allowed to reflect to
\r
753 //! the processor can be returned.
\r
755 //! \return The current interrupt status, enumerated as a bit field of
\r
756 //! values described in UARTIntEnable().
\r
758 //*****************************************************************************
\r
759 #if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
761 UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
\r
764 // Check the arguments.
\r
766 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
769 // Return either the interrupt status or the raw interrupt status as
\r
774 return(HWREG(ulBase + UART_O_MIS));
\r
778 return(HWREG(ulBase + UART_O_RIS));
\r
783 //*****************************************************************************
\r
785 //! Clears UART interrupt sources.
\r
787 //! \param ulBase is the base address of the UART port.
\r
788 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
\r
790 //! The specified UART interrupt sources are cleared, so that they no longer
\r
791 //! assert. This must be done in the interrupt handler to keep it from being
\r
792 //! called again immediately upon exit.
\r
794 //! The parameter \e ulIntFlags has the same definition as the same parameter
\r
795 //! to UARTIntEnable().
\r
799 //*****************************************************************************
\r
800 #if defined(GROUP_intclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
802 UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
\r
805 // Check the arguments.
\r
807 ASSERT((ulBase == UART0_BASE) || (ulBase == UART1_BASE));
\r
810 // Clear the requested interrupt sources.
\r
812 HWREG(ulBase + UART_O_ICR) = ulIntFlags;
\r
816 //*****************************************************************************
\r
818 // Close the Doxygen group.
\r
821 //*****************************************************************************
\r