1 //*****************************************************************************
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3 // pwm.c - API for the PWM modules
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 991 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 //! \addtogroup pwm_api
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33 //*****************************************************************************
\r
35 #include "../hw_ints.h"
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36 #include "../hw_memmap.h"
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37 #include "../hw_pwm.h"
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38 #include "../hw_types.h"
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40 #include "interrupt.h"
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43 //*****************************************************************************
\r
45 // Misc macros for manipulating the encoded generator and output defines used
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48 //*****************************************************************************
\r
49 #define PWM_GEN_BADDR(_mod_, _gen_) \
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51 #define PWM_OUT_BADDR(_mod_, _out_) \
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52 ((_mod_) + ((_out_) & 0xFFFFFFC0))
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53 #define PWM_IS_OUTPUT_ODD(_out_) \
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54 ((_out_) & 0x00000001)
\r
56 //*****************************************************************************
\r
58 //! Configures a PWM generator.
\r
60 //! \param ulBase is the base address of the PWM module.
\r
61 //! \param ulGen is the PWM generator to configure. Must be one of
\r
62 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
63 //! \param ulConfig is the configuration for the PWM generator.
\r
65 //! This function is used to set the mode of operation for a PWM generator.
\r
66 //! The counting mode, synchronization mode, and debug behavior are all
\r
67 //! configured. After configuration, the generator is left in the disabled
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70 //! A PWM generator can count in two different modes: count down mode or count
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71 //! up/down mode. In count down mode, it will count from a value down to zero,
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72 //! and then reset to the preset value. This will produce left-aligned PWM
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73 //! signals (i.e. the rising edge of the two PWM signals produced by the
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74 //! generator will occur at the same time). In count up/down mode, it will
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75 //! count up from zero to the preset value, count back down to zero, and then
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76 //! repeat the process. This will produce center-aligned PWM signals (i.e. the
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77 //! middle of the high/low period of the PWM signals produced by the generator
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78 //! will occur at the same time).
\r
80 //! When the PWM generator parameters (period and pulse width) are modified,
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81 //! their affect on the output PWM signals can be delayed. In synchronous
\r
82 //! mode, the parameter updates are not applied until a synchronization event
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83 //! occurs. This allows multiple parameters to be modified and take affect
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84 //! simultaneously, instead of one at a time. Additionally, parameters to
\r
85 //! multiple PWM generators in synchronous mode can be updated simultaneously,
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86 //! allowing them to be treated as if they were a unified generator. In
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87 //! non-synchronous mode, the parameter updates are not delayed until a
\r
88 //! synchronization event. In either mode, the parameter updates only occur
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89 //! when the counter is at zero to help prevent oddly formed PWM signals during
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90 //! the update (i.e. a PWM pulse that is too short or too long).
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92 //! The PWM generator can either pause or continue running when the processor
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93 //! is stopped via the debugger. If configured to pause, it will continue to
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94 //! count until it reaches zero, at which point it will pause until the
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95 //! processor is restarted. If configured to continue running, it will keep
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96 //! counting as if nothing had happened.
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98 //! The \b ulConfig parameter contains the desired configuration. It is the
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99 //! logical OR of the following: \b PWM_GEN_MODE_DOWN or
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100 //! \b PWM_GEN_MODE_UP_DOWN to specify the counting mode, \b PWM_GEN_MODE_SYNC
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101 //! or \b PWM_GEN_MODE_NO_SYNC to specify the synchronization mode, and
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102 //! \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
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105 //! \note Changes to the counter mode will affect the period of the PWM signals
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106 //! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
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107 //! any changes to the counter mode of a generator.
\r
111 //*****************************************************************************
\r
112 #if defined(GROUP_genconfigure) || defined(BUILD_ALL) || defined(DOXYGEN)
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114 PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
\r
115 unsigned long ulConfig)
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118 // Check the arguments.
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120 ASSERT(ulBase == PWM_BASE);
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121 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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122 (ulGen == PWM_GEN_2));
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125 // Compute the generator's base address.
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127 ulGen = PWM_GEN_BADDR(ulBase, ulGen);
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130 // Change the global configuration of the generator.
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132 HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &
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133 ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
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134 PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
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135 PWM_X_CTL_CMPBUPD)) | ulConfig);
\r
138 // Set the individual PWM generator controls.
\r
140 if(ulConfig & PWM_X_CTL_MODE)
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143 // In up/down count mode, set the signal high on up count comparison
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144 // and low on down count comparison (i.e. center align the signals).
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146 HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE <<
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147 PWM_GEN_ACT_A_UP_SHIFT) |
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148 (PWM_GEN_ACT_ZERO <<
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149 PWM_GEN_ACT_A_DN_SHIFT));
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150 HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE <<
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151 PWM_GEN_ACT_B_UP_SHIFT) |
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152 (PWM_GEN_ACT_ZERO <<
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153 PWM_GEN_ACT_B_DN_SHIFT));
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158 // In down count mode, set the signal high on load and low on count
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159 // comparison (i.e. left align the signals).
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161 HWREG(ulGen + PWM_O_X_GENA) = ((PWM_GEN_ACT_ONE <<
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162 PWM_GEN_ACT_LOAD_SHIFT) |
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163 (PWM_GEN_ACT_ZERO <<
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164 PWM_GEN_ACT_A_DN_SHIFT));
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165 HWREG(ulGen + PWM_O_X_GENB) = ((PWM_GEN_ACT_ONE <<
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166 PWM_GEN_ACT_LOAD_SHIFT) |
\r
167 (PWM_GEN_ACT_ZERO <<
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168 PWM_GEN_ACT_B_DN_SHIFT));
\r
173 //*****************************************************************************
\r
175 //! Set the period of a PWM generator.
\r
177 //! \param ulBase is the base address of the PWM module.
\r
178 //! \param ulGen is the PWM generator to be modified. Must be one of
\r
179 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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180 //! \param ulPeriod specifies the period of PWM generator output, measured
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181 //! in clock ticks.
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183 //! This function sets the period of the specified PWM generator block, where
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184 //! the period of the generator block is defined as the number of \b PWM
\r
185 //! clock ticks between pulses on the generator block \b zero signal.
\r
187 //! \note Any subsequent calls made to this function before an update occurs
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188 //! will cause the previous values to be overwritten.
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192 //*****************************************************************************
\r
193 #if defined(GROUP_genperiodset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
195 PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
\r
196 unsigned long ulPeriod)
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199 // Check the arguments.
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201 ASSERT(ulBase == PWM_BASE);
\r
202 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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203 (ulGen == PWM_GEN_2));
\r
206 // Compute the generator's base address.
\r
208 ulGen = PWM_GEN_BADDR(ulBase, ulGen);
\r
211 // Set the reload register based on the mode.
\r
213 if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
\r
216 // In up/down count mode, set the reload register to half the requested
\r
219 ASSERT((ulPeriod / 2) < 65536);
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220 HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;
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225 // In down count mode, set the reload register to the requested period
\r
228 ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));
\r
229 HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;
\r
234 //*****************************************************************************
\r
236 //! Gets the period of a PWM generator block.
\r
238 //! \param ulBase is the base address of the PWM module.
\r
239 //! \param ulGen is the PWM generator to query. Must be one of
\r
240 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
242 //! This function gets the period of the specified PWM generator block. The
\r
243 //! period of the generator block is defined as the number of \b PWM clock
\r
244 //! ticks between pulses on the generator block \b zero signal.
\r
246 //! If the update of the counter for the specified PWM generator has yet
\r
247 //! to be completed, the value returned may not be the active period. The
\r
248 //! value returned is the programmed period, measured in \b PWM clock ticks.
\r
250 //! \return Returns the programmed period of the specified generator block
\r
251 //! in \b PWM clock ticks.
\r
253 //*****************************************************************************
\r
254 #if defined(GROUP_genperiodget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
256 PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)
\r
259 // Check the arguments.
\r
261 ASSERT(ulBase == PWM_BASE);
\r
262 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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263 (ulGen == PWM_GEN_2));
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266 // Compute the generator's base address.
\r
268 ulGen = PWM_GEN_BADDR(ulBase, ulGen);
\r
271 // Figure out the counter mode.
\r
273 if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
\r
276 // The period is twice the reload register value.
\r
278 return(HWREG(ulGen + PWM_O_X_LOAD) * 2);
\r
283 // The period is the reload register value plus one.
\r
285 return(HWREG(ulGen + PWM_O_X_LOAD) + 1);
\r
290 //*****************************************************************************
\r
292 //! Enables the timer/counter for a PWM generator block.
\r
294 //! \param ulBase is the base address of the PWM module.
\r
295 //! \param ulGen is the PWM generator to be enabled. Must be one of
\r
296 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
298 //! This function allows the \b PWM clock to drive the timer/counter for the
\r
299 //! specified generator block.
\r
303 //*****************************************************************************
\r
304 #if defined(GROUP_genenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
306 PWMGenEnable(unsigned long ulBase, unsigned long ulGen)
\r
309 // Check the arguments.
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311 ASSERT(ulBase == PWM_BASE);
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312 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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313 (ulGen == PWM_GEN_2));
\r
316 // Enable the PWM generator.
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318 HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
\r
322 //*****************************************************************************
\r
324 //! Disables the timer/counter for a PWM generator block.
\r
326 //! \param ulBase is the base address of the PWM module.
\r
327 //! \param ulGen is the PWM generator to be disabled. Must be one of
\r
328 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
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330 //! This function blocks the \b PWM clock from driving the timer/counter for
\r
331 //! the specified generator block.
\r
335 //*****************************************************************************
\r
336 #if defined(GROUP_gendisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
338 PWMGenDisable(unsigned long ulBase, unsigned long ulGen)
\r
341 // Check the arguments.
\r
343 ASSERT(ulBase == PWM_BASE);
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344 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
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345 (ulGen == PWM_GEN_2));
\r
348 // Disable the PWM generator.
\r
350 HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);
\r
354 //*****************************************************************************
\r
356 //! Sets the pulse width for the specified PWM output.
\r
358 //! \param ulBase is the base address of the PWM module.
\r
359 //! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,
\r
360 //! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5.
\r
361 //! \param ulWidth specifies the width of the positive portion of the pulse.
\r
363 //! This function sets the pulse width for the specified PWM output, where the
\r
364 //! pulse width is defined as the number of \b PWM clock ticks.
\r
366 //! \note Any subsequent calls made to this function before an update occurs
\r
367 //! will cause the previous values to be overwritten.
\r
371 //*****************************************************************************
\r
372 #if defined(GROUP_pulsewidthset) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
374 PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
\r
375 unsigned long ulWidth)
\r
377 unsigned long ulGenBase, ulReg;
\r
380 // Check the arguments.
\r
382 ASSERT(ulBase == PWM_BASE);
\r
383 ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
\r
384 (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
\r
385 (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5));
\r
388 // Compute the generator's base address.
\r
390 ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
\r
393 // If the counter is in up/down count mode, divide the width by two.
\r
395 if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
\r
403 ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);
\r
406 // Make sure the width is not too large.
\r
408 ASSERT(ulWidth < ulReg);
\r
411 // Compute the compare value.
\r
413 ulReg = ulReg - ulWidth;
\r
416 // Write to the appropriate registers.
\r
418 if(PWM_IS_OUTPUT_ODD(ulPWMOut))
\r
420 HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;
\r
424 HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;
\r
429 //*****************************************************************************
\r
431 //! Gets the pulse width of a PWM output.
\r
433 //! \param ulBase is the base address of the PWM module.
\r
434 //! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,
\r
435 //! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, or \b PWM_OUT_5.
\r
437 //! This function gets the currently programmed pulse width for the
\r
438 //! specified PWM output. If the update of the comparator for the specified
\r
439 //! output has yet to be completed, the value returned may not be the active
\r
440 //! pulse width. The value returned is the programmed pulse width, measured
\r
441 //! in \b PWM clock ticks.
\r
443 //! \return Returns the width of the pulse in \b PWM clock ticks.
\r
445 //*****************************************************************************
\r
446 #if defined(GROUP_pulsewidthget) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
448 PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)
\r
450 unsigned long ulGenBase, ulReg, ulLoad;
\r
453 // Check the arguments.
\r
455 ASSERT(ulBase == PWM_BASE);
\r
456 ASSERT((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
\r
457 (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
\r
458 (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5));
\r
461 // Compute the generator's base address.
\r
463 ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
\r
466 // Then compute the pulse width. If mode is UpDown, set
\r
467 // width = (load-compare)*2. Otherwise, set width = load - compare
\r
469 ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);
\r
470 if(PWM_IS_OUTPUT_ODD(ulPWMOut))
\r
472 ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);
\r
476 ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);
\r
478 ulReg = ulLoad - ulReg;
\r
481 // If in up/down count mode, double the pulse width.
\r
483 if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
\r
489 // Return the pulse width.
\r
495 //*****************************************************************************
\r
497 //! Enables the PWM dead band output, and sets the dead band delays.
\r
499 //! \param ulBase is the base address of the PWM module.
\r
500 //! \param ulGen is the PWM generator to modify. Must be one of
\r
501 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
502 //! \param usRise specifies the width of delay from the rising edge.
\r
503 //! \param usFall specifies the width of delay from the falling edge.
\r
505 //! This function sets the dead bands for the specified PWM generator,
\r
506 //! where the dead bands are defined as the number of \b PWM clock ticks
\r
507 //! from the rising or falling edge of the generator's \b OutA signal.
\r
508 //! Note that this function causes the coupling of \b OutB to \b OutA.
\r
512 //*****************************************************************************
\r
513 #if defined(GROUP_deadbandenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
515 PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
\r
516 unsigned short usRise, unsigned short usFall)
\r
519 // Check the arguments.
\r
521 ASSERT(ulBase == PWM_BASE);
\r
522 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
523 (ulGen == PWM_GEN_2));
\r
524 ASSERT(usRise < 4096);
\r
525 ASSERT(usFall < 4096);
\r
528 // Compute the generator's base address.
\r
530 ulGen = PWM_GEN_BADDR(ulBase, ulGen);
\r
533 // Write the dead band delay values.
\r
535 HWREG(ulGen + PWM_O_X_DBRISE) = usRise;
\r
536 HWREG(ulGen + PWM_O_X_DBFALL) = usFall;
\r
539 // Enable the deadband functionality.
\r
541 HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_DBCTL_ENABLE;
\r
545 //*****************************************************************************
\r
547 //! Disables the PWM dead band output.
\r
549 //! \param ulBase is the base address of the PWM module.
\r
550 //! \param ulGen is the PWM generator to modify. Must be one of
\r
551 //! \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
553 //! This function disables the dead band mode for the specified PWM generator.
\r
554 //! Doing so decouples the \b OutA and \b OutB signals.
\r
558 //*****************************************************************************
\r
559 #if defined(GROUP_deadbanddisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
561 PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)
\r
564 // Check the arguments.
\r
566 ASSERT(ulBase == PWM_BASE);
\r
567 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
568 (ulGen == PWM_GEN_2));
\r
571 // Disable the deadband functionality.
\r
573 HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &= ~(PWM_DBCTL_ENABLE);
\r
577 //*****************************************************************************
\r
579 //! Synchronizes all pending updates.
\r
581 //! \param ulBase is the base address of the PWM module.
\r
582 //! \param ulGenBits are the PWM generator blocks to be updated. Must be the
\r
583 //! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or
\r
584 //! \b PWM_GEN_2_BIT.
\r
586 //! For the selected PWM generators, this function causes all queued updates to
\r
587 //! the period or pulse width to be applied the next time the corresponding
\r
588 //! counter becomes zero.
\r
592 //*****************************************************************************
\r
593 #if defined(GROUP_syncupdate) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
595 PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)
\r
598 // Check the arguments.
\r
600 ASSERT(ulBase == PWM_BASE);
\r
601 ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT)));
\r
604 // Update the PWM timing registers.
\r
606 HWREG(ulBase + PWM_O_CTL) = ulGenBits;
\r
610 //*****************************************************************************
\r
612 //! Synchronizes the counters in one or multiple PWM generator blocks.
\r
614 //! \param ulBase is the base address of the PWM module.
\r
615 //! \param ulGenBits are the PWM generator blocks to be synchronized. Must be
\r
616 //! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT, or
\r
617 //! \b PWM_GEN_2_BIT.
\r
619 //! For the selected PWM module, this function synchronizes the time base
\r
620 //! of the generator blocks by causing the specified generator counters to be
\r
625 //*****************************************************************************
\r
626 #if defined(GROUP_synctimebase) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
628 PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)
\r
631 // Check the arguments.
\r
633 ASSERT(ulBase == PWM_BASE);
\r
634 ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT)));
\r
637 // Synchronize the counters in the specified generators by writing to
\r
638 // the module's synchronization register.
\r
640 HWREG(ulBase + PWM_O_SYNC) = ulGenBits;
\r
644 //*****************************************************************************
\r
646 //! Enables or disables PWM outputs.
\r
648 //! \param ulBase is the base address of the PWM module.
\r
649 //! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
\r
650 //! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
\r
651 //! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.
\r
652 //! \param bEnable determines if the signal is enabled or disabled.
\r
654 //! This function is used to enable or disable the selected PWM outputs. The
\r
655 //! outputs are selected using the parameter \e ulPWMOutBits. The parameter
\r
656 //! \e bEnable determines the state of the selected outputs. If \e bEnable is
\r
657 //! \b true, then the selected PWM outputs are enabled, or placed in the active
\r
658 //! state. If \e bEnable is \b false, then the selected outputs are disabled,
\r
659 //! or placed in the inactive state.
\r
663 //*****************************************************************************
\r
664 #if defined(GROUP_outputstate) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
666 PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
\r
670 // Check the arguments.
\r
672 ASSERT(ulBase == PWM_BASE);
\r
673 ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
\r
674 PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));
\r
677 // Read the module's ENABLE output control register, and set or clear
\r
678 // the requested bits.
\r
680 if(bEnable == true)
\r
682 HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;
\r
686 HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);
\r
691 //*****************************************************************************
\r
693 //! Selects the inversion mode for PWM outputs.
\r
695 //! \param ulBase is the base address of the PWM module.
\r
696 //! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
\r
697 //! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
\r
698 //! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.
\r
699 //! \param bInvert determines if the signal is inverted or passed through.
\r
701 //! This function is used to select the inversion mode for the selected PWM
\r
702 //! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
\r
703 //! The parameter \e bInvert determines the inversion mode for the selected
\r
704 //! outputs. If \e bInvert is \b true, this function will cause the specified
\r
705 //! PWM output signals to be inverted, or made active low. If \e bInvert is
\r
706 //! \b false, the specified output will be passed through as is, or be made
\r
711 //*****************************************************************************
\r
712 #if defined(GROUP_outputinvert) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
714 PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
\r
718 // Check the arguments.
\r
720 ASSERT(ulBase == PWM_BASE);
\r
721 ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
\r
722 PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));
\r
725 // Read the module's INVERT output control register, and set or clear
\r
726 // the requested bits.
\r
728 if(bInvert == true)
\r
730 HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;
\r
734 HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);
\r
739 //*****************************************************************************
\r
741 //! Specifies the state of PWM outputs in response to a fault condition.
\r
743 //! \param ulBase is the base address of the PWM module.
\r
744 //! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
\r
745 //! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
\r
746 //! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, or \b PWM_OUT_5_BIT.
\r
747 //! \param bFaultKill determines if the signal is killed or passed through
\r
748 //! during an active fault condition.
\r
750 //! This function sets the fault handling characteristics of the selected PWM
\r
751 //! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
\r
752 //! The parameter \e bFaultKill determines the fault handling characteristics
\r
753 //! for the selected outputs. If \e bFaultKill is \b true, then the selected
\r
754 //! outputs will be made inactive. If \e bFaultKill is \b false, then the
\r
755 //! selected outputs are unaffected by the detected fault.
\r
759 //*****************************************************************************
\r
760 #if defined(GROUP_outputfault) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
762 PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
\r
763 tBoolean bFaultKill)
\r
766 // Check the arguments.
\r
768 ASSERT(ulBase == PWM_BASE);
\r
769 ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
\r
770 PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT)));
\r
773 // Read the module's FAULT output control register, and set or clear
\r
774 // the requested bits.
\r
776 if(bFaultKill == true)
\r
778 HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;
\r
782 HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);
\r
787 //*****************************************************************************
\r
789 //! Registers an interrupt handler for the specified PWM generator block.
\r
791 //! \param ulBase is the base address of the PWM module.
\r
792 //! \param ulGen is the PWM generator in question.
\r
793 //! \param pfnIntHandler is a pointer to the function to be called when the PWM
\r
794 //! generator interrupt occurs.
\r
796 //! This function will ensure that the interrupt handler specified by
\r
797 //! \e pfnIntHandler is called when an interrupt is detected for the specified
\r
798 //! PWM generator block. This function will also enable the corresponding
\r
799 //! PWM generator interrupt in the interrupt controller; individual generator
\r
800 //! interrupts and interrupt sources must be enabled with PWMIntEnable() and
\r
801 //! PWMGenIntTrigEnable().
\r
803 //! \sa IntRegister() for important information about registering interrupt
\r
808 //*****************************************************************************
\r
809 #if defined(GROUP_genintregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
811 PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
\r
812 void (*pfnIntHandler)(void))
\r
814 unsigned long ulInt;
\r
817 // Check the arguments.
\r
819 ASSERT(ulBase == PWM_BASE);
\r
820 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
821 (ulGen == PWM_GEN_2));
\r
824 // Get the interrupt number associated with the specified generator.
\r
826 ulInt = INT_PWM0 + (ulGen >> 6) - 1;
\r
829 // Register the interrupt handler.
\r
831 IntRegister(ulInt, pfnIntHandler);
\r
834 // Enable the PWMx interrupt.
\r
840 //*****************************************************************************
\r
842 //! Removes an interrupt handler for the specified PWM generator block.
\r
844 //! \param ulBase is the base address of the PWM module.
\r
845 //! \param ulGen is the PWM generator in question.
\r
847 //! This function will unregister the interrupt handler for the specified
\r
848 //! PWM generator block. This function will also disable the corresponding
\r
849 //! PWM generator interrupt in the interrupt controller; individual generator
\r
850 //! interrupts and interrupt sources must be disabled with PWMIntDisable() and
\r
851 //! PWMGenIntTrigDisable().
\r
853 //! \sa IntRegister() for important information about registering interrupt
\r
858 //*****************************************************************************
\r
859 #if defined(GROUP_genintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
861 PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)
\r
863 unsigned long ulInt;
\r
866 // Check the arguments.
\r
868 ASSERT(ulBase == PWM_BASE);
\r
869 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
870 (ulGen == PWM_GEN_2));
\r
873 // Get the interrupt number associated with the specified generator.
\r
875 ulInt = INT_PWM0 + (ulGen >> 6) - 1;
\r
878 // Disable the PWMx interrupt.
\r
883 // Unregister the interrupt handler.
\r
885 IntUnregister(ulInt);
\r
889 //*****************************************************************************
\r
891 //! Registers an interrupt handler for a fault condition detected in a PWM
\r
894 //! \param ulBase is the base address of the PWM module.
\r
895 //! \param pfnIntHandler is a pointer to the function to be called when the PWM
\r
896 //! fault interrupt occurs.
\r
898 //! This function will ensure that the interrupt handler specified by
\r
899 //! \e pfnIntHandler is called when a fault interrupt is detected for the
\r
900 //! selected PWM module. This function will also enable the PWM fault
\r
901 //! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
\r
902 //! module level using PWMIntEnable().
\r
904 //! \sa IntRegister() for important information about registering interrupt
\r
909 //*****************************************************************************
\r
910 #if defined(GROUP_faultintregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
912 PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))
\r
915 // Check the arguments.
\r
917 ASSERT(ulBase == PWM_BASE);
\r
920 // Register the interrupt handler, returning an error if one occurs.
\r
922 IntRegister(INT_PWM_FAULT, pfnIntHandler);
\r
925 // Enable the PWM fault interrupt.
\r
927 IntEnable(INT_PWM_FAULT);
\r
931 //*****************************************************************************
\r
933 //! Removes the PWM fault condition interrupt handler.
\r
935 //! \param ulBase is the base address of the PWM module.
\r
937 //! This function will remove the interrupt handler for a PWM fault interrupt
\r
938 //! from the selected PWM module. This function will also disable the PWM
\r
939 //! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
\r
940 //! at the module level using PWMIntDisable().
\r
942 //! \sa IntRegister() for important information about registering interrupt
\r
947 //*****************************************************************************
\r
948 #if defined(GROUP_faultintunregister) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
950 PWMFaultIntUnregister(unsigned long ulBase)
\r
953 // Check the arguments.
\r
955 ASSERT(ulBase == PWM_BASE);
\r
958 // Disable the PWM fault interrupt.
\r
960 IntDisable(INT_PWM_FAULT);
\r
963 // Unregister the interrupt handler, returning an error if one occurs.
\r
965 IntUnregister(INT_PWM_FAULT);
\r
969 //*****************************************************************************
\r
971 //! Enables interrupts and triggers for the specified PWM generator block.
\r
973 //! \param ulBase is the base address of the PWM module.
\r
974 //! \param ulGen is the PWM generator to have interrupts and triggers enabled.
\r
975 //! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
976 //! \param ulIntTrig specifies the interrupts and triggers to be enabled.
\r
978 //! Unmasks the specified interrupt(s) and trigger(s) by setting the
\r
979 //! specified bits of the interrupt/trigger enable register for the specified
\r
980 //! PWM generator. The defined values for the bits are as follows:
\r
982 //! - PWM_INT_CNT_ZERO
\r
983 //! - PWM_INT_CNT_LOAD
\r
984 //! - PWM_INT_CMP_AU
\r
985 //! - PWM_INT_CMP_AD
\r
986 //! - PWM_INT_CMP_BU
\r
987 //! - PWM_INT_CMP_BD
\r
988 //! - PWM_TR_CNT_ZERO
\r
989 //! - PWM_TR_CNT_LOAD
\r
990 //! - PWM_TR_CMP_AU
\r
991 //! - PWM_TR_CMP_AD
\r
992 //! - PWM_TR_CMP_BU
\r
993 //! - PWM_TR_CMP_BD
\r
997 //*****************************************************************************
\r
998 #if defined(GROUP_geninttrigenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1000 PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
\r
1001 unsigned long ulIntTrig)
\r
1004 // Check the arguments.
\r
1006 ASSERT(ulBase == PWM_BASE);
\r
1007 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
1008 (ulGen == PWM_GEN_2));
\r
1011 // Enable the specified interrupts/triggers.
\r
1013 HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;
\r
1017 //*****************************************************************************
\r
1019 //! Disables interrupts for the specified PWM generator block.
\r
1021 //! \param ulBase is the base address of the PWM module.
\r
1022 //! \param ulGen is the PWM generator to have interrupts and triggers disabled.
\r
1023 //! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, or \b PWM_GEN_2.
\r
1024 //! \param ulIntTrig specifies the interrupts and triggers to be disabled.
\r
1026 //! Masks the specified interrupt(s) and trigger(s) by clearing the
\r
1027 //! specified bits of the interrupt/trigger enable register for the specified
\r
1028 //! PWM generator. The defined values for the bits are as follows:
\r
1030 //! - PWM_INT_CNT_ZERO
\r
1031 //! - PWM_INT_CNT_LOAD
\r
1032 //! - PWM_INT_CMP_AU
\r
1033 //! - PWM_INT_CMP_AD
\r
1034 //! - PWM_INT_CMP_BU
\r
1035 //! - PWM_INT_CMP_BD
\r
1036 //! - PWM_TR_CNT_ZERO
\r
1037 //! - PWM_TR_CNT_LOAD
\r
1038 //! - PWM_TR_CMP_AU
\r
1039 //! - PWM_TR_CMP_AD
\r
1040 //! - PWM_TR_CMP_BU
\r
1041 //! - PWM_TR_CMP_BD
\r
1045 //*****************************************************************************
\r
1046 #if defined(GROUP_geninttrigdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1048 PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
\r
1049 unsigned long ulIntTrig)
\r
1052 // Check the arguments.
\r
1054 ASSERT(ulBase == PWM_BASE);
\r
1055 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
1056 (ulGen == PWM_GEN_2));
\r
1059 // Disable the specified interrupts/triggers.
\r
1061 HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);
\r
1065 //*****************************************************************************
\r
1067 //! Gets interrupt status for the specified PWM generator block.
\r
1069 //! \param ulBase is the base address of the PWM module.
\r
1070 //! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
\r
1071 //! \b PWM_GEN_1, or \b PWM_GEN_2.
\r
1072 //! \param bMasked specifies whether masked or raw interrupt status is
\r
1075 //! If \e bMasked is set as \b true, then the masked interrupt status is
\r
1076 //! returned; otherwise, the raw interrupt status will be returned.
\r
1078 //! \return Returns the contents of the interrupt status register, or the
\r
1079 //! contents of the raw interrupt status register, for the specified
\r
1080 //! PWM generator.
\r
1082 //*****************************************************************************
\r
1083 #if defined(GROUP_genintstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1085 PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
\r
1088 // Check the arguments.
\r
1090 ASSERT(ulBase == PWM_BASE);
\r
1091 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
1092 (ulGen == PWM_GEN_2));
\r
1095 // Compute the generator's base address.
\r
1097 ulGen = PWM_GEN_BADDR(ulBase, ulGen);
\r
1100 // Read and return the specified generator's raw or enabled interrupt
\r
1103 if(bMasked == true)
\r
1105 return(HWREG(ulGen + PWM_O_X_ISC));
\r
1109 return(HWREG(ulGen + PWM_O_X_RIS));
\r
1114 //*****************************************************************************
\r
1116 //! Clears the specified interrupt(s) for the specified PWM generator block.
\r
1118 //! \param ulBase is the base address of the PWM module.
\r
1119 //! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
\r
1120 //! \b PWM_GEN_1, or \b PWM_GEN_2.
\r
1121 //! \param ulInts specifies the interrupts to be cleared.
\r
1123 //! Clears the specified interrupt(s) by writing a 1 to the specified bits
\r
1124 //! of the interrupt status register for the specified PWM generator. The
\r
1125 //! defined values for the bits are as follows:
\r
1127 //! - PWM_INT_CNT_ZERO
\r
1128 //! - PWM_INT_CNT_LOAD
\r
1129 //! - PWM_INT_CMP_AU
\r
1130 //! - PWM_INT_CMP_AD
\r
1131 //! - PWM_INT_CMP_BU
\r
1132 //! - PWM_INT_CMP_BD
\r
1136 //*****************************************************************************
\r
1137 #if defined(GROUP_genintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1139 PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)
\r
1142 // Check the arguments.
\r
1144 ASSERT(ulBase == PWM_BASE);
\r
1145 ASSERT((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
\r
1146 (ulGen == PWM_GEN_2));
\r
1149 // Clear the requested interrupts by writing ones to the specified bit
\r
1150 // of the module's interrupt enable register.
\r
1152 HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;
\r
1156 //*****************************************************************************
\r
1158 //! Enables generator and fault interrupts for a PWM module.
\r
1160 //! \param ulBase is the base address of the PWM module.
\r
1161 //! \param ulGenFault contains the interrupts to be enabled. Must be a logical
\r
1162 //! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, or
\r
1163 //! \b PWM_INT_FAULT.
\r
1165 //! Unmasks the specified interrupt(s) by setting the specified bits of
\r
1166 //! the interrupt enable register for the selected PWM module.
\r
1170 //*****************************************************************************
\r
1171 #if defined(GROUP_intenable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1173 PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)
\r
1176 // Check the arguments.
\r
1178 ASSERT(ulBase == PWM_BASE);
\r
1181 // Read the module's interrupt enable register, and enable interrupts
\r
1182 // for the specified PWM generators.
\r
1184 HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;
\r
1188 //*****************************************************************************
\r
1190 //! Disables generator and fault interrupts for a PWM module.
\r
1192 //! \param ulBase is the base address of the PWM module.
\r
1193 //! \param ulGenFault contains the interrupts to be disabled. Must be a
\r
1194 //! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
\r
1195 //! or \b PWM_INT_FAULT.
\r
1197 //! Masks the specified interrupt(s) by clearing the specified bits of
\r
1198 //! the interrupt enable register for the selected PWM module.
\r
1202 //*****************************************************************************
\r
1203 #if defined(GROUP_intdisable) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1205 PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
\r
1208 // Check the arguments.
\r
1210 ASSERT(ulBase == PWM_BASE);
\r
1213 // Read the module's interrupt enable register, and disable interrupts
\r
1214 // for the specified PWM generators.
\r
1216 HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);
\r
1220 //*****************************************************************************
\r
1222 //! Clears the fault interrupt for a PWM module.
\r
1224 //! \param ulBase is the base address of the PWM module.
\r
1226 //! Clears the fault interrupt by writing to the appropriate bit of the
\r
1227 //! interrupt status register for the selected PWM module.
\r
1231 //*****************************************************************************
\r
1232 #if defined(GROUP_faultintclear) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1234 PWMFaultIntClear(unsigned long ulBase)
\r
1237 // Check the arguments.
\r
1239 ASSERT(ulBase == PWM_BASE);
\r
1242 // Write the only writeable bit in the module's interrupt register.
\r
1244 HWREG(ulBase + PWM_O_ISC) = PWM_INT_INTFAULT;
\r
1248 //*****************************************************************************
\r
1250 //! Gets the interrupt status for a PWM module.
\r
1252 //! \param ulBase is the base address of the PWM module.
\r
1253 //! \param bMasked specifies whether masked or raw interrupt status is
\r
1256 //! If \e bMasked is set as \b true, then the masked interrupt status is
\r
1257 //! returned; otherwise, the raw interrupt status will be returned.
\r
1259 //! \return The current interrupt status, enumerated as a bit field of
\r
1260 //! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, and \b PWM_INT_FAULT.
\r
1262 //*****************************************************************************
\r
1263 #if defined(GROUP_intstatus) || defined(BUILD_ALL) || defined(DOXYGEN)
\r
1265 PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
\r
1268 // Check the arguments.
\r
1270 ASSERT(ulBase == PWM_BASE);
\r
1273 // Read and return either the module's raw or enabled interrupt status.
\r
1275 if(bMasked == true)
\r
1277 return(HWREG(ulBase + PWM_O_ISC));
\r
1281 return(HWREG(ulBase + PWM_O_RIS));
\r
1286 //*****************************************************************************
\r
1288 // Close the Doxygen group.
\r
1291 //*****************************************************************************
\r