2 FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.
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4 ***************************************************************************
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8 * + New to FreeRTOS, *
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10 * + Looking for basic training, *
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11 * + Wanting to improve your FreeRTOS skills and productivity *
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13 * then take a look at the FreeRTOS books - available as PDF or paperback *
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15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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16 * http://www.FreeRTOS.org/Documentation *
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18 * A pdf reference manual is also available. Both are usually delivered *
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19 * to your inbox within 20 minutes to two hours when purchased between 8am *
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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54 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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56 /* Kernel includes. */
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57 #include "FreeRTOS.h"
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61 /* Hardware specific includes. */
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62 #include "EthDev_LPC17xx.h"
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64 /* Time to wait between each inspection of the link status. */
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65 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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67 /* Short delay used in several places during the initialisation process. */
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68 #define emacSHORT_DELAY ( 2 )
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70 /* Hardware specific bit definitions. */
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71 #define emacLINK_ESTABLISHED ( 0x0001 )
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72 #define emacFULL_DUPLEX_ENABLED ( 0x0004 )
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73 #define emac10BASE_T_MODE ( 0x0002 )
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74 #define emacPINSEL2_VALUE 0x50150105
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76 /* If no buffers are available, then wait this long before looking again.... */
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77 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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79 /* ...and don't look more than this many times. */
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80 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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82 /* Index to the Tx descriptor that is always used first for every Tx. The second
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83 descriptor is then used to re-send in order to speed up the uIP Tx process. */
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84 #define emacTX_DESC_INDEX ( 0 )
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86 #define PCONP_PCENET 0x40000000
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87 /*-----------------------------------------------------------*/
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90 * Configure both the Rx and Tx descriptors during the init process.
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92 static void prvInitDescriptors( void );
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95 * Setup the IO and peripherals required for Ethernet communication.
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97 static void prvSetupEMACHardware( void );
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100 * Control the auto negotiate process.
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102 static void prvConfigurePHY( void );
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105 * Wait for a link to be established, then setup the PHY according to the link
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108 static long prvSetupLinkStatus( void );
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111 * Search the pool of buffers to find one that is free. If a buffer is found
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112 * mark it as in use before returning its address.
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114 static unsigned char *prvGetNextBuffer( void );
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117 * Return an allocated buffer to the pool of free buffers.
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119 static void prvReturnBuffer( unsigned char *pucBuffer );
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122 * Send lValue to the lPhyReg within the PHY.
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124 static long prvWritePHY( long lPhyReg, long lValue );
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127 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
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128 * pdFALSE if there is an error.
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130 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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132 /*-----------------------------------------------------------*/
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134 /* The semaphore used to wake the uIP task when data arrives. */
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135 extern xSemaphoreHandle xEMACSemaphore;
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137 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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138 If the index contains a 1 then the buffer within pool is in use, if it
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139 contains a 0 then the buffer is free. */
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140 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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142 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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143 allocated within this file. */
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144 unsigned char * uip_buf;
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146 /* Store the length of the data being sent so the data can be sent twice. The
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147 value will be set back to 0 once the data has been sent twice. */
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148 static unsigned short usSendLen = 0;
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150 /*-----------------------------------------------------------*/
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152 long lEMACInit( void )
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154 long lReturn = pdPASS;
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155 unsigned long ulID1, ulID2;
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157 /* Reset peripherals, configure port pins and registers. */
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158 prvSetupEMACHardware();
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160 /* Check the PHY part number is as expected. */
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161 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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162 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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163 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
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165 /* Set the Ethernet MAC Address registers */
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166 LPC_EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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167 LPC_EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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168 LPC_EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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170 /* Initialize Tx and Rx DMA Descriptors */
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171 prvInitDescriptors();
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173 /* Receive broadcast and perfect match packets */
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174 LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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176 /* Setup the PHY. */
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184 /* Check the link status. */
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185 if( lReturn == pdPASS )
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187 lReturn = prvSetupLinkStatus();
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190 if( lReturn == pdPASS )
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192 /* Initialise uip_buf to ensure it points somewhere valid. */
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193 uip_buf = prvGetNextBuffer();
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195 /* Reset all interrupts */
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196 LPC_EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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198 /* Enable receive and transmit mode of MAC Ethernet core */
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199 LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
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200 LPC_EMAC->MAC1 |= MAC1_REC_EN;
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205 /*-----------------------------------------------------------*/
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207 static unsigned char *prvGetNextBuffer( void )
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210 unsigned char *pucReturn = NULL;
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211 unsigned long ulAttempts = 0;
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213 while( pucReturn == NULL )
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215 /* Look through the buffers to find one that is not in use by
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217 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
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219 if( ucBufferInUse[ x ] == pdFALSE )
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221 ucBufferInUse[ x ] = pdTRUE;
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222 pucReturn = ( unsigned char * ) ETH_BUF( x );
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227 /* Was a buffer found? */
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228 if( pucReturn == NULL )
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232 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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237 /* Wait then look again. */
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238 vTaskDelay( emacBUFFER_WAIT_DELAY );
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244 /*-----------------------------------------------------------*/
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246 static void prvInitDescriptors( void )
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248 long x, lNextBuffer = 0;
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250 for( x = 0; x < NUM_RX_FRAG; x++ )
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252 /* Allocate the next Ethernet buffer to this descriptor. */
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253 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
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254 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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255 RX_STAT_INFO( x ) = 0;
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256 RX_STAT_HASHCRC( x ) = 0;
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258 /* The Ethernet buffer is now in use. */
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259 ucBufferInUse[ lNextBuffer ] = pdTRUE;
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263 /* Set EMAC Receive Descriptor Registers. */
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264 LPC_EMAC->RxDescriptor = RX_DESC_BASE;
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265 LPC_EMAC->RxStatus = RX_STAT_BASE;
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266 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
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268 /* Rx Descriptors Point to 0 */
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269 LPC_EMAC->RxConsumeIndex = 0;
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271 /* A buffer is not allocated to the Tx descriptors until they are actually
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273 for( x = 0; x < NUM_TX_FRAG; x++ )
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275 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
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276 TX_DESC_CTRL( x ) = 0;
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277 TX_STAT_INFO( x ) = 0;
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280 /* Set EMAC Transmit Descriptor Registers. */
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281 LPC_EMAC->TxDescriptor = TX_DESC_BASE;
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282 LPC_EMAC->TxStatus = TX_STAT_BASE;
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283 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
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285 /* Tx Descriptors Point to 0 */
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286 LPC_EMAC->TxProduceIndex = 0;
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288 /*-----------------------------------------------------------*/
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290 static void prvSetupEMACHardware( void )
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295 /* Enable P1 Ethernet Pins. */
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296 LPC_PINCON->PINSEL2 = emacPINSEL2_VALUE;
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297 LPC_PINCON->PINSEL3 = ( LPC_PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
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299 /* Power Up the EMAC controller. */
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300 LPC_SC->PCONP |= PCONP_PCENET;
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301 vTaskDelay( emacSHORT_DELAY );
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303 /* Reset all EMAC internal modules. */
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304 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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305 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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307 /* A short delay after reset. */
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308 vTaskDelay( emacSHORT_DELAY );
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310 /* Initialize MAC control registers. */
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311 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
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312 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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313 LPC_EMAC->MAXF = ETH_MAX_FLEN;
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314 LPC_EMAC->CLRT = CLRT_DEF;
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315 LPC_EMAC->IPGR = IPGR_DEF;
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317 /* Enable Reduced MII interface. */
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318 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
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320 /* Reset Reduced MII Logic. */
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321 LPC_EMAC->SUPP = SUPP_RES_RMII;
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322 vTaskDelay( emacSHORT_DELAY );
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323 LPC_EMAC->SUPP = 0;
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325 /* Put the PHY in reset mode */
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326 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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327 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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329 /* Wait for hardware reset to end. */
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330 for( x = 0; x < 100; x++ )
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332 vTaskDelay( emacSHORT_DELAY * 5 );
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333 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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334 if( !( us & MCFG_RES_MII ) )
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336 /* Reset complete */
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341 /*-----------------------------------------------------------*/
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343 static void prvConfigurePHY( void )
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348 /* Auto negotiate the configuration. */
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349 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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351 vTaskDelay( emacSHORT_DELAY * 5 );
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353 for( x = 0; x < 10; x++ )
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355 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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357 if( us & PHY_AUTO_NEG_COMPLETE )
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362 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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366 /*-----------------------------------------------------------*/
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368 static long prvSetupLinkStatus( void )
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370 long lReturn = pdFAIL, x;
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371 unsigned short usLinkStatus;
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373 /* Wait with timeout for the link to be established. */
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374 for( x = 0; x < 10; x++ )
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376 usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );
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377 if( usLinkStatus & emacLINK_ESTABLISHED )
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379 /* Link is established. */
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384 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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387 if( lReturn == pdPASS )
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389 /* Configure Full/Half Duplex mode. */
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390 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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392 /* Full duplex is enabled. */
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393 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
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394 LPC_EMAC->Command |= CR_FULL_DUP;
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395 LPC_EMAC->IPGT = IPGT_FULL_DUP;
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399 /* Half duplex mode. */
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400 LPC_EMAC->IPGT = IPGT_HALF_DUP;
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403 /* Configure 100MBit/10MBit mode. */
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404 if( usLinkStatus & emac10BASE_T_MODE )
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407 LPC_EMAC->SUPP = 0;
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411 /* 100MBit mode. */
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412 LPC_EMAC->SUPP = SUPP_SPEED;
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418 /*-----------------------------------------------------------*/
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420 static void prvReturnBuffer( unsigned char *pucBuffer )
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424 /* Return a buffer to the pool of free buffers. */
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425 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
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427 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
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429 ucBufferInUse[ ul ] = pdFALSE;
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434 /*-----------------------------------------------------------*/
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436 unsigned long ulGetEMACRxData( void )
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438 unsigned long ulLen = 0;
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441 if( LPC_EMAC->RxProduceIndex != LPC_EMAC->RxConsumeIndex )
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443 /* Mark the current buffer as free as uip_buf is going to be set to
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444 the buffer that contains the received data. */
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445 prvReturnBuffer( uip_buf );
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447 ulLen = ( RX_STAT_INFO( LPC_EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
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448 uip_buf = ( unsigned char * ) RX_DESC_PACKET( LPC_EMAC->RxConsumeIndex );
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450 /* Allocate a new buffer to the descriptor. */
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451 RX_DESC_PACKET( LPC_EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
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453 /* Move the consume index onto the next position, ensuring it wraps to
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454 the beginning at the appropriate place. */
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455 lIndex = LPC_EMAC->RxConsumeIndex;
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458 if( lIndex >= NUM_RX_FRAG )
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463 LPC_EMAC->RxConsumeIndex = lIndex;
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468 /*-----------------------------------------------------------*/
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470 void vSendEMACTxData( unsigned short usTxDataLen )
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472 unsigned long ulAttempts = 0UL;
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474 /* Check to see if the Tx descriptor is free, indicated by its buffer being
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476 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
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478 /* Wait for the Tx descriptor to become available. */
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479 vTaskDelay( emacBUFFER_WAIT_DELAY );
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482 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
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484 /* Something has gone wrong as the Tx descriptor is still in use.
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485 Clear it down manually, the data it was sending will probably be
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487 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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492 /* Setup the Tx descriptor for transmission. Remember the length of the
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493 data being sent so the second descriptor can be used to send it again from
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495 usSendLen = usTxDataLen;
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496 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
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497 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
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498 LPC_EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
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500 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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501 uip_buf = prvGetNextBuffer();
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503 /*-----------------------------------------------------------*/
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505 static long prvWritePHY( long lPhyReg, long lValue )
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507 const long lMaxTime = 10;
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510 LPC_EMAC->MADR = DP83848C_DEF_ADR | lPhyReg;
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511 LPC_EMAC->MWTD = lValue;
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514 for( x = 0; x < lMaxTime; x++ )
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516 if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )
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518 /* Operation has finished. */
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522 vTaskDelay( emacSHORT_DELAY );
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534 /*-----------------------------------------------------------*/
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536 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
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539 const long lMaxTime = 10;
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541 LPC_EMAC->MADR = DP83848C_DEF_ADR | ucPhyReg;
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542 LPC_EMAC->MCMD = MCMD_READ;
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544 for( x = 0; x < lMaxTime; x++ )
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546 /* Operation has finished. */
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547 if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )
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552 vTaskDelay( emacSHORT_DELAY );
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555 LPC_EMAC->MCMD = 0;
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557 if( x >= lMaxTime )
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559 *plStatus = pdFAIL;
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562 return( LPC_EMAC->MRDD );
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564 /*-----------------------------------------------------------*/
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566 void vEMAC_ISR( void )
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568 unsigned long ulStatus;
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569 long lHigherPriorityTaskWoken = pdFALSE;
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571 ulStatus = LPC_EMAC->IntStatus;
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573 /* Clear the interrupt. */
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574 LPC_EMAC->IntClear = ulStatus;
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576 if( ulStatus & INT_RX_DONE )
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578 /* Ensure the uIP task is not blocked as data has arrived. */
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579 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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582 if( ulStatus & INT_TX_DONE )
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584 if( usSendLen > 0 )
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586 /* Send the data again, using the second descriptor. As there are
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587 only two descriptors the index is set back to 0. */
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588 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
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589 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
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590 LPC_EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
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592 /* This is the second Tx so set usSendLen to 0 to indicate that the
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593 Tx descriptors will be free again. */
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598 /* The Tx buffer is no longer required. */
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599 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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600 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
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604 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
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