2 FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.
\r
4 ***************************************************************************
\r
8 * + New to FreeRTOS, *
\r
9 * + Wanting to learn FreeRTOS or multitasking in general quickly *
\r
10 * + Looking for basic training, *
\r
11 * + Wanting to improve your FreeRTOS skills and productivity *
\r
13 * then take a look at the FreeRTOS books - available as PDF or paperback *
\r
15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
\r
16 * http://www.FreeRTOS.org/Documentation *
\r
18 * A pdf reference manual is also available. Both are usually delivered *
\r
19 * to your inbox within 20 minutes to two hours when purchased between 8am *
\r
20 * and 8pm GMT (although please allow up to 24 hours in case of *
\r
21 * exceptional circumstances). Thank you for your support! *
\r
23 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 ***NOTE*** The exception to the GPL is included to allow you to distribute
\r
31 a combined work that includes FreeRTOS without being obliged to provide the
\r
32 source code for proprietary components outside of the FreeRTOS kernel.
\r
33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
\r
34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
47 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
50 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
51 licensing and training services.
\r
54 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
\r
56 /* Kernel includes. */
\r
57 #include "FreeRTOS.h"
\r
61 /* Hardware specific includes. */
\r
62 #include "EthDev_LPC17xx.h"
\r
64 /* Time to wait between each inspection of the link status. */
\r
65 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
\r
67 /* Short delay used in several places during the initialisation process. */
\r
68 #define emacSHORT_DELAY ( 2 )
\r
70 /* Hardware specific bit definitions. */
\r
71 #define emacLINK_ESTABLISHED ( 0x0001 )
\r
72 #define emacFULL_DUPLEX_ENABLED ( 0x0004 )
\r
73 #define emac10BASE_T_MODE ( 0x0002 )
\r
74 #define emacPINSEL2_VALUE 0x50150105
\r
76 /* If no buffers are available, then wait this long before looking again.... */
\r
77 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
\r
79 /* ...and don't look more than this many times. */
\r
80 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
82 /* Index to the Tx descriptor that is always used first for every Tx. The second
\r
83 descriptor is then used to re-send in order to speed up the uIP Tx process. */
\r
84 #define emacTX_DESC_INDEX ( 0 )
\r
86 /*-----------------------------------------------------------*/
\r
89 * Configure both the Rx and Tx descriptors during the init process.
\r
91 static void prvInitDescriptors( void );
\r
94 * Setup the IO and peripherals required for Ethernet communication.
\r
96 static void prvSetupEMACHardware( void );
\r
99 * Control the auto negotiate process.
\r
101 static void prvConfigurePHY( void );
\r
104 * Wait for a link to be established, then setup the PHY according to the link
\r
107 static long prvSetupLinkStatus( void );
\r
110 * Search the pool of buffers to find one that is free. If a buffer is found
\r
111 * mark it as in use before returning its address.
\r
113 static unsigned char *prvGetNextBuffer( void );
\r
116 * Return an allocated buffer to the pool of free buffers.
\r
118 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
121 * Send lValue to the lPhyReg within the PHY.
\r
123 static long prvWritePHY( long lPhyReg, long lValue );
\r
126 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
\r
127 * pdFALSE if there is an error.
\r
129 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
\r
131 /*-----------------------------------------------------------*/
\r
133 /* The semaphore used to wake the uIP task when data arrives. */
\r
134 extern xSemaphoreHandle xEMACSemaphore;
\r
136 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
\r
137 If the index contains a 1 then the buffer within pool is in use, if it
\r
138 contains a 0 then the buffer is free. */
\r
139 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
\r
141 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
\r
142 allocated within this file. */
\r
143 unsigned char * uip_buf;
\r
145 /* Store the length of the data being sent so the data can be sent twice. The
\r
146 value will be set back to 0 once the data has been sent twice. */
\r
147 static unsigned short usSendLen = 0;
\r
149 /*-----------------------------------------------------------*/
\r
151 long lEMACInit( void )
\r
153 long lReturn = pdPASS;
\r
154 unsigned long ulID1, ulID2;
\r
156 /* Reset peripherals, configure port pins and registers. */
\r
157 prvSetupEMACHardware();
\r
159 /* Check the PHY part number is as expected. */
\r
160 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
\r
161 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
\r
162 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
\r
164 /* Set the Ethernet MAC Address registers */
\r
165 EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
\r
166 EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
\r
167 EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
\r
169 /* Initialize Tx and Rx DMA Descriptors */
\r
170 prvInitDescriptors();
\r
172 /* Receive broadcast and perfect match packets */
\r
173 EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
\r
175 /* Setup the PHY. */
\r
183 /* Check the link status. */
\r
184 if( lReturn == pdPASS )
\r
186 lReturn = prvSetupLinkStatus();
\r
189 if( lReturn == pdPASS )
\r
191 /* Initialise uip_buf to ensure it points somewhere valid. */
\r
192 uip_buf = prvGetNextBuffer();
\r
194 /* Reset all interrupts */
\r
195 EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
\r
197 /* Enable receive and transmit mode of MAC Ethernet core */
\r
198 EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
\r
199 EMAC->MAC1 |= MAC1_REC_EN;
\r
204 /*-----------------------------------------------------------*/
\r
206 static unsigned char *prvGetNextBuffer( void )
\r
209 unsigned char *pucReturn = NULL;
\r
210 unsigned long ulAttempts = 0;
\r
212 while( pucReturn == NULL )
\r
214 /* Look through the buffers to find one that is not in use by
\r
216 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
\r
218 if( ucBufferInUse[ x ] == pdFALSE )
\r
220 ucBufferInUse[ x ] = pdTRUE;
\r
221 pucReturn = ( unsigned char * ) ETH_BUF( x );
\r
226 /* Was a buffer found? */
\r
227 if( pucReturn == NULL )
\r
231 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
236 /* Wait then look again. */
\r
237 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
243 /*-----------------------------------------------------------*/
\r
245 static void prvInitDescriptors( void )
\r
247 long x, lNextBuffer = 0;
\r
249 for( x = 0; x < NUM_RX_FRAG; x++ )
\r
251 /* Allocate the next Ethernet buffer to this descriptor. */
\r
252 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
\r
253 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
\r
254 RX_STAT_INFO( x ) = 0;
\r
255 RX_STAT_HASHCRC( x ) = 0;
\r
257 /* The Ethernet buffer is now in use. */
\r
258 ucBufferInUse[ lNextBuffer ] = pdTRUE;
\r
262 /* Set EMAC Receive Descriptor Registers. */
\r
263 EMAC->RxDescriptor = RX_DESC_BASE;
\r
264 EMAC->RxStatus = RX_STAT_BASE;
\r
265 EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
\r
267 /* Rx Descriptors Point to 0 */
\r
268 EMAC->RxConsumeIndex = 0;
\r
270 /* A buffer is not allocated to the Tx descriptors until they are actually
\r
272 for( x = 0; x < NUM_TX_FRAG; x++ )
\r
274 TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
\r
275 TX_DESC_CTRL( x ) = 0;
\r
276 TX_STAT_INFO( x ) = 0;
\r
279 /* Set EMAC Transmit Descriptor Registers. */
\r
280 EMAC->TxDescriptor = TX_DESC_BASE;
\r
281 EMAC->TxStatus = TX_STAT_BASE;
\r
282 EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
\r
284 /* Tx Descriptors Point to 0 */
\r
285 EMAC->TxProduceIndex = 0;
\r
287 /*-----------------------------------------------------------*/
\r
289 static void prvSetupEMACHardware( void )
\r
294 /* Enable P1 Ethernet Pins. */
\r
295 PINCON->PINSEL2 = emacPINSEL2_VALUE;
\r
296 PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
\r
298 /* Power Up the EMAC controller. */
\r
299 SC->PCONP |= PCONP_PCENET;
\r
300 vTaskDelay( emacSHORT_DELAY );
\r
302 /* Reset all EMAC internal modules. */
\r
303 EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
\r
304 EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
\r
306 /* A short delay after reset. */
\r
307 vTaskDelay( emacSHORT_DELAY );
\r
309 /* Initialize MAC control registers. */
\r
310 EMAC->MAC1 = MAC1_PASS_ALL;
\r
311 EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
\r
312 EMAC->MAXF = ETH_MAX_FLEN;
\r
313 EMAC->CLRT = CLRT_DEF;
\r
314 EMAC->IPGR = IPGR_DEF;
\r
316 /* Enable Reduced MII interface. */
\r
317 EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
\r
319 /* Reset Reduced MII Logic. */
\r
320 EMAC->SUPP = SUPP_RES_RMII;
\r
321 vTaskDelay( emacSHORT_DELAY );
\r
324 /* Put the PHY in reset mode */
\r
325 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
326 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
\r
328 /* Wait for hardware reset to end. */
\r
329 for( x = 0; x < 100; x++ )
\r
331 vTaskDelay( emacSHORT_DELAY * 5 );
\r
332 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
\r
333 if( !( us & MCFG_RES_MII ) )
\r
335 /* Reset complete */
\r
340 /*-----------------------------------------------------------*/
\r
342 static void prvConfigurePHY( void )
\r
347 /* Auto negotiate the configuration. */
\r
348 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
\r
350 vTaskDelay( emacSHORT_DELAY * 5 );
\r
352 for( x = 0; x < 10; x++ )
\r
354 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
\r
356 if( us & PHY_AUTO_NEG_COMPLETE )
\r
361 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
365 /*-----------------------------------------------------------*/
\r
367 static long prvSetupLinkStatus( void )
\r
369 long lReturn = pdFAIL, x;
\r
370 unsigned short usLinkStatus;
\r
372 /* Wait with timeout for the link to be established. */
\r
373 for( x = 0; x < 10; x++ )
\r
375 usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );
\r
376 if( usLinkStatus & emacLINK_ESTABLISHED )
\r
378 /* Link is established. */
\r
383 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
\r
386 if( lReturn == pdPASS )
\r
388 /* Configure Full/Half Duplex mode. */
\r
389 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
\r
391 /* Full duplex is enabled. */
\r
392 EMAC->MAC2 |= MAC2_FULL_DUP;
\r
393 EMAC->Command |= CR_FULL_DUP;
\r
394 EMAC->IPGT = IPGT_FULL_DUP;
\r
398 /* Half duplex mode. */
\r
399 EMAC->IPGT = IPGT_HALF_DUP;
\r
402 /* Configure 100MBit/10MBit mode. */
\r
403 if( usLinkStatus & emac10BASE_T_MODE )
\r
410 /* 100MBit mode. */
\r
411 EMAC->SUPP = SUPP_SPEED;
\r
417 /*-----------------------------------------------------------*/
\r
419 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
423 /* Return a buffer to the pool of free buffers. */
\r
424 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
\r
426 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
\r
428 ucBufferInUse[ ul ] = pdFALSE;
\r
433 /*-----------------------------------------------------------*/
\r
435 unsigned long ulGetEMACRxData( void )
\r
437 unsigned long ulLen = 0;
\r
440 if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
\r
442 /* Mark the current buffer as free as uip_buf is going to be set to
\r
443 the buffer that contains the received data. */
\r
444 prvReturnBuffer( uip_buf );
\r
446 ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
\r
447 uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
\r
449 /* Allocate a new buffer to the descriptor. */
\r
450 RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
\r
452 /* Move the consume index onto the next position, ensuring it wraps to
\r
453 the beginning at the appropriate place. */
\r
454 lIndex = EMAC->RxConsumeIndex;
\r
457 if( lIndex >= NUM_RX_FRAG )
\r
462 EMAC->RxConsumeIndex = lIndex;
\r
467 /*-----------------------------------------------------------*/
\r
469 void vSendEMACTxData( unsigned short usTxDataLen )
\r
471 unsigned long ulAttempts = 0UL;
\r
473 /* Check to see if the Tx descriptor is free, indicated by its buffer being
\r
475 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
\r
477 /* Wait for the Tx descriptor to become available. */
\r
478 vTaskDelay( emacBUFFER_WAIT_DELAY );
\r
481 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
\r
483 /* Something has gone wrong as the Tx descriptor is still in use.
\r
484 Clear it down manually, the data it was sending will probably be
\r
486 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
491 /* Setup the Tx descriptor for transmission. Remember the length of the
\r
492 data being sent so the second descriptor can be used to send it again from
\r
494 usSendLen = usTxDataLen;
\r
495 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
\r
496 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
\r
497 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
\r
499 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
\r
500 uip_buf = prvGetNextBuffer();
\r
502 /*-----------------------------------------------------------*/
\r
504 static long prvWritePHY( long lPhyReg, long lValue )
\r
506 const long lMaxTime = 10;
\r
509 EMAC->MADR = DP83848C_DEF_ADR | lPhyReg;
\r
510 EMAC->MWTD = lValue;
\r
513 for( x = 0; x < lMaxTime; x++ )
\r
515 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
517 /* Operation has finished. */
\r
521 vTaskDelay( emacSHORT_DELAY );
\r
533 /*-----------------------------------------------------------*/
\r
535 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
\r
538 const long lMaxTime = 10;
\r
540 EMAC->MADR = DP83848C_DEF_ADR | ucPhyReg;
\r
541 EMAC->MCMD = MCMD_READ;
\r
543 for( x = 0; x < lMaxTime; x++ )
\r
545 /* Operation has finished. */
\r
546 if( ( EMAC->MIND & MIND_BUSY ) == 0 )
\r
551 vTaskDelay( emacSHORT_DELAY );
\r
556 if( x >= lMaxTime )
\r
558 *plStatus = pdFAIL;
\r
561 return( EMAC->MRDD );
\r
563 /*-----------------------------------------------------------*/
\r
565 void vEMAC_ISR( void )
\r
567 unsigned long ulStatus;
\r
568 long lHigherPriorityTaskWoken = pdFALSE;
\r
570 ulStatus = EMAC->IntStatus;
\r
572 /* Clear the interrupt. */
\r
573 EMAC->IntClear = ulStatus;
\r
575 if( ulStatus & INT_RX_DONE )
\r
577 /* Ensure the uIP task is not blocked as data has arrived. */
\r
578 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
\r
581 if( ulStatus & INT_TX_DONE )
\r
583 if( usSendLen > 0 )
\r
585 /* Send the data again, using the second descriptor. As there are
\r
586 only two descriptors the index is set back to 0. */
\r
587 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
\r
588 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
\r
589 EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
\r
591 /* This is the second Tx so set usSendLen to 0 to indicate that the
\r
592 Tx descriptors will be free again. */
\r
597 /* The Tx buffer is no longer required. */
\r
598 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
\r
599 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
\r
603 portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
\r