git.sur5r.net Git - freertos/blob - Demo/CORTEX_LPC1768_GCC_Rowley/CortexM3.h

   1 /******************************************************************************/\r
   2 /* CortexM3.H: Header file for Cortex-M3                                      */\r
   3 /******************************************************************************/\r
   4 /* This file is part of the uVision/ARM development tools.                    */\r
   5 /* Copyright (c) 2008 Keil Software. All rights reserved.                     */\r
   6 /******************************************************************************/\r
   7 \r
   8 #ifndef __CortexM3_H\r
   9 #define __CortexM3_H\r
  10 \r
  11 \r
  12 #define REG8(x)  (*((volatile unsigned char  *)(x)))\r
  13 #define REG16(x) (*((volatile unsigned short *)(x)))\r
  14 #define REG32(x) (*((volatile unsigned long  *)(x)))\r
  15 \r
  16 \r
  17 /* NVIC Registers */\r
  18 #define NVIC_INT_TYPE           REG32(0xE000E004)\r
  19 #define NVIC_ST_CTRL            REG32(0xE000E010)\r
  20 #define NVIC_ST_RELOAD          REG32(0xE000E014)\r
  21 #define NVIC_ST_CURRENT         REG32(0xE000E018)\r
  22 #define NVIC_ST_CALIB           REG32(0xE000E01C)\r
  23 #define NVIC_ENABLE0            REG32(0xE000E100)\r
  24 #define NVIC_ENABLE1            REG32(0xE000E104)\r
  25 #define NVIC_ENABLE2            REG32(0xE000E108)\r
  26 #define NVIC_ENABLE3            REG32(0xE000E10C)\r
  27 #define NVIC_ENABLE4            REG32(0xE000E110)\r
  28 #define NVIC_ENABLE5            REG32(0xE000E114)\r
  29 #define NVIC_ENABLE6            REG32(0xE000E118)\r
  30 #define NVIC_ENABLE7            REG32(0xE000E11C)\r
  31 #define NVIC_DISABLE0           REG32(0xE000E180)\r
  32 #define NVIC_DISABLE1           REG32(0xE000E184)\r
  33 #define NVIC_DISABLE2           REG32(0xE000E188)\r
  34 #define NVIC_DISABLE3           REG32(0xE000E18C)\r
  35 #define NVIC_DISABLE4           REG32(0xE000E190)\r
  36 #define NVIC_DISABLE5           REG32(0xE000E194)\r
  37 #define NVIC_DISABLE6           REG32(0xE000E198)\r
  38 #define NVIC_DISABLE7           REG32(0xE000E19C)\r
  39 #define NVIC_PEND0              REG32(0xE000E200)\r
  40 #define NVIC_PEND1              REG32(0xE000E204)\r
  41 #define NVIC_PEND2              REG32(0xE000E208)\r
  42 #define NVIC_PEND3              REG32(0xE000E20C)\r
  43 #define NVIC_PEND4              REG32(0xE000E210)\r
  44 #define NVIC_PEND5              REG32(0xE000E214)\r
  45 #define NVIC_PEND6              REG32(0xE000E218)\r
  46 #define NVIC_PEND7              REG32(0xE000E21C)\r
  47 #define NVIC_UNPEND0            REG32(0xE000E280)\r
  48 #define NVIC_UNPEND1            REG32(0xE000E284)\r
  49 #define NVIC_UNPEND2            REG32(0xE000E288)\r
  50 #define NVIC_UNPEND3            REG32(0xE000E28C)\r
  51 #define NVIC_UNPEND4            REG32(0xE000E290)\r
  52 #define NVIC_UNPEND5            REG32(0xE000E294)\r
  53 #define NVIC_UNPEND6            REG32(0xE000E298)\r
  54 #define NVIC_UNPEND7            REG32(0xE000E29C)\r
  55 #define NVIC_ACTIVE0            REG32(0xE000E300)\r
  56 #define NVIC_ACTIVE1            REG32(0xE000E304)\r
  57 #define NVIC_ACTIVE2            REG32(0xE000E308)\r
  58 #define NVIC_ACTIVE3            REG32(0xE000E30C)\r
  59 #define NVIC_ACTIVE4            REG32(0xE000E310)\r
  60 #define NVIC_ACTIVE5            REG32(0xE000E314)\r
  61 #define NVIC_ACTIVE6            REG32(0xE000E318)\r
  62 #define NVIC_ACTIVE7            REG32(0xE000E31C)\r
  63 #define NVIC_PRI0               REG32(0xE000E400)\r
  64 #define NVIC_PRI1               REG32(0xE000E404)\r
  65 #define NVIC_PRI2               REG32(0xE000E408)\r
  66 #define NVIC_PRI3               REG32(0xE000E40C)\r
  67 #define NVIC_PRI4               REG32(0xE000E410)\r
  68 #define NVIC_PRI5               REG32(0xE000E414)\r
  69 #define NVIC_PRI6               REG32(0xE000E418)\r
  70 #define NVIC_PRI7               REG32(0xE000E41C)\r
  71 #define NVIC_PRI8               REG32(0xE000E420)\r
  72 #define NVIC_PRI9               REG32(0xE000E424)\r
  73 #define NVIC_PRI10              REG32(0xE000E428)\r
  74 #define NVIC_PRI11              REG32(0xE000E42C)\r
  75 #define NVIC_PRI12              REG32(0xE000E430)\r
  76 #define NVIC_PRI13              REG32(0xE000E434)\r
  77 #define NVIC_PRI14              REG32(0xE000E438)\r
  78 #define NVIC_PRI15              REG32(0xE000E43C)\r
  79 #define NVIC_PRI16              REG32(0xE000E440)\r
  80 #define NVIC_PRI17              REG32(0xE000E444)\r
  81 #define NVIC_PRI18              REG32(0xE000E448)\r
  82 #define NVIC_PRI19              REG32(0xE000E44C)\r
  83 #define NVIC_PRI20              REG32(0xE000E450)\r
  84 #define NVIC_PRI21              REG32(0xE000E454)\r
  85 #define NVIC_PRI22              REG32(0xE000E458)\r
  86 #define NVIC_PRI23              REG32(0xE000E45C)\r
  87 #define NVIC_PRI24              REG32(0xE000E460)\r
  88 #define NVIC_PRI25              REG32(0xE000E464)\r
  89 #define NVIC_PRI26              REG32(0xE000E468)\r
  90 #define NVIC_PRI27              REG32(0xE000E46C)\r
  91 #define NVIC_PRI28              REG32(0xE000E470)\r
  92 #define NVIC_PRI29              REG32(0xE000E474)\r
  93 #define NVIC_PRI30              REG32(0xE000E478)\r
  94 #define NVIC_PRI31              REG32(0xE000E47C)\r
  95 #define NVIC_PRI32              REG32(0xE000E480)\r
  96 #define NVIC_PRI33              REG32(0xE000E484)\r
  97 #define NVIC_PRI34              REG32(0xE000E488)\r
  98 #define NVIC_PRI35              REG32(0xE000E48C)\r
  99 #define NVIC_PRI36              REG32(0xE000E490)\r
 100 #define NVIC_PRI37              REG32(0xE000E494)\r
 101 #define NVIC_PRI38              REG32(0xE000E498)\r
 102 #define NVIC_PRI39              REG32(0xE000E49C)\r
 103 #define NVIC_PRI40              REG32(0xE000E4A0)\r
 104 #define NVIC_PRI41              REG32(0xE000E4A4)\r
 105 #define NVIC_PRI42              REG32(0xE000E4A8)\r
 106 #define NVIC_PRI43              REG32(0xE000E4AC)\r
 107 #define NVIC_PRI44              REG32(0xE000E4B0)\r
 108 #define NVIC_PRI45              REG32(0xE000E4B4)\r
 109 #define NVIC_PRI46              REG32(0xE000E4B8)\r
 110 #define NVIC_PRI47              REG32(0xE000E4BC)\r
 111 #define NVIC_PRI48              REG32(0xE000E4C0)\r
 112 #define NVIC_PRI49              REG32(0xE000E4C4)\r
 113 #define NVIC_PRI50              REG32(0xE000E4C8)\r
 114 #define NVIC_PRI51              REG32(0xE000E4CC)\r
 115 #define NVIC_PRI52              REG32(0xE000E4D0)\r
 116 #define NVIC_PRI53              REG32(0xE000E4D4)\r
 117 #define NVIC_PRI54              REG32(0xE000E4D8)\r
 118 #define NVIC_PRI55              REG32(0xE000E4DC)\r
 119 #define NVIC_PRI56              REG32(0xE000E4E0)\r
 120 #define NVIC_PRI57              REG32(0xE000E4E4)\r
 121 #define NVIC_PRI58              REG32(0xE000E4E8)\r
 122 #define NVIC_PRI59              REG32(0xE000E4EC)\r
 123 #define NVIC_CPUID              REG32(0xE000ED00)\r
 124 #define NVIC_INT_CTRL           REG32(0xE000ED04)\r
 125 #define NVIC_VECT_TABLE         REG32(0xE000ED08)\r
 126 #define NVIC_AP_INT_RST         REG32(0xE000ED0C)\r
 127 #define NVIC_SYS_CTRL           REG32(0xE000ED10)\r
 128 #define NVIC_CFG_CTRL           REG32(0xE000ED14)\r
 129 #define NVIC_SYS_H_PRI1         REG32(0xE000ED18)\r
 130 #define NVIC_SYS_H_PRI2         REG32(0xE000ED1C)\r
 131 #define NVIC_SYS_H_PRI3         REG32(0xE000ED20)\r
 132 #define NVIC_SYS_H_CTRL         REG32(0xE000ED24)\r
 133 #define NVIC_FAULT_STA          REG32(0xE000ED28)\r
 134 #define NVIC_HARD_F_STA         REG32(0xE000ED2C)\r
 135 #define NVIC_DBG_F_STA          REG32(0xE000ED30)\r
 136 #define NVIC_MM_F_ADR           REG32(0xE000ED34)\r
 137 #define NVIC_BUS_F_ADR          REG32(0xE000ED38)\r
 138 #define NVIC_SW_TRIG            REG32(0xE000EF00)\r
 139 \r
 140 \r
 141 /* MPU Registers */\r
 142 #define MPU_TYPE                REG32(0xE000ED90)\r
 143 #define MPU_CTRL                REG32(0xE000ED94)\r
 144 #define MPU_RG_NUM              REG32(0xE000ED98)\r
 145 #define MPU_RG_ADDR             REG32(0xE000ED9C)\r
 146 #define MPU_RG_AT_SZ            REG32(0xE000EDA0)\r
 147 \r
 148 \r
 149 #endif  // __CortexM3_H\r