1 /*****************************************************************************
2 * Copyright (c) 2009 Rowley Associates Limited. *
4 * This file may be distributed under the terms of the License Agreement *
5 * provided with this software. *
7 * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
8 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
9 *****************************************************************************/
11 /*****************************************************************************
12 * Preprocessor Definitions
13 * ------------------------
17 * If defined, the program will startup from power-on/reset. If not defined
18 * the program will just loop endlessly from power-on/reset.
20 * This definition is not defined by default on this target because the
21 * debugger is unable to reset this target and maintain control of it over the
22 * JTAG interface. The advantage of doing this is that it allows the debugger
23 * to reset the CPU and run programs from a known reset CPU state on each run.
24 * It also acts as a safety net if you accidently download a program in FLASH
25 * that crashes and prevents the debugger from taking control over JTAG
26 * rendering the target unusable over JTAG. The obvious disadvantage of doing
27 * this is that your application will not startup without the debugger.
29 * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst
30 * you are developing and only define STARTUP_FROM_RESET when development is
36 * If defined, the USB clock will be configured.
38 *****************************************************************************/
42 #if OSCILLATOR_CLOCK_FREQUENCY==12000000
46 /* Fosc = 12Mhz, Fcco = 400Mhz, cclk = 100Mhz */
48 #define PLL0CFG_VAL ((49 << PLL0CFG_MSEL0_BIT) | (2 << PLL0CFG_NSEL0_BIT))
56 #define FLASHCFG_VAL 0x0000403A
61 /* Fosc = 12Mhz, Fcco = 288Mhz, cclk = 72Mhz */
63 #define PLL0CFG_VAL ((11 << PLL0CFG_MSEL0_BIT) | (0 << PLL0CFG_NSEL0_BIT))
71 #define FLASHCFG_VAL 0x0000303A
76 /* Fosc = 12Mhz, Fcco = 192Mhz, usbclk = 48Mhz */
78 #define PLL1CFG_VAL ((3 << PLL1CFG_MSEL1_BIT) | (1 << PLL1CFG_PSEL1_BIT))
87 .section .vectors, "ax"
92 .macro DEFAULT_ISR_HANDLER name=
96 1: b 1b /* endless loop */
99 .extern xPortPendSVHandler
100 .extern xPortSysTickHandler
101 .extern vPortSVCHandler
106 #ifdef STARTUP_FROM_RESET
110 #endif /* STARTUP_FROM_RESET */
112 .word HardFault_Handler
113 .word MemManage_Handler
114 .word BusFault_Handler
115 .word UsageFault_Handler
120 .word vPortSVCHandler
121 .word DebugMon_Handler
123 .word xPortPendSVHandler
124 .word xPortSysTickHandler
126 .word TIMER0_IRQHandler
127 .word TIMER1_IRQHandler
128 .word TIMER2_IRQHandler
129 .word TIMER3_IRQHandler
130 .word UART0_IRQHandler
131 .word UART1_IRQHandler
132 .word UART2_IRQHandler
133 .word UART3_IRQHandler
134 .word PWM1_IRQHandler
135 .word I2C0_IRQHandler
136 .word I2C1_IRQHandler
137 .word I2C2_IRQHandler
139 .word SSP0_IRQHandler
140 .word SSP1_IRQHandler
141 .word PLL0_IRQHandler
143 .word EINT0_IRQHandler
144 .word EINT1_IRQHandler
145 .word EINT2_IRQHandler
146 .word EINT3_IRQHandler
151 .word GPDMA_IRQHandler
155 .word MCPWM_IRQHandler
157 .word PLL1_IRQHandler
158 .word USBACT_IRQHandler
159 .word CANACT_IRQHandler
165 #ifndef __FLASH_BUILD
166 /* If this is a RAM build, configure vector table offset register to point
167 to the RAM vector table. */
173 ldr r0, =SC_BASE_ADDRESS
175 /* Configure PLL0 Multiplier/Divider */
176 ldr r1, [r0, #PLL0STAT_OFFSET]
177 tst r1, #PLL0STAT_PLLC0_STAT
180 /* Disconnect PLL0 */
181 ldr r1, =PLL0CON_PLLE0
182 str r1, [r0, #PLL0CON_OFFSET]
184 str r1, [r0, #PLL0FEED_OFFSET]
186 str r1, [r0, #PLL0FEED_OFFSET]
190 str r1, [r0, #PLL0CON_OFFSET]
192 str r1, [r0, #PLL0FEED_OFFSET]
194 str r1, [r0, #PLL0FEED_OFFSET]
196 /* Enable main oscillator */
197 ldr r1, [r0, #SCS_OFFSET]
198 orr r1, r1, #SCS_OSCEN
199 str r1, [r0, #SCS_OFFSET]
201 ldr r1, [r0, #SCS_OFFSET]
205 /* Select main oscillator as the PLL0 clock source */
207 str r1, [r0, #CLKSRCSEL_OFFSET]
211 str r1, [r0, #PLL0CFG_OFFSET]
213 str r1, [r0, #PLL0FEED_OFFSET]
215 str r1, [r0, #PLL0FEED_OFFSET]
218 ldr r1, =PLL0CON_PLLE0
219 str r1, [r0, #PLL0CON_OFFSET]
221 str r1, [r0, #PLL0FEED_OFFSET]
223 str r1, [r0, #PLL0FEED_OFFSET]
226 /* Set the CPU clock divider */
228 str r1, [r0, #CCLKCFG_OFFSET]
232 /* Configure the FLASH accelerator */
233 ldr r1, =FLASHCFG_VAL
234 str r1, [r0, #FLASHCFG_OFFSET]
237 /* Wait for PLL0 to lock */
239 ldr r1, [r0, #PLL0STAT_OFFSET]
240 tst r1, #PLL0STAT_PLOCK0
243 /* PLL0 Locked, connect PLL as clock source */
244 mov r1, #(PLL0CON_PLLE0 | PLL0CON_PLLC0)
245 str r1, [r0, #PLL0CON_OFFSET]
247 str r1, [r0, #PLL0FEED_OFFSET]
249 str r1, [r0, #PLL0FEED_OFFSET]
250 /* Wait for PLL0 to connect */
252 ldr r1, [r0, #PLL0STAT_OFFSET]
253 tst r1, #PLL0STAT_PLLC0_STAT
257 /* Configure PLL1 Multiplier/Divider */
258 ldr r1, [r0, #PLL1STAT_OFFSET]
259 tst r1, #PLL1STAT_PLLC1_STAT
262 /* Disconnect PLL1 */
263 ldr r1, =PLL1CON_PLLE1
264 str r1, [r0, #PLL1CON_OFFSET]
266 str r1, [r0, #PLL1FEED_OFFSET]
268 str r1, [r0, #PLL1FEED_OFFSET]
272 str r1, [r0, #PLL1CON_OFFSET]
274 str r1, [r0, #PLL1FEED_OFFSET]
276 str r1, [r0, #PLL1FEED_OFFSET]
280 str r1, [r0, #PLL1CFG_OFFSET]
282 str r1, [r0, #PLL1FEED_OFFSET]
284 str r1, [r0, #PLL1FEED_OFFSET]
287 ldr r1, =PLL1CON_PLLE1
288 str r1, [r0, #PLL1CON_OFFSET]
290 str r1, [r0, #PLL1FEED_OFFSET]
292 str r1, [r0, #PLL1FEED_OFFSET]
294 /* Wait for PLL1 to lock */
296 ldr r1, [r0, #PLL1STAT_OFFSET]
297 tst r1, #PLL1STAT_PLOCK1
300 /* PLL1 Locked, connect PLL as clock source */
301 mov r1, #(PLL1CON_PLLE1 | PLL1CON_PLLC1)
302 str r1, [r0, #PLL1CON_OFFSET]
304 str r1, [r0, #PLL1FEED_OFFSET]
306 str r1, [r0, #PLL1FEED_OFFSET]
307 /* Wait for PLL1 to connect */
309 ldr r1, [r0, #PLL1STAT_OFFSET]
310 tst r1, #PLL1STAT_PLLC1_STAT
316 DEFAULT_ISR_HANDLER NMI_Handler
317 DEFAULT_ISR_HANDLER HardFault_Handler
318 DEFAULT_ISR_HANDLER MemManage_Handler
319 DEFAULT_ISR_HANDLER BusFault_Handler
320 DEFAULT_ISR_HANDLER UsageFault_Handler
321 DEFAULT_ISR_HANDLER SVC_Handler
322 DEFAULT_ISR_HANDLER DebugMon_Handler
323 DEFAULT_ISR_HANDLER PendSV_Handler
324 DEFAULT_ISR_HANDLER SysTick_Handler
325 DEFAULT_ISR_HANDLER WDT_IRQHandler
326 DEFAULT_ISR_HANDLER TIMER0_IRQHandler
327 DEFAULT_ISR_HANDLER TIMER1_IRQHandler
328 DEFAULT_ISR_HANDLER TIMER2_IRQHandler
329 DEFAULT_ISR_HANDLER TIMER3_IRQHandler
330 DEFAULT_ISR_HANDLER UART0_IRQHandler
331 DEFAULT_ISR_HANDLER UART1_IRQHandler
332 DEFAULT_ISR_HANDLER UART2_IRQHandler
333 DEFAULT_ISR_HANDLER UART3_IRQHandler
334 DEFAULT_ISR_HANDLER PWM1_IRQHandler
335 DEFAULT_ISR_HANDLER I2C0_IRQHandler
336 DEFAULT_ISR_HANDLER I2C1_IRQHandler
337 DEFAULT_ISR_HANDLER I2C2_IRQHandler
338 DEFAULT_ISR_HANDLER SPI_IRQHandler
339 DEFAULT_ISR_HANDLER SSP0_IRQHandler
340 DEFAULT_ISR_HANDLER SSP1_IRQHandler
341 DEFAULT_ISR_HANDLER PLL0_IRQHandler
342 DEFAULT_ISR_HANDLER RTC_IRQHandler
343 DEFAULT_ISR_HANDLER EINT0_IRQHandler
344 DEFAULT_ISR_HANDLER EINT1_IRQHandler
345 DEFAULT_ISR_HANDLER EINT2_IRQHandler
346 DEFAULT_ISR_HANDLER EINT3_IRQHandler
347 DEFAULT_ISR_HANDLER ADC_IRQHandler
348 DEFAULT_ISR_HANDLER BOD_IRQHandler
349 DEFAULT_ISR_HANDLER USB_IRQHandler
350 DEFAULT_ISR_HANDLER CAN_IRQHandler
351 DEFAULT_ISR_HANDLER GPDMA_IRQHandler
352 DEFAULT_ISR_HANDLER I2S_IRQHandler
353 DEFAULT_ISR_HANDLER ENET_IRQHandler
354 DEFAULT_ISR_HANDLER RIT_IRQHandler
355 DEFAULT_ISR_HANDLER MCPWM_IRQHandler
356 DEFAULT_ISR_HANDLER QEI_IRQHandler
357 DEFAULT_ISR_HANDLER PLL1_IRQHandler
358 DEFAULT_ISR_HANDLER USBACT_IRQHandler
359 DEFAULT_ISR_HANDLER CANACT_IRQHandler
361 #ifndef STARTUP_FROM_RESET
362 DEFAULT_ISR_HANDLER reset_wait
363 #endif /* STARTUP_FROM_RESET */