4 #include "CortexM3.h"
\r
7 /* System Control Block (SCB) includes:
\r
8 Flash Accelerator Module, Clocking and Power Control, External Interrupts,
\r
9 Reset, System Control and Status
\r
11 #define SCB_BASE_ADDR 0x400FC000
\r
13 /* Flash Accelerator Module */
\r
14 #define FLASHCTRL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
\r
15 #define FLASHTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
\r
17 /* Phase Locked Loop (Main PLL0) */
\r
18 #define PLL0CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
\r
19 #define PLL0CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
\r
20 #define PLL0STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
\r
21 #define PLL0FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
\r
23 /* Phase Locked Loop (USB PLL1) */
\r
24 #define PLL1CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))
\r
25 #define PLL1CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))
\r
26 #define PLL1STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))
\r
27 #define PLL1FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))
\r
30 #define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
\r
31 #define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
\r
33 /* Clock Selection and Dividers */
\r
34 #define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
\r
35 #define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
\r
36 #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
\r
37 #define IRCTRIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A4))
\r
38 #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
\r
39 #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
\r
41 /* External Interrupts */
\r
42 #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
\r
43 #define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
\r
44 #define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
\r
47 #define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
\r
49 /* System Controls and Status */
\r
50 #define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
\r
53 /* Pin Connect Block */
\r
54 #define PINCON_BASE_ADDR 0x4002C000
\r
55 #define PINSEL0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x00))
\r
56 #define PINSEL1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x04))
\r
57 #define PINSEL2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x08))
\r
58 #define PINSEL3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x0C))
\r
59 #define PINSEL4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x10))
\r
60 #define PINSEL5 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x14))
\r
61 #define PINSEL6 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x18))
\r
62 #define PINSEL7 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x1C))
\r
63 #define PINSEL8 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x20))
\r
64 #define PINSEL9 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x24))
\r
65 #define PINSEL10 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x28))
\r
67 #define PINMODE0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x40))
\r
68 #define PINMODE1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x44))
\r
69 #define PINMODE2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x48))
\r
70 #define PINMODE3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x4C))
\r
71 #define PINMODE4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x50))
\r
72 #define PINMODE5 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x54))
\r
73 #define PINMODE6 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x58))
\r
74 #define PINMODE7 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x5C))
\r
75 #define PINMODE8 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x60))
\r
76 #define PINMODE9 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x64))
\r
77 #define PINMODE_OD0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x68))
\r
78 #define PINMODE_OD1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x6C))
\r
79 #define PINMODE_OD2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x70))
\r
80 #define PINMODE_OD3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x74))
\r
81 #define PINMODE_OD4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x78))
\r
84 /* General Purpose Input/Output (GPIO) - Fast GPIO */
\r
85 // #define GPIO_BASE_ADDR 0x50014000 /* For the first silicon v0.00 */
\r
86 #define GPIO_BASE_ADDR 0x2009C000 /* For silicon v0.01 or newer */
\r
87 #define FIO0DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
\r
88 #define FIO0MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
\r
89 #define FIO0PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
\r
90 #define FIO0SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
\r
91 #define FIO0CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
\r
93 #define FIO1DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x20))
\r
94 #define FIO1MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x30))
\r
95 #define FIO1PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x34))
\r
96 #define FIO1SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x38))
\r
97 #define FIO1CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x3C))
\r
99 #define FIO2DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x40))
\r
100 #define FIO2MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x50))
\r
101 #define FIO2PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x54))
\r
102 #define FIO2SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x58))
\r
103 #define FIO2CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x5C))
\r
105 #define FIO3DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x60))
\r
106 #define FIO3MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x70))
\r
107 #define FIO3PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x74))
\r
108 #define FIO3SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x78))
\r
109 #define FIO3CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x7C))
\r
111 #define FIO4DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
\r
112 #define FIO4MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
\r
113 #define FIO4PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
\r
114 #define FIO4SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x98))
\r
115 #define FIO4CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x9C))
\r
117 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
\r
118 #define FIO0DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x00))
\r
119 #define FIO1DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x20))
\r
120 #define FIO2DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x40))
\r
121 #define FIO3DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x60))
\r
122 #define FIO4DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x80))
\r
124 #define FIO0DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x01))
\r
125 #define FIO1DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x21))
\r
126 #define FIO2DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x41))
\r
127 #define FIO3DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x61))
\r
128 #define FIO4DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x81))
\r
130 #define FIO0DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x02))
\r
131 #define FIO1DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x22))
\r
132 #define FIO2DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x42))
\r
133 #define FIO3DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x62))
\r
134 #define FIO4DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x82))
\r
136 #define FIO0DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x03))
\r
137 #define FIO1DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x23))
\r
138 #define FIO2DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x43))
\r
139 #define FIO3DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x63))
\r
140 #define FIO4DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x83))
\r
142 #define FIO0DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x00))
\r
143 #define FIO1DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x20))
\r
144 #define FIO2DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x40))
\r
145 #define FIO3DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x60))
\r
146 #define FIO4DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x80))
\r
148 #define FIO0DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x02))
\r
149 #define FIO1DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x22))
\r
150 #define FIO2DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x42))
\r
151 #define FIO3DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x62))
\r
152 #define FIO4DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x82))
\r
154 #define FIO0MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x10))
\r
155 #define FIO1MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x30))
\r
156 #define FIO2MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x40))
\r
157 #define FIO3MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x50))
\r
158 #define FIO4MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x90))
\r
160 #define FIO0MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x11))
\r
161 #define FIO1MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x31))
\r
162 #define FIO2MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x41))
\r
163 #define FIO3MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x51))
\r
164 #define FIO4MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x91))
\r
166 #define FIO0MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x12))
\r
167 #define FIO1MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x32))
\r
168 #define FIO2MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x42))
\r
169 #define FIO3MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x52))
\r
170 #define FIO4MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x92))
\r
172 #define FIO0MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x13))
\r
173 #define FIO1MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x33))
\r
174 #define FIO2MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x43))
\r
175 #define FIO3MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x53))
\r
176 #define FIO4MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x93))
\r
178 #define FIO0MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x10))
\r
179 #define FIO1MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x30))
\r
180 #define FIO2MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x40))
\r
181 #define FIO3MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x50))
\r
182 #define FIO4MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x90))
\r
184 #define FIO0MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x12))
\r
185 #define FIO1MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x32))
\r
186 #define FIO2MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x42))
\r
187 #define FIO3MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x52))
\r
188 #define FIO4MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x92))
\r
190 #define FIO0PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x14))
\r
191 #define FIO1PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x34))
\r
192 #define FIO2PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x44))
\r
193 #define FIO3PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x54))
\r
194 #define FIO4PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x94))
\r
196 #define FIO0PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x15))
\r
197 #define FIO1PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x35))
\r
198 #define FIO2PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x45))
\r
199 #define FIO3PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x55))
\r
200 #define FIO4PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x95))
\r
202 #define FIO0PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x16))
\r
203 #define FIO1PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x36))
\r
204 #define FIO2PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x46))
\r
205 #define FIO3PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x56))
\r
206 #define FIO4PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x96))
\r
208 #define FIO0PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x17))
\r
209 #define FIO1PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x37))
\r
210 #define FIO2PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x47))
\r
211 #define FIO3PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x57))
\r
212 #define FIO4PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x97))
\r
214 #define FIO0PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x14))
\r
215 #define FIO1PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x34))
\r
216 #define FIO2PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x44))
\r
217 #define FIO3PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x54))
\r
218 #define FIO4PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x94))
\r
220 #define FIO0PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x16))
\r
221 #define FIO1PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x36))
\r
222 #define FIO2PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x46))
\r
223 #define FIO3PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x56))
\r
224 #define FIO4PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x96))
\r
226 #define FIO0SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x18))
\r
227 #define FIO1SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x38))
\r
228 #define FIO2SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x48))
\r
229 #define FIO3SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x58))
\r
230 #define FIO4SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x98))
\r
232 #define FIO0SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x19))
\r
233 #define FIO1SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x39))
\r
234 #define FIO2SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x49))
\r
235 #define FIO3SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x59))
\r
236 #define FIO4SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x99))
\r
238 #define FIO0SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1A))
\r
239 #define FIO1SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3A))
\r
240 #define FIO2SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4A))
\r
241 #define FIO3SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5A))
\r
242 #define FIO4SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9A))
\r
244 #define FIO0SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1B))
\r
245 #define FIO1SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3B))
\r
246 #define FIO2SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4B))
\r
247 #define FIO3SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5B))
\r
248 #define FIO4SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9B))
\r
250 #define FIO0SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x18))
\r
251 #define FIO1SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x38))
\r
252 #define FIO2SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x48))
\r
253 #define FIO3SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x58))
\r
254 #define FIO4SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x98))
\r
256 #define FIO0SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1A))
\r
257 #define FIO1SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3A))
\r
258 #define FIO2SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4A))
\r
259 #define FIO3SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5A))
\r
260 #define FIO4SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9A))
\r
262 #define FIO0CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1C))
\r
263 #define FIO1CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3C))
\r
264 #define FIO2CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4C))
\r
265 #define FIO3CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5C))
\r
266 #define FIO4CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9C))
\r
268 #define FIO0CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1D))
\r
269 #define FIO1CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3D))
\r
270 #define FIO2CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4D))
\r
271 #define FIO3CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5D))
\r
272 #define FIO4CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9D))
\r
274 #define FIO0CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1E))
\r
275 #define FIO1CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3E))
\r
276 #define FIO2CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4E))
\r
277 #define FIO3CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5E))
\r
278 #define FIO4CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9E))
\r
280 #define FIO0CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1F))
\r
281 #define FIO1CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3F))
\r
282 #define FIO2CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4F))
\r
283 #define FIO3CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5F))
\r
284 #define FIO4CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9F))
\r
286 #define FIO0CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1C))
\r
287 #define FIO1CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3C))
\r
288 #define FIO2CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4C))
\r
289 #define FIO3CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5C))
\r
290 #define FIO4CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9C))
\r
292 #define FIO0CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1E))
\r
293 #define FIO1CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3E))
\r
294 #define FIO2CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4E))
\r
295 #define FIO3CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5E))
\r
296 #define FIO4CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9E))
\r
298 /* GPIO Interrupt Registers */
\r
299 #define GPIO_INT_BASE_ADDR 0x40028000
\r
300 #define IO0IntEnR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x90))
\r
301 #define IO0IntEnF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x94))
\r
302 #define IO0IntStatR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x84))
\r
303 #define IO0IntStatF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x88))
\r
304 #define IO0IntClr (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x8C))
\r
306 #define IO2IntEnR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xB0))
\r
307 #define IO2IntEnF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xB4))
\r
308 #define IO2IntStatR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xA4))
\r
309 #define IO2IntStatF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xA8))
\r
310 #define IO2IntClr (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xAC))
\r
312 #define IOIntStatus (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x80))
\r
316 #define TMR0_BASE_ADDR 0x40004000
\r
317 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
\r
318 #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
\r
319 #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
\r
320 #define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
\r
321 #define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
\r
322 #define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
\r
323 #define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
\r
324 #define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
\r
325 #define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
\r
326 #define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
\r
327 #define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
\r
328 #define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
\r
329 #define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
\r
330 #define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
\r
331 #define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
\r
332 #define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
\r
333 #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
\r
336 #define TMR1_BASE_ADDR 0x40008000
\r
337 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
\r
338 #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
\r
339 #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
\r
340 #define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
\r
341 #define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
\r
342 #define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
\r
343 #define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
\r
344 #define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
\r
345 #define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
\r
346 #define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
\r
347 #define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
\r
348 #define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
\r
349 #define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
\r
350 #define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
\r
351 #define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
\r
352 #define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
\r
353 #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
\r
356 #define TMR2_BASE_ADDR 0x40090000
\r
357 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
\r
358 #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
\r
359 #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
\r
360 #define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
\r
361 #define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
\r
362 #define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
\r
363 #define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
\r
364 #define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
\r
365 #define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
\r
366 #define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
\r
367 #define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
\r
368 #define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
\r
369 #define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
\r
370 #define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
\r
371 #define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
\r
372 #define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
\r
373 #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
\r
376 #define TMR3_BASE_ADDR 0x40094000
\r
377 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
\r
378 #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
\r
379 #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
\r
380 #define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
\r
381 #define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
\r
382 #define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
\r
383 #define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
\r
384 #define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
\r
385 #define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
\r
386 #define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
\r
387 #define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
\r
388 #define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
\r
389 #define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
\r
390 #define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
\r
391 #define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
\r
392 #define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
\r
393 #define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
\r
396 /* Pulse Width Modulator (PWM) */
\r
397 #define PWM1_BASE_ADDR 0x40018000
\r
398 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
\r
399 #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
\r
400 #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
\r
401 #define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
\r
402 #define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
\r
403 #define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
\r
404 #define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
\r
405 #define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
\r
406 #define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
\r
407 #define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
\r
408 #define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
\r
409 #define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
\r
410 #define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
\r
411 #define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
\r
412 #define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
\r
413 #define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
\r
414 #define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
\r
415 #define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
\r
416 #define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
\r
417 #define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
\r
418 #define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
\r
421 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
\r
422 #define UART0_BASE_ADDR 0x4000C000
\r
423 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
\r
424 #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
\r
425 #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
\r
426 #define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
\r
427 #define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
\r
428 #define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
\r
429 #define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
\r
430 #define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
\r
431 #define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
\r
432 #define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
\r
433 #define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
\r
434 #define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
\r
435 #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
\r
436 #define U0RS485CTRL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x4C))
\r
437 #define U0ADRMATCH (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x50))
\r
439 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
\r
440 #define UART1_BASE_ADDR 0x40010000
\r
441 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
\r
442 #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
\r
443 #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
\r
444 #define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
\r
445 #define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
\r
446 #define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
\r
447 #define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
\r
448 #define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
\r
449 #define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
\r
450 #define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
\r
451 #define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
\r
452 #define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
\r
453 #define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
\r
454 #define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
\r
455 #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
\r
456 #define U1RS485CTRL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x4C))
\r
457 #define U1ADRMATCH (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x50))
\r
458 #define U1RS485DLY (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x54))
\r
460 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
\r
461 #define UART2_BASE_ADDR 0x40098000
\r
462 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
\r
463 #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
\r
464 #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
\r
465 #define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
\r
466 #define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
\r
467 #define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
\r
468 #define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
\r
469 #define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
\r
470 #define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
\r
471 #define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
\r
472 #define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
\r
473 #define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
\r
474 #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
\r
475 #define U2RS485CTRL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x4C))
\r
476 #define U2ADRMATCH (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x50))
\r
478 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
\r
479 #define UART3_BASE_ADDR 0x4009C000
\r
480 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
\r
481 #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
\r
482 #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
\r
483 #define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
\r
484 #define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
\r
485 #define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
\r
486 #define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
\r
487 #define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
\r
488 #define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
\r
489 #define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
\r
490 #define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
\r
491 #define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
\r
492 #define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
\r
493 #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
\r
494 #define U3RS485CTRL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x4C))
\r
495 #define U3ADRMATCH (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x50))
\r
498 /* SPI0 (Serial Peripheral Interface 0) */
\r
499 #define SPI0_BASE_ADDR 0x40020000
\r
500 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
\r
501 #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
\r
502 #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
\r
503 #define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
\r
504 #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
\r
506 /* SSP0 Controller */
\r
507 #define SSP0_BASE_ADDR 0x40088000
\r
508 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
\r
509 #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
\r
510 #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
\r
511 #define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
\r
512 #define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
\r
513 #define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
\r
514 #define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
\r
515 #define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
\r
516 #define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
\r
517 #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
\r
519 /* SSP1 Controller */
\r
520 #define SSP1_BASE_ADDR 0x40030000
\r
521 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
\r
522 #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
\r
523 #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
\r
524 #define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
\r
525 #define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
\r
526 #define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
\r
527 #define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
\r
528 #define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
\r
529 #define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
\r
530 #define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
\r
533 /* I2C Interface 0 */
\r
534 #define I2C0_BASE_ADDR 0x4001C000
\r
535 #define I2C0CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
\r
536 #define I2C0STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
\r
537 #define I2C0DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
\r
538 #define I2C0ADR0 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
\r
539 #define I2C0SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
\r
540 #define I2C0SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
\r
541 #define I2C0CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
\r
542 #define I2C0MMCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x1C))
\r
543 #define I2C0ADR1 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x20))
\r
544 #define I2C0ADR2 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x24))
\r
545 #define I2C0ADR3 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x28))
\r
546 #define I2C0DATBUFFER (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x2C))
\r
547 #define I2C0MASK0 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x30))
\r
548 #define I2C0MASK1 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x34))
\r
549 #define I2C0MASK2 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x38))
\r
550 #define I2C0MASK3 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x3C))
\r
552 /* I2C Interface 1 */
\r
553 #define I2C1_BASE_ADDR 0x4005C000
\r
554 #define I2C1CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
\r
555 #define I2C1STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
\r
556 #define I2C1DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
\r
557 #define I2C1ADR0 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
\r
558 #define I2C1SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
\r
559 #define I2C1SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
\r
560 #define I2C1CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
\r
561 #define I2C1MMCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x1C))
\r
562 #define I2C1ADR1 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x20))
\r
563 #define I2C1ADR2 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x24))
\r
564 #define I2C1ADR3 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x28))
\r
565 #define I2C1DATBUFFER (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x2C))
\r
566 #define I2C1MASK0 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x30))
\r
567 #define I2C1MASK1 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x34))
\r
568 #define I2C1MASK2 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x38))
\r
569 #define I2C1MASK3 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x3C))
\r
571 /* I2C Interface 2 */
\r
572 #define I2C2_BASE_ADDR 0x400A0000
\r
573 #define I2C2CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
\r
574 #define I2C2STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
\r
575 #define I2C2DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
\r
576 #define I2C2ADR0 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
\r
577 #define I2C2SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
\r
578 #define I2C2SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
\r
579 #define I2C2CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
\r
580 #define I2C2MMCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x1C))
\r
581 #define I2C2ADR1 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x20))
\r
582 #define I2C2ADR2 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x24))
\r
583 #define I2C2ADR3 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x28))
\r
584 #define I2C2DATBUFFER (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x2C))
\r
585 #define I2C2MASK0 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x30))
\r
586 #define I2C2MASK1 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x34))
\r
587 #define I2C2MASK2 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x38))
\r
588 #define I2C2MASK3 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x3C))
\r
591 /* I2S Interface Controller (I2S) */
\r
592 #define I2S_BASE_ADDR 0x400A8000
\r
593 #define I2SDAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
\r
594 #define I2SDAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
\r
595 #define I2STXFIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
\r
596 #define I2SRXFIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
\r
597 #define I2SSTATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
\r
598 #define I2SDMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
\r
599 #define I2SDMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
\r
600 #define I2SIRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
\r
601 #define I2STXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
\r
602 #define I2SRXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
\r
603 #define I2STXBITRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x28))
\r
604 #define I2SRXBITRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x2C))
\r
605 #define I2STXMODE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x30))
\r
606 #define I2SRXMODE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x34))
\r
609 /* Repetitive Interrupt Timer (RIT) */
\r
610 #define RIT_BASE_ADDR 0x400B4000
\r
611 #define RICOMPVAL (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x00))
\r
612 #define RIMASK (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x04))
\r
613 #define RICTRL (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x08))
\r
614 #define RICOUNTER (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x0C))
\r
617 /* Real Time Clock (RTC) */
\r
618 #define RTC_BASE_ADDR 0x40024000
\r
619 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
\r
620 #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
\r
621 #define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
\r
622 #define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
\r
623 #define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
\r
624 #define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
\r
625 #define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
\r
626 #define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
\r
627 #define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
\r
628 #define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
\r
629 #define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
\r
630 #define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
\r
631 #define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
\r
632 #define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
\r
633 #define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
\r
634 #define RTC_CALIBRATION (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
\r
635 #define RTC_GPREG0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x44))
\r
636 #define RTC_GPREG1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x48))
\r
637 #define RTC_GPREG2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x4C))
\r
638 #define RTC_GPREG3 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x50))
\r
639 #define RTC_GPREG4 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x54))
\r
640 #define RTC_WAKEUPDIS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x58))
\r
641 #define RTC_PWRCTRL (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x5c))
\r
642 #define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
\r
643 #define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
\r
644 #define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
\r
645 #define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
\r
646 #define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
\r
647 #define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
\r
648 #define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
\r
649 #define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
\r
652 /* Watchdog Timer (WDT) */
\r
653 #define WDT_BASE_ADDR 0x40000000
\r
654 #define WDMOD (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x00))
\r
655 #define WDTC (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x04))
\r
656 #define WDFEED (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x08))
\r
657 #define WDTV (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x0C))
\r
658 #define WDCLKSEL (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x10))
\r
661 /* A/D Converter 0 (ADC0) */
\r
662 #define AD0_BASE_ADDR 0x40034000
\r
663 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
\r
664 #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
\r
665 #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
\r
666 #define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
\r
667 #define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
\r
668 #define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
\r
669 #define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
\r
670 #define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
\r
671 #define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
\r
672 #define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
\r
673 #define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
\r
674 #define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
\r
675 #define ADTRIM (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x34))
\r
678 /* D/A Converter (DAC) */
\r
679 #define DAC_BASE_ADDR 0x4008C000
\r
680 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
\r
681 #define DACCTRL (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x04))
\r
682 #define DACCNTVAL (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x08))
\r
685 /* Motor Control PWM */
\r
686 #define MCPWM_BASE_ADDR 0x400B8000
\r
687 #define MCCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x00))
\r
688 #define MCCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x04))
\r
689 #define MCCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x08))
\r
690 #define MCCAPCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x0C))
\r
691 #define MCCAPCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x10))
\r
692 #define MCCAPCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x14))
\r
693 #define MCTIM0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x18))
\r
694 #define MCTIM1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x1C))
\r
695 #define MCTIM2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x20))
\r
696 #define MCPER0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x24))
\r
697 #define MCPER1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x28))
\r
698 #define MCPER2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x2C))
\r
699 #define MCPW0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x30))
\r
700 #define MCPW1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x34))
\r
701 #define MCPW2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x38))
\r
702 #define MCDEADTIME (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x3C))
\r
703 #define MCCCP (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x40))
\r
704 #define MCCR0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x44))
\r
705 #define MCCR1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x48))
\r
706 #define MCCR2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x4C))
\r
707 #define MCINTEN (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x50))
\r
708 #define MCINTEN_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x54))
\r
709 #define MCINTEN_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x58))
\r
710 #define MCCNTCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x5C))
\r
711 #define MCCNTCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x60))
\r
712 #define MCCNTCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x64))
\r
713 #define MCINTFLAG (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x68))
\r
714 #define MCINTFLAG_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x6C))
\r
715 #define MCINTFLAG_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x70))
\r
716 #define MCCAP_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x74))
\r
719 /* Quadrature Encoder Interface (QEI) */
\r
720 #define QEI_BASE_ADDR 0x400BC000
\r
722 /* QEI Control Registers */
\r
723 #define QEICON (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x000))
\r
724 #define QEISTAT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x004))
\r
725 #define QEICONF (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x008))
\r
727 /* QEI Position, Index, and Timer Registers */
\r
728 #define QEIPOS (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x00C))
\r
729 #define QEIMAXPSOS (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x010))
\r
730 #define CMPOS0 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x014))
\r
731 #define CMPOS1 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x018))
\r
732 #define CMPOS2 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x01C))
\r
733 #define INXCNT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x020))
\r
734 #define INXCMP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x024))
\r
735 #define QEILOAD (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x028))
\r
736 #define QEITIME (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x02C))
\r
737 #define QEIVEL (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x030))
\r
738 #define QEICAP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x034))
\r
739 #define VELCOMP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x038))
\r
740 #define FILTER (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x03C))
\r
742 /* QEI Interrupt registers */
\r
743 #define QEIIES (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFDC))
\r
744 #define QEIIEC (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFD8))
\r
745 #define QEIINTSTAT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE0))
\r
746 #define QEIIE (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE4))
\r
747 #define QEICLR (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE8))
\r
748 #define QEISET (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFEC))
\r
751 /* CAN Controllers and Acceptance Filter */
\r
753 /* CAN Acceptance Filter */
\r
754 #define CAN_AF_BASE_ADDR 0x4003C000
\r
755 #define AFMR (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x00))
\r
756 #define SFF_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x04))
\r
757 #define SFF_GRP_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x08))
\r
758 #define EFF_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x0C))
\r
759 #define EFF_GRP_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x10))
\r
760 #define ENDofTable (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x14))
\r
761 #define LUTerrAd (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x18))
\r
762 #define LUTerr (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x1C))
\r
763 #define FCANIE (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x20))
\r
764 #define FCANIC0 (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x24))
\r
765 #define FCANIC1 (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x28))
\r
767 /* CAN Centralized Registers */
\r
768 #define CAN_BASE_ADDR 0x40040000
\r
769 #define CANTxSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x00))
\r
770 #define CANRxSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x04))
\r
771 #define CANMSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x08))
\r
773 /* CAN1 Controller */
\r
774 #define CAN1_BASE_ADDR 0x40044000
\r
775 #define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
\r
776 #define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
\r
777 #define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
\r
778 #define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
\r
779 #define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
\r
780 #define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
\r
781 #define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
\r
782 #define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
\r
783 #define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
\r
784 #define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
\r
785 #define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
\r
786 #define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
\r
787 #define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
\r
788 #define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
\r
789 #define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
\r
790 #define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
\r
791 #define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
\r
792 #define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
\r
793 #define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
\r
794 #define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
\r
795 #define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
\r
796 #define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
\r
797 #define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
\r
798 #define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
\r
800 /* CAN2 Controller */
\r
801 #define CAN2_BASE_ADDR 0x40048000
\r
802 #define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
\r
803 #define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
\r
804 #define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
\r
805 #define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
\r
806 #define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
\r
807 #define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
\r
808 #define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
\r
809 #define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
\r
810 #define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
\r
811 #define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
\r
812 #define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
\r
813 #define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
\r
814 #define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
\r
815 #define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
\r
816 #define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
\r
817 #define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
\r
818 #define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
\r
819 #define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
\r
820 #define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
\r
821 #define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
\r
822 #define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
\r
823 #define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
\r
824 #define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
\r
825 #define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
\r
828 /* General Purpose DMA Controller (GPDMA) */
\r
829 #define DMA_BASE_ADDR 0x50004000
\r
830 #define DMACIntStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
\r
831 #define DMACIntTCStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
\r
832 #define DMACIntTCClear (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
\r
833 #define DMACIntErrStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
\r
834 #define DMACIntErrClr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
\r
835 #define DMACRawIntTCStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
\r
836 #define DMACRawIntErrStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
\r
837 #define DMACEnbldChns (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
\r
838 #define DMACSoftBReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
\r
839 #define DMACSoftSReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
\r
840 #define DMACSoftLBReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
\r
841 #define DMACSoftLSReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
\r
842 #define DMACConfig (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
\r
843 #define DMACSync (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
\r
845 /* DMA Channel 0 Registers */
\r
846 #define DMACC0SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
\r
847 #define DMACC0DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
\r
848 #define DMACC0LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
\r
849 #define DMACC0Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
\r
850 #define DMACC0Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
\r
852 /* DMA Channel 1 Registers */
\r
853 #define DMACC1SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
\r
854 #define DMACC1DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
\r
855 #define DMACC1LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
\r
856 #define DMACC1Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
\r
857 #define DMACC1Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
\r
859 /* DMA Channel 2 Registers */
\r
860 #define DMACC2SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x140))
\r
861 #define DMACC2DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x144))
\r
862 #define DMACC2LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x148))
\r
863 #define DMACC2Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x14C))
\r
864 #define DMACC2Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x150))
\r
866 /* DMA Channel 3 Registers */
\r
867 #define DMACC3SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x160))
\r
868 #define DMACC3DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x164))
\r
869 #define DMACC3LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x168))
\r
870 #define DMACC3Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x16C))
\r
871 #define DMACC3Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x170))
\r
873 /* DMA Channel 4 Registers */
\r
874 #define DMACC4SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x180))
\r
875 #define DMACC4DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x184))
\r
876 #define DMACC4LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x188))
\r
877 #define DMACC4Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x18C))
\r
878 #define DMACC4Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x190))
\r
880 /* DMA Channel 5 Registers */
\r
881 #define DMACC5SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A0))
\r
882 #define DMACC5DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A4))
\r
883 #define DMACC5LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A8))
\r
884 #define DMACC5Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1AC))
\r
885 #define DMACC5Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1B0))
\r
887 /* DMA Channel 6 Registers */
\r
888 #define DMACC6SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C0))
\r
889 #define DMACC6DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C4))
\r
890 #define DMACC6LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C8))
\r
891 #define DMACC6Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1CC))
\r
892 #define DMACC6Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1D0))
\r
894 /* DMA Channel 7 Registers */
\r
895 #define DMACC7SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E0))
\r
896 #define DMACC7DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E4))
\r
897 #define DMACC7LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E8))
\r
898 #define DMACC7Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1EC))
\r
899 #define DMACC7Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1F0))
\r
902 /* USB Controller */
\r
903 #define USB_BASE_ADDR 0x5000C000
\r
905 #define USBIntSt (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1C0))
\r
908 /* USB Device Controller */
\r
910 /* USB Device Clock Control Registers */
\r
911 #define USBClkCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF4))
\r
912 #define USBClkSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF8))
\r
914 /* USB Device Interrupt Registers */
\r
915 #define USBDevIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x200))
\r
916 #define USBDevIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x204))
\r
917 #define USBDevIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x208))
\r
918 #define USBDevIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20C))
\r
919 #define USBDevIntPri (*(volatile unsigned long *)(USB_BASE_ADDR + 0x22C))
\r
921 /* USB Device Endpoint Interrupt Registers */
\r
922 #define USBEpIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x230))
\r
923 #define USBEpIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x234))
\r
924 #define USBEpIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x238))
\r
925 #define USBEpIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x23C))
\r
926 #define USBEpIntPri (*(volatile unsigned long *)(USB_BASE_ADDR + 0x240))
\r
928 /* USB Device Endpoint Realization Registers */
\r
929 #define USBReEp (*(volatile unsigned long *)(USB_BASE_ADDR + 0x244))
\r
930 #define USBEpInd (*(volatile unsigned long *)(USB_BASE_ADDR + 0x248))
\r
931 #define USBMaxPSize (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24C))
\r
933 /* USB Device SIE Command Reagisters */
\r
934 #define USBCmdCode (*(volatile unsigned long *)(USB_BASE_ADDR + 0x210))
\r
935 #define USBCmdData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x214))
\r
937 /* USB Device Data Transfer Registers */
\r
938 #define USBRxData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x218))
\r
939 #define USBTxData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x21C))
\r
940 #define USBRxPLen (*(volatile unsigned long *)(USB_BASE_ADDR + 0x220))
\r
941 #define USBTxPLen (*(volatile unsigned long *)(USB_BASE_ADDR + 0x224))
\r
942 #define USBCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x228))
\r
944 /* USB Device DMA Registers */
\r
945 #define USBDMARSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x250))
\r
946 #define USBDMARClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x254))
\r
947 #define USBDMARSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x258))
\r
948 #define USBUDCAH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x280))
\r
949 #define USBEpDMASt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x284))
\r
950 #define USBEpDMAEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x288))
\r
951 #define USBEpDMADis (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28C))
\r
952 #define USBDMAIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x290))
\r
953 #define USBDMAIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x294))
\r
954 #define USBEoTIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A0))
\r
955 #define USBEoTIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A4))
\r
956 #define USBEoTIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A8))
\r
957 #define USBNDDRIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2AC))
\r
958 #define USBNDDRIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B0))
\r
959 #define USBNDDRIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B4))
\r
960 #define USBSysErrIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B8))
\r
961 #define USBSysErrIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2BC))
\r
962 #define USBSysErrIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C0))
\r
965 /* USB Host Controller */
\r
966 #define HcRevision (*(volatile unsigned long *)(USB_BASE_ADDR + 0x000))
\r
967 #define HcControl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x004))
\r
968 #define HcCommandStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x008))
\r
969 #define HcInterruptStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00C))
\r
970 #define HcInterruptEnable (*(volatile unsigned long *)(USB_BASE_ADDR + 0x010))
\r
971 #define HcInterruptDisable (*(volatile unsigned long *)(USB_BASE_ADDR + 0x014))
\r
972 #define HcHCCA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x018))
\r
973 #define HcPeriodCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x01C))
\r
974 #define HcControlHeadED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x020))
\r
975 #define HcControlCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x024))
\r
976 #define HcBulkHeadED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x028))
\r
977 #define HcBulkCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x02C))
\r
978 #define HcDoneHead (*(volatile unsigned long *)(USB_BASE_ADDR + 0x030))
\r
979 #define HcFmInterval (*(volatile unsigned long *)(USB_BASE_ADDR + 0x034))
\r
980 #define HcFmRemaining (*(volatile unsigned long *)(USB_BASE_ADDR + 0x038))
\r
981 #define HcFmNumber (*(volatile unsigned long *)(USB_BASE_ADDR + 0x03C))
\r
982 #define HcPeriodStart (*(volatile unsigned long *)(USB_BASE_ADDR + 0x040))
\r
983 #define HcLSThreshold (*(volatile unsigned long *)(USB_BASE_ADDR + 0x044))
\r
984 #define HcRhDescriptorA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x048))
\r
985 #define HcRhDescriptorB (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04C))
\r
986 #define HcRhStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x050))
\r
987 #define HcRhPortStatus1 (*(volatile unsigned long *)(USB_BASE_ADDR + 0x054))
\r
988 #define HcRhPortStatus2 (*(volatile unsigned long *)(USB_BASE_ADDR + 0x058))
\r
991 /* USB OTG Controller */
\r
993 /* USB OTG Registers */
\r
994 #define OTGIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x100))
\r
995 #define OTGIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x104))
\r
996 #define OTGIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x108))
\r
997 #define OTGIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10C))
\r
998 #define OTGIntCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x110))
\r
999 #define OTGTmr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x114))
\r
1001 /* USB OTG I2C Registers */
\r
1002 #define I2C_RX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x300))
\r
1003 #define I2C_TX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x300))
\r
1004 #define I2C_STS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x304))
\r
1005 #define I2C_CTL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x308))
\r
1006 #define I2C_CLKHI (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30C))
\r
1007 #define I2C_CLKLO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x310))
\r
1009 /* USB OTG Clock Control Registers */
\r
1010 #define OTGClkCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF4))
\r
1011 #define OTGClkSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF8))
\r
1014 /* Ethernet MAC */
\r
1015 #define MAC_BASE_ADDR 0x50000000
\r
1017 /* MAC Registers */
\r
1018 #define ETH_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000))
\r
1019 #define ETH_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004))
\r
1020 #define ETH_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008))
\r
1021 #define ETH_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C))
\r
1022 #define ETH_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010))
\r
1023 #define ETH_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014))
\r
1024 #define ETH_PHYSUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018))
\r
1025 #define ETH_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C))
\r
1026 #define ETH_MIICFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020))
\r
1027 #define ETH_MIICMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024))
\r
1028 #define ETH_MIIADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028))
\r
1029 #define ETH_MIIWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C))
\r
1030 #define ETH_MIIRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030))
\r
1031 #define ETH_MIIIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034))
\r
1032 #define ETH_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040))
\r
1033 #define ETH_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044))
\r
1034 #define ETH_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048))
\r
1036 /* MAC Control Registers */
\r
1037 #define ETH_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100))
\r
1038 #define ETH_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104))
\r
1039 #define ETH_RXDESC (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108))
\r
1040 #define ETH_RXSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C))
\r
1041 #define ETH_RXDESCRNO (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110))
\r
1042 #define ETH_RXPRODIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114))
\r
1043 #define ETH_RXCONSIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118))
\r
1044 #define ETH_TXDESC (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C))
\r
1045 #define ETH_TXSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120))
\r
1046 #define ETH_TXDESCRNO (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124))
\r
1047 #define ETH_TXPRODIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128))
\r
1048 #define ETH_TXCONSIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C))
\r
1049 #define ETH_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158))
\r
1050 #define ETH_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C))
\r
1051 #define ETH_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160))
\r
1052 #define ETH_FLOWCNTCOUNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170))
\r
1053 #define ETH_FLOWCNTSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174))
\r
1055 /* MAX Rx Filter Registers */
\r
1056 #define ETH_RXFILTERCTL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200))
\r
1057 #define ETH_RXFILTERWOLSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204))
\r
1058 #define ETH_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208))
\r
1059 #define ETH_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210))
\r
1060 #define ETH_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214))
\r
1062 /* MAC Module Control Registers */
\r
1063 #define ETH_INSTSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0))
\r
1064 #define ETH_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4))
\r
1065 #define ETH_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8))
\r
1066 #define ETH_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC))
\r
1067 #define ETH_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4))
\r
1069 #define MAC_Module_ID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC))
\r
1071 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
\r
1072 #define MAC_BASE_ADDR 0x50000000
\r
1073 #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
\r
1074 #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
\r
1075 #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
\r
1076 #define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
\r
1077 #define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
\r
1078 #define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
\r
1079 #define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
\r
1080 #define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
\r
1081 #define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
\r
1082 #define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
\r
1083 #define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
\r
1084 #define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
\r
1085 #define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
\r
1086 #define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
\r
1088 #define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
\r
1089 #define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
\r
1090 #define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
\r
1092 #define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
\r
1093 #define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
\r
1094 #define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
\r
1095 #define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
\r
1096 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
\r
1097 #define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
\r
1098 #define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
\r
1099 #define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
\r
1100 #define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
\r
1101 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
\r
1102 #define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
\r
1103 #define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
\r
1105 #define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
\r
1106 #define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
\r
1107 #define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
\r
1109 #define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
\r
1110 #define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
\r
1112 #define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
\r
1113 #define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
\r
1114 #define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
\r
1116 #define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
\r
1117 #define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
\r
1119 #define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
\r
1120 #define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
\r
1121 #define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
\r
1122 #define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
\r
1124 #define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
\r
1125 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
\r
1127 #define PCONP_PCTIM0 0x00000002
\r
1128 #define PCONP_PCTIM1 0x00000004
\r
1129 #define PCONP_PCUART0 0x00000008
\r
1130 #define PCONP_PCUART1 0x00000010
\r
1131 #define PCONP_PCPWM1 0x00000040
\r
1132 #define PCONP_PCI2C0 0x00000080
\r
1133 #define PCONP_PCSPI 0x00000100
\r
1134 #define PCONP_PCRTC 0x00000200
\r
1135 #define PCONP_PCSSP1 0x00000400
\r
1136 #define PCONP_PCAD 0x00001000
\r
1137 #define PCONP_PCCAN1 0x00002000
\r
1138 #define PCONP_PCCAN2 0x00004000
\r
1139 #define PCONP_PCGPIO 0x00008000
\r
1140 #define PCONP_PCRIT 0x00010000
\r
1141 #define PCONP_PCMCPWM 0x00020000
\r
1142 #define PCONP_PCQEI 0x00040000
\r
1143 #define PCONP_PCI2C1 0x00080000
\r
1144 #define PCONP_PCSSP0 0x00200000
\r
1145 #define PCONP_PCTIM2 0x00400000
\r
1146 #define PCONP_PCTIM3 0x00800000
\r
1147 #define PCONP_PCUART2 0x01000000
\r
1148 #define PCONP_PCUART3 0x02000000
\r
1149 #define PCONP_PCI2C2 0x04000000
\r
1150 #define PCONP_PCI2S 0x08000000
\r
1151 #define PCONP_PCGPDMA 0x20000000
\r
1152 #define PCONP_PCENET 0x40000000
\r
1153 #define PCONP_PCUSB 0x80000000
\r
1155 #define PLLCON_PLLE 0x00000001
\r
1156 #define PLLCON_PLLC 0x00000002
\r
1157 #define PLLCON_MASK 0x00000003
\r
1159 #define PLLCFG_MUL1 0x00000000
\r
1160 #define PLLCFG_MUL2 0x00000001
\r
1161 #define PLLCFG_MUL3 0x00000002
\r
1162 #define PLLCFG_MUL4 0x00000003
\r
1163 #define PLLCFG_MUL5 0x00000004
\r
1164 #define PLLCFG_MUL6 0x00000005
\r
1165 #define PLLCFG_MUL7 0x00000006
\r
1166 #define PLLCFG_MUL8 0x00000007
\r
1167 #define PLLCFG_MUL9 0x00000008
\r
1168 #define PLLCFG_MUL10 0x00000009
\r
1169 #define PLLCFG_MUL11 0x0000000A
\r
1170 #define PLLCFG_MUL12 0x0000000B
\r
1171 #define PLLCFG_MUL13 0x0000000C
\r
1172 #define PLLCFG_MUL14 0x0000000D
\r
1173 #define PLLCFG_MUL15 0x0000000E
\r
1174 #define PLLCFG_MUL16 0x0000000F
\r
1175 #define PLLCFG_MUL17 0x00000010
\r
1176 #define PLLCFG_MUL18 0x00000011
\r
1177 #define PLLCFG_MUL19 0x00000012
\r
1178 #define PLLCFG_MUL20 0x00000013
\r
1179 #define PLLCFG_MUL21 0x00000014
\r
1180 #define PLLCFG_MUL22 0x00000015
\r
1181 #define PLLCFG_MUL23 0x00000016
\r
1182 #define PLLCFG_MUL24 0x00000017
\r
1183 #define PLLCFG_MUL25 0x00000018
\r
1184 #define PLLCFG_MUL26 0x00000019
\r
1185 #define PLLCFG_MUL27 0x0000001A
\r
1186 #define PLLCFG_MUL28 0x0000001B
\r
1187 #define PLLCFG_MUL29 0x0000001C
\r
1188 #define PLLCFG_MUL30 0x0000001D
\r
1189 #define PLLCFG_MUL31 0x0000001E
\r
1190 #define PLLCFG_MUL32 0x0000001F
\r
1191 #define PLLCFG_MUL33 0x00000020
\r
1192 #define PLLCFG_MUL34 0x00000021
\r
1193 #define PLLCFG_MUL35 0x00000022
\r
1194 #define PLLCFG_MUL36 0x00000023
\r
1196 #define PLLCFG_DIV1 0x00000000
\r
1197 #define PLLCFG_DIV2 0x00010000
\r
1198 #define PLLCFG_DIV3 0x00020000
\r
1199 #define PLLCFG_DIV4 0x00030000
\r
1200 #define PLLCFG_DIV5 0x00040000
\r
1201 #define PLLCFG_DIV6 0x00050000
\r
1202 #define PLLCFG_DIV7 0x00060000
\r
1203 #define PLLCFG_DIV8 0x00070000
\r
1204 #define PLLCFG_DIV9 0x00080000
\r
1205 #define PLLCFG_DIV10 0x00090000
\r
1206 #define PLLCFG_MASK 0x00FF7FFF
\r
1208 #define PLLSTAT_MSEL_MASK 0x00007FFF
\r
1209 #define PLLSTAT_NSEL_MASK 0x00FF0000
\r
1211 #define PLLSTAT_PLLE (1 << 24)
\r
1212 #define PLLSTAT_PLLC (1 << 25)
\r
1213 #define PLLSTAT_PLOCK (1 << 26)
\r
1215 #define PLLFEED_FEED1 0x000000AA
\r
1216 #define PLLFEED_FEED2 0x00000055
\r
1218 #define NVIC_IRQ_WDT 0u // IRQ0, exception number 16
\r
1219 #define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17
\r
1220 #define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18
\r
1221 #define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19
\r
1222 #define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20
\r
1223 #define NVIC_IRQ_UART0 5u // IRQ5, exception number 21
\r
1224 #define NVIC_IRQ_UART1 6u // IRQ6, exception number 22
\r
1225 #define NVIC_IRQ_UART2 7u // IRQ7, exception number 23
\r
1226 #define NVIC_IRQ_UART3 8u // IRQ8, exception number 24
\r
1227 #define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25
\r
1228 #define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26
\r
1229 #define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27
\r
1230 #define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28
\r
1231 #define NVIC_IRQ_SPI 13u // IRQ13, exception number 29
\r
1232 #define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30
\r
1233 #define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31
\r
1234 #define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32
\r
1235 #define NVIC_IRQ_RTC 17u // IRQ17, exception number 33
\r
1236 #define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34
\r
1237 #define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35
\r
1238 #define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36
\r
1239 #define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37
\r
1240 #define NVIC_IRQ_ADC 22u // IRQ22, exception number 38
\r
1241 #define NVIC_IRQ_BOD 23u // IRQ23, exception number 39
\r
1242 #define NVIC_IRQ_USB 24u // IRQ24, exception number 40
\r
1243 #define NVIC_IRQ_CAN 25u // IRQ25, exception number 41
\r
1244 #define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42
\r
1245 #define NVIC_IRQ_I2S 27u // IRQ27, exception number 43
\r
1246 #define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44
\r
1247 #define NVIC_IRQ_RIT 29u // IRQ29, exception number 45
\r
1248 #define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46
\r
1249 #define NVIC_IRQ_QE 31u // IRQ31, exception number 47
\r
1250 #define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48
\r
1251 #define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49
\r
1252 #define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50
\r
1256 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
\r
1257 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
\r
1258 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
\r
1259 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
\r
1260 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
\r
1261 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
\r
1262 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
\r
1263 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
\r
1264 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
\r
1266 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
\r
1267 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
\r
1268 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
\r
1269 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
\r
1270 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
\r
1271 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
\r
1272 UART0_IRQn = 5, /*!< UART0 Interrupt */
\r
1273 UART1_IRQn = 6, /*!< UART1 Interrupt */
\r
1274 UART2_IRQn = 7, /*!< UART2 Interrupt */
\r
1275 UART3_IRQn = 8, /*!< UART3 Interrupt */
\r
1276 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
\r
1277 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
\r
1278 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
\r
1279 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
\r
1280 SPI_IRQn = 13, /*!< SPI Interrupt */
\r
1281 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
\r
1282 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
\r
1283 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
\r
1284 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
\r
1285 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
\r
1286 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
\r
1287 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
\r
1288 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
\r
1289 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
\r
1290 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
\r
1291 USB_IRQn = 24, /*!< USB Interrupt */
\r
1292 CAN_IRQn = 25, /*!< CAN Interrupt */
\r
1293 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
\r
1294 I2S_IRQn = 27, /*!< I2S Interrupt */
\r
1295 ENET_IRQn = 28, /*!< Ethernet Interrupt */
\r
1296 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
\r
1297 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
\r
1298 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
\r
1299 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
\r
1302 #endif // __LPC17xx_H
\r
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