1 /******************************************************************************
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2 * LPC17xx.h: Header file for NXP LPC17xx Cortex-M3 Family Microprocessors
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3 * The header file is the super set of all hardware definitions of the
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4 * peripherals for the LPC17xx/24xx microprocessor.
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6 * Copyright(C) 2006-2008, NXP Semiconductor
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7 * All rights reserved.
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11 ******************************************************************************/
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16 //#include "sysdefs.h"
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18 #define SRAM_BASE_LOCAL ((unsigned long)0x10000000) // 32 Kb
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19 #define SRAM_BASE_AHB ((unsigned long)0x20000000) // 32 Kb
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21 /* System Control Space memory map */
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23 #define SCS_BASE ((unsigned long)0xE000E000)
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26 #define SysTick_BASE (SCS_BASE + 0x0010)
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27 #define NVIC_BASE (SCS_BASE + 0x0100)
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28 #define CM3_PERIPH_BASE_ADDR (SCS_BASE + 0x0D00)
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32 unsigned long CPUID;
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33 unsigned long IRQControlState;
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34 unsigned long ExceptionTableOffset;
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36 unsigned long SysCtrl;
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37 unsigned long ConfigCtrl;
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38 unsigned long SystemPriority[3];
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39 unsigned long SysHandlerCtrl;
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40 unsigned long ConfigFaultStatus;
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41 unsigned long HardFaultStatus;
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42 unsigned long DebugFaultStatus;
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43 unsigned long MemoryManageFaultAddr;
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44 unsigned long BusFaultAddr;
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47 /* Vector Table Base Address */
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48 #define NVIC_VectorTable_RAM SRAM_BASE_AHB
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49 #define NVIC_VectorTable_FLASH ((unsigned long)0x00000000)
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51 #define IS_NVIC_VECTORTBL(TABLE_BASE) ((TABLE_BASE == NVIC_VectorTable_RAM) || \
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52 (TABLE_BASE == NVIC_VectorTable_FLASH))
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54 /* Pin Connect Block */
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55 #define PINSEL_BASE_ADDR 0x4002C000
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56 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
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57 #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
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58 #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
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59 #define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C))
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60 #define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10))
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61 #define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
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62 #define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18))
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63 #define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C))
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64 #define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20))
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65 #define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24))
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66 #define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28))
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68 #define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40))
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69 #define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44))
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70 #define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48))
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71 #define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C))
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72 #define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50))
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73 #define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54))
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74 #define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58))
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75 #define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C))
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76 #define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60))
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77 #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
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79 /* Open drain mode control */
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80 #define PINMODE_OD0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x68))
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81 #define PINMODE_OD1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x6C))
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82 #define PINMODE_OD2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x70))
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83 #define PINMODE_OD3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x74))
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84 #define PINMODE_OD4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x78))
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86 #define PINSEL0_P00_GPIO ((unsigned int) 0x00000000)
87 #define PINSEL0_P00_TXD0 ((unsigned int) 0x00000001)
88 #define PINSEL0_P00_PWM1 ((unsigned int) 0x00000002)
89 #define PINSEL0_P00_RSVD3 ((unsigned int) 0x00000003)
90 #define PINSEL0_P00_MASK ((unsigned int) 0x00000003)
92 #define PINSEL0_P01_GPIO ((unsigned int) 0x00000000)
93 #define PINSEL0_P01_RXD0 ((unsigned int) 0x00000004)
94 #define PINSEL0_P01_PWM3 ((unsigned int) 0x00000008)
95 #define PINSEL0_P01_EINT0 ((unsigned int) 0x0000000C)
96 #define PINSEL0_P01_MASK ((unsigned int) 0x0000000C)
98 #define PINSEL0_P02_GPIO ((unsigned int) 0x00000000)
99 #define PINSEL0_P02_SCL0 ((unsigned int) 0x00000010)
100 #define PINSEL0_P02_CAP00 ((unsigned int) 0x00000020)
101 #define PINSEL0_P02_RSVD3 ((unsigned int) 0x00000030)
102 #define PINSEL0_P02_MASK ((unsigned int) 0x00000030)
104 #define PINSEL0_P03_GPIO ((unsigned int) 0x00000000)
105 #define PINSEL0_P03_SDA0 ((unsigned int) 0x00000040)
106 #define PINSEL0_P03_MAT00 ((unsigned int) 0x00000080)
107 #define PINSEL0_P03_EINT1 ((unsigned int) 0x000000C0)
108 #define PINSEL0_P03_MASK ((unsigned int) 0x000000C0)
110 #define PINSEL0_P04_GPIO ((unsigned int) 0x00000000)
111 #define PINSEL0_P04_SCK0 ((unsigned int) 0x00000100)
112 #define PINSEL0_P04_CAP01 ((unsigned int) 0x00000200)
113 #define PINSEL0_P04_RSVD3 ((unsigned int) 0x00000300)
114 #define PINSEL0_P04_MASK ((unsigned int) 0x00000300)
116 #define PINSEL0_P05_GPIO ((unsigned int) 0x00000000)
117 #define PINSEL0_P05_MISO0 ((unsigned int) 0x00000400)
118 #define PINSEL0_P05_MAT01 ((unsigned int) 0x00000800)
119 #define PINSEL0_P05_AD06 ((unsigned int) 0x00000C00)
120 #define PINSEL0_P05_MASK ((unsigned int) 0x00000C00)
122 #define PINSEL0_P06_GPIO ((unsigned int) 0x00000000)
123 #define PINSEL0_P06_MOSI0 ((unsigned int) 0x00001000)
124 #define PINSEL0_P06_CAP02 ((unsigned int) 0x00002000)
125 #define PINSEL0_P06_AD10 ((unsigned int) 0x00003000)
126 #define PINSEL0_P06_MASK ((unsigned int) 0x00003000)
128 #define PINSEL0_P07_GPIO ((unsigned int) 0x00000000)
129 #define PINSEL0_P07_SSEL0 ((unsigned int) 0x00004000)
130 #define PINSEL0_P07_PWM2 ((unsigned int) 0x00008000)
131 #define PINSEL0_P07_EINT2 ((unsigned int) 0x0000C000)
132 #define PINSEL0_P07_MASK ((unsigned int) 0x0000C000)
134 #define PINSEL0_P08_GPIO ((unsigned int) 0x00000000)
135 #define PINSEL0_P08_TXD1 ((unsigned int) 0x00010000)
136 #define PINSEL0_P08_PWM4 ((unsigned int) 0x00020000)
137 #define PINSEL0_P08_AD11 ((unsigned int) 0x00030000)
138 #define PINSEL0_P08_MASK ((unsigned int) 0x00030000)
140 #define PINSEL0_P09_GPIO ((unsigned int) 0x00000000)
141 #define PINSEL0_P09_RXD1 ((unsigned int) 0x00040000)
142 #define PINSEL0_P09_PWM6 ((unsigned int) 0x00080000)
143 #define PINSEL0_P09_EINT3 ((unsigned int) 0x000C0000)
144 #define PINSEL0_P09_MASK ((unsigned int) 0x000C0000)
146 #define PINSEL0_P010_GPIO ((unsigned int) 0x00000000)
147 #define PINSEL0_P010_RTS1 ((unsigned int) 0x00100000)
148 #define PINSEL0_P010_CAP10 ((unsigned int) 0x00200000)
149 #define PINSEL0_P010_AD12 ((unsigned int) 0x00300000)
150 #define PINSEL0_P010_MASK ((unsigned int) 0x00300000)
152 #define PINSEL0_P011_GPIO ((unsigned int) 0x00000000)
153 #define PINSEL0_P011_CTS1 ((unsigned int) 0x00400000)
154 #define PINSEL0_P011_CAP11 ((unsigned int) 0x00800000)
155 #define PINSEL0_P011_SCL1 ((unsigned int) 0x00C00000)
156 #define PINSEL0_P011_MASK ((unsigned int) 0x00C00000)
158 #define PINSEL0_P012_GPIO ((unsigned int) 0x00000000)
159 #define PINSEL0_P012_DSR1 ((unsigned int) 0x01000000)
160 #define PINSEL0_P012_MAT10 ((unsigned int) 0x02000000)
161 #define PINSEL0_P012_AD13 ((unsigned int) 0x03000000)
162 #define PINSEL0_P012_MASK ((unsigned int) 0x03000000)
164 #define PINSEL0_P013_GPIO ((unsigned int) 0x00000000)
165 #define PINSEL0_P013_DTR1 ((unsigned int) 0x04000000)
166 #define PINSEL0_P013_MAT11 ((unsigned int) 0x08000000)
167 #define PINSEL0_P013_AD14 ((unsigned int) 0x0C000000)
168 #define PINSEL0_P013_MASK ((unsigned int) 0x0C000000)
170 #define PINSEL0_P014_GPIO ((unsigned int) 0x00000000)
171 #define PINSEL0_P014_DCD1 ((unsigned int) 0x10000000)
172 #define PINSEL0_P014_EINT1 ((unsigned int) 0x20000000)
173 #define PINSEL0_P014_SDA1 ((unsigned int) 0x30000000)
174 #define PINSEL0_P014_MASK ((unsigned int) 0x30000000)
176 #define PINSEL0_P015_GPIO ((unsigned int) 0x00000000)
177 #define PINSEL0_P015_RI1 ((unsigned int) 0x40000000)
178 #define PINSEL0_P015_EINT2 ((unsigned int) 0x80000000)
179 #define PINSEL0_P015_AD15 ((unsigned int) 0xC0000000)
180 #define PINSEL0_P015_MASK ((unsigned int) 0xC0000000)
182 #define PINSEL1_P016_GPIO ((unsigned int) 0x00000000)
183 #define PINSEL1_P016_EINT0 ((unsigned int) 0x00000001)
184 #define PINSEL1_P016_MAT02 ((unsigned int) 0x00000002)
185 #define PINSEL1_P016_CAP02 ((unsigned int) 0x00000003)
186 #define PINSEL1_P016_MASK ((unsigned int) 0x00000003)
188 #define PINSEL1_P017_GPIO ((unsigned int) 0x00000000)
189 #define PINSEL1_P017_CAP12 ((unsigned int) 0x00000004)
190 #define PINSEL1_P017_SCK1 ((unsigned int) 0x00000008)
191 #define PINSEL1_P017_MAT12 ((unsigned int) 0x0000000c)
192 #define PINSEL1_P017_MASK ((unsigned int) 0x0000000c)
194 #define PINSEL1_P018_GPIO ((unsigned int) 0x00000000)
195 #define PINSEL1_P018_CAP13 ((unsigned int) 0x00000010)
196 #define PINSEL1_P018_MISO1 ((unsigned int) 0x00000020)
197 #define PINSEL1_P018_MAT13 ((unsigned int) 0x00000030)
198 #define PINSEL1_P018_MASK ((unsigned int) 0x00000030)
200 #define PINSEL1_P019_GPIO ((unsigned int) 0x00000000)
201 #define PINSEL1_P019_MAT12 ((unsigned int) 0x00000040)
202 #define PINSEL1_P019_MOSI1 ((unsigned int) 0x00000080)
203 #define PINSEL1_P019_CAP12 ((unsigned int) 0x000000c0)
205 #define PINSEL1_P020_GPIO ((unsigned int) 0x00000000)
206 #define PINSEL1_P020_MAT13 ((unsigned int) 0x00000100)
207 #define PINSEL1_P020_SSEL1 ((unsigned int) 0x00000200)
208 #define PINSEL1_P020_EINT3 ((unsigned int) 0x00000300)
209 #define PINSEL1_P020_MASK ((unsigned int) 0x00000300)
211 #define PINSEL1_P021_GPIO ((unsigned int) 0x00000000)
212 #define PINSEL1_P021_PWM5 ((unsigned int) 0x00000400)
213 #define PINSEL1_P021_AD16 ((unsigned int) 0x00000800)
214 #define PINSEL1_P021_CAP13 ((unsigned int) 0x00000c00)
215 #define PINSEL1_P021_MASK ((unsigned int) 0x00000c00)
217 #define PINSEL1_P022_GPIO ((unsigned int) 0x00000000)
218 #define PINSEL1_P022_AD17 ((unsigned int) 0x00001000)
219 #define PINSEL1_P022_CAP00 ((unsigned int) 0x00002000)
220 #define PINSEL1_P022_MAT00 ((unsigned int) 0x00003000)
221 #define PINSEL1_P022_MASK ((unsigned int) 0x00003000)
223 #define PINSEL1_P023_GPIO ((unsigned int) 0x00000000)
224 #define PINSEL1_P023_VBUS ((unsigned int) 0x00004000)
225 #define PINSEL1_P023_RSVD2 ((unsigned int) 0x00008000)
226 #define PINSEL1_P023_RSVD3 ((unsigned int) 0x0000c000)
227 #define PINSEL1_P023_MASK ((unsigned int) 0x0000c000)
229 #define PINSEL1_P024_RSVD0 ((unsigned int) 0x00000000)
230 #define PINSEL1_P024_RSVD1 ((unsigned int) 0x00010000)
231 #define PINSEL1_P024_RSVD2 ((unsigned int) 0x00020000)
232 #define PINSEL1_P024_RSVD3 ((unsigned int) 0x00030000)
233 #define PINSEL1_P024_MASK ((unsigned int) 0x00030000)
235 #define PINSEL1_P025_GPIO ((unsigned int) 0x00000000)
236 #define PINSEL1_P025_AD04 ((unsigned int) 0x00040000)
237 #define PINSEL1_P025_AOUT ((unsigned int) 0x00080000)
238 #define PINSEL1_P025_RSVD3 ((unsigned int) 0x000c0000)
239 #define PINSEL1_P025_MASK ((unsigned int) 0x000c0000)
241 #define PINSEL1_P026_RSVD0 ((unsigned int) 0x00000000)
242 #define PINSEL1_P026_RSVD1 ((unsigned int) 0x00100000)
243 #define PINSEL1_P026_RSVD2 ((unsigned int) 0x00200000)
244 #define PINSEL1_P026_RSVD3 ((unsigned int) 0x00300000)
245 #define PINSEL1_P026_MASK ((unsigned int) 0x00300000)
247 #define PINSEL1_P027_RSVD0 ((unsigned int) 0x00000000)
248 #define PINSEL1_P027_RSVD1 ((unsigned int) 0x00400000)
249 #define PINSEL1_P027_RSVD2 ((unsigned int) 0x00800000)
250 #define PINSEL1_P027_RSVD3 ((unsigned int) 0x00c00000)
251 #define PINSEL1_P027_MASK ((unsigned int) 0x00c00000)
253 #define PINSEL1_P028_GPIO ((unsigned int) 0x00000000)
254 #define PINSEL1_P028_AD01 ((unsigned int) 0x01000000)
255 #define PINSEL1_P028_CAP02 ((unsigned int) 0x02000000)
256 #define PINSEL1_P028_MAT02 ((unsigned int) 0x03000000)
257 #define PINSEL1_P028_MASK ((unsigned int) 0x03000000)
259 #define PINSEL1_P029_GPIO ((unsigned int) 0x00000000)
260 #define PINSEL1_P029_AD02 ((unsigned int) 0x04000000)
261 #define PINSEL1_P029_CAP03 ((unsigned int) 0x08000000)
262 #define PINSEL1_P029_MAT03 ((unsigned int) 0x0c000000)
263 #define PINSEL1_P029_MASK ((unsigned int) 0x0c000000)
265 #define PINSEL1_P030_GPIO ((unsigned int) 0x00000000)
266 #define PINSEL1_P030_AD03 ((unsigned int) 0x10000000)
267 #define PINSEL1_P030_EINT3 ((unsigned int) 0x20000000)
268 #define PINSEL1_P030_CAP00 ((unsigned int) 0x30000000)
269 #define PINSEL1_P030_MASK ((unsigned int) 0x30000000)
271 #define PINSEL1_P031_GPIO ((unsigned int) 0x00000000)
272 #define PINSEL1_P031_UPLED ((unsigned int) 0x40000000)
273 #define PINSEL1_P031_CONNECT ((unsigned int) 0x80000000)
274 #define PINSEL1_P031_RSVD3 ((unsigned int) 0xc0000000)
275 #define PINSEL1_P031_MASK ((unsigned int) 0xc0000000)
277 #define PINSEL2_P13626_GPIO ((unsigned int) 0x00000000)
278 #define PINSEL2_P13626_DEBUG ((unsigned int) 0x00000004)
279 #define PINSEL2_P13626_MASK ((unsigned int) 0x00000004)
281 #define PINSEL2_P12516_GPIO ((unsigned int) 0x00000000)
282 #define PINSEL2_P12516_TRACE ((unsigned int) 0x00000008)
283 #define PINSEL2_P12516_MASK ((unsigned int) 0x00000008)
285 /* General Purpose Input/Output (GPIO) */
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286 /* Fast I/O setup */
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288 #define FIO_BASE_ADDR 0x50014000
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290 #define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
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291 #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
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292 #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
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293 #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
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294 #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
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296 #ifdef LPC1766_UM_DEFS
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297 /* Fast GPIO Register Access */
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298 #define FIO0SET0 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
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299 #define FIO0SET1 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x39))
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300 #define FIO0SET2 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3A))
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301 #define FIO0SET3 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3B))
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302 #define FIO0SETL (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
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303 #define FIO0SETU (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3A))
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306 #define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
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307 #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
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308 #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
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309 #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
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310 #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
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312 #ifdef LPC1766_UM_DEFS
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313 /* Fast GPIO Register Access */
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314 #define FIO1SET0 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
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315 #define FIO1SET1 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x79))
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316 #define FIO1SET2 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7A))
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317 #define FIO1SET3 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7B))
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318 #define FIO1SETL (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
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319 #define FIO1SETU (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7A))
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322 #define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40))
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323 #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
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324 #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
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325 #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
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326 #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
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328 #ifdef LPC1766_UM_DEFS
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329 /* Fast GPIO Register Access */
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330 #define FIO2SET0 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xB8))
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331 #define FIO2SET1 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xB9))
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332 #define FIO2SET2 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xBA))
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333 #define FIO2SET3 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xBB))
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334 #define FIO2SETL (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xB8))
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335 #define FIO2SETU (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xBA))
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338 #define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60))
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339 #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
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340 #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
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341 #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
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342 #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
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344 #ifdef LPC1766_UM_DEFS
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345 /* Fast GPIO Register Access */
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346 #define FIO3SET0 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xF8))
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347 #define FIO3SET1 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xF9))
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348 #define FIO3SET2 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xFA))
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349 #define FIO3SET3 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xFB))
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350 #define FIO3SETL (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xF8))
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351 #define FIO3SETU (*(volatile unsigned long *)(FIO_BASE_ADDR + 0xFA))
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354 #define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80))
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355 #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
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356 #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
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357 #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
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358 #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
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360 #ifdef LPC1766_UM_DEFS
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361 /* Fast GPIO Register Access */
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362 #define FIO4SET0 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x138))
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363 #define FIO4SET1 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x139))
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364 #define FIO4SET2 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x13A))
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365 #define FIO0SET3 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3B))
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366 #define FIO4SET3 (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x13B))
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367 #define FIO4SETL (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x138))
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368 #define FIO4SETU (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x13A))
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371 /* General Purpose Input/Output (GPIO) */
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372 #define GPIO_BASE_ADDR 0x40028000
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373 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
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374 #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
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375 #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
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376 #define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
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377 #define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
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378 #define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
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379 #define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
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380 #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
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382 #define GPIO_IO_P0 ((unsigned int) 0x00000001)
383 #define GPIO_IO_P1 ((unsigned int) 0x00000002)
384 #define GPIO_IO_P2 ((unsigned int) 0x00000004)
385 #define GPIO_IO_P3 ((unsigned int) 0x00000008)
386 #define GPIO_IO_P4 ((unsigned int) 0x00000010)
387 #define GPIO_IO_P5 ((unsigned int) 0x00000020)
388 #define GPIO_IO_P6 ((unsigned int) 0x00000040)
389 #define GPIO_IO_P7 ((unsigned int) 0x00000080)
390 #define GPIO_IO_P8 ((unsigned int) 0x00000100)
391 #define GPIO_IO_P9 ((unsigned int) 0x00000200)
392 #define GPIO_IO_P10 ((unsigned int) 0x00000400)
393 #define GPIO_IO_P11 ((unsigned int) 0x00000800)
394 #define GPIO_IO_P12 ((unsigned int) 0x00001000)
395 #define GPIO_IO_P13 ((unsigned int) 0x00002000)
396 #define GPIO_IO_P14 ((unsigned int) 0x00004000)
397 #define GPIO_IO_P15 ((unsigned int) 0x00008000)
398 #define GPIO_IO_P16 ((unsigned int) 0x00010000)
399 #define GPIO_IO_P17 ((unsigned int) 0x00020000)
400 #define GPIO_IO_P18 ((unsigned int) 0x00040000)
401 #define GPIO_IO_P19 ((unsigned int) 0x00080000)
402 #define GPIO_IO_P20 ((unsigned int) 0x00100000)
403 #define GPIO_IO_P21 ((unsigned int) 0x00200000)
404 #define GPIO_IO_P22 ((unsigned int) 0x00400000)
405 #define GPIO_IO_P23 ((unsigned int) 0x00800000)
406 #define GPIO_IO_P24 ((unsigned int) 0x01000000)
407 #define GPIO_IO_P25 ((unsigned int) 0x02000000)
408 #define GPIO_IO_P26 ((unsigned int) 0x04000000)
409 #define GPIO_IO_P27 ((unsigned int) 0x08000000)
410 #define GPIO_IO_P28 ((unsigned int) 0x10000000)
411 #define GPIO_IO_P29 ((unsigned int) 0x20000000)
412 #define GPIO_IO_P30 ((unsigned int) 0x40000000)
413 #define GPIO_IO_P31 ((unsigned int) 0x80000000)
414 #define GPIO_IO_JTAG ((unsigned int) 0x003E0000)
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416 /* GPIO Interrupt Registers */
\r
417 #define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
\r
418 #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
\r
419 #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
\r
420 #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
\r
421 #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
\r
423 #define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0))
\r
424 #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
\r
425 #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
\r
426 #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
\r
427 #define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC))
\r
429 #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
\r
431 #define PARTCFG_BASE_ADDR 0x3FFF8000
\r
432 #define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00))
\r
434 /* System Control Block(SCB) modules include Memory Accelerator Module,
\r
435 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
\r
436 Reset, and Code Security/Debugging */
\r
437 #define SCB_BASE_ADDR 0x400FC000
\r
439 /* Memory Accelerator Module */
\r
441 /* Phase Locked Loop (PLL0) */
\r
442 #define PLL0CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
\r
443 #define PLL0CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
\r
444 #define PLL0STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
\r
445 #define PLL0FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
\r
447 /* Phase Locked Loop (PLL1) */
\r
448 #define PLL1CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))
\r
449 #define PLL1CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))
\r
450 #define PLL1STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))
\r
451 #define PLL1FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))
\r
453 #define PLLCON_PLLE 0x00000001
454 #define PLLCON_PLLC 0x00000002
455 #define PLLCON_MASK 0x00000003
\r
457 #define PLLCFG_MUL1 0x00000000
458 #define PLLCFG_MUL2 0x00000001
459 #define PLLCFG_MUL3 0x00000002
460 #define PLLCFG_MUL4 0x00000003
461 #define PLLCFG_MUL5 0x00000004
462 #define PLLCFG_MUL6 0x00000005
463 #define PLLCFG_MUL7 0x00000006
464 #define PLLCFG_MUL8 0x00000007
465 #define PLLCFG_MUL9 0x00000008
466 #define PLLCFG_MUL10 0x00000009
467 #define PLLCFG_MUL11 0x0000000A
468 #define PLLCFG_MUL12 0x0000000B
469 #define PLLCFG_MUL13 0x0000000C
470 #define PLLCFG_MUL14 0x0000000D
471 #define PLLCFG_MUL15 0x0000000E
472 #define PLLCFG_MUL16 0x0000000F
473 #define PLLCFG_MUL17 0x00000010
474 #define PLLCFG_MUL18 0x00000011
475 #define PLLCFG_MUL19 0x00000012
476 #define PLLCFG_MUL20 0x00000013
477 #define PLLCFG_MUL21 0x00000014
478 #define PLLCFG_MUL22 0x00000015
479 #define PLLCFG_MUL23 0x00000016
480 #define PLLCFG_MUL24 0x00000017
481 #define PLLCFG_MUL25 0x00000018
482 #define PLLCFG_MUL26 0x00000019
483 #define PLLCFG_MUL27 0x0000001A
484 #define PLLCFG_MUL28 0x0000001B
485 #define PLLCFG_MUL29 0x0000001C
486 #define PLLCFG_MUL30 0x0000001D
487 #define PLLCFG_MUL31 0x0000001E
488 #define PLLCFG_MUL32 0x0000001F
\r
489 #define PLLCFG_MUL33 0x00000020
\r
490 #define PLLCFG_MUL34 0x00000021
\r
491 #define PLLCFG_MUL35 0x00000022
\r
492 #define PLLCFG_MUL36 0x00000023
\r
494 #define PLLCFG_DIV1 0x00000000
495 #define PLLCFG_DIV2 0x00010000
\r
496 #define PLLCFG_DIV3 0x00020000
497 #define PLLCFG_DIV4 0x00030000
\r
498 #define PLLCFG_DIV5 0x00040000
\r
499 #define PLLCFG_DIV6 0x00050000
\r
500 #define PLLCFG_DIV7 0x00060000
501 #define PLLCFG_DIV8 0x00070000
\r
502 #define PLLCFG_DIV9 0x00080000
\r
503 #define PLLCFG_DIV10 0x00090000
504 #define PLLCFG_MASK 0x00FF7FFF
\r
506 #define PLLSTAT_MSEL_MASK 0x00007FFF
\r
507 #define PLLSTAT_NSEL_MASK 0x00FF0000
\r
509 #define PLLSTAT_PLLE (1 << 24)
510 #define PLLSTAT_PLLC (1 << 25)
511 #define PLLSTAT_PLOCK (1 << 26)
\r
513 #define PLLFEED_FEED1 0x000000AA
514 #define PLLFEED_FEED2 0x00000055
\r
516 /* Power Control */
\r
517 #define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
\r
518 #define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
\r
520 #define PCON_IDL 0x00000001
521 #define PCON_PD 0x00000002
522 #define PCON_PDBOD 0x00000004
523 #define PCON_BODPDM 0x00000008
524 #define PCON_BOGD 0x00000010
525 #define PCON_BORD 0x00000020
526 #define PCON_MASK 0x0000003F
528 #define PCONP_PCTIM0 0x00000002
529 #define PCONP_PCTIM1 0x00000004
530 #define PCONP_PCUART0 0x00000008
531 #define PCONP_PCUART1 0x00000010
532 #define PCONP_PCPWM1 0x00000040
533 #define PCONP_PCI2C0 0x00000080
534 #define PCONP_PCSPI 0x00000100
535 #define PCONP_PCRTC 0x00000200
536 #define PCONP_PCSSP1 0x00000400
\r
537 #define PCONP_PCAD 0x00001000
\r
538 #define PCONP_PCCAN1 0x00002000
\r
539 #define PCONP_PCCAN2 0x00004000
\r
540 #define PCONP_PCGPIO 0x00008000
\r
541 #define PCONP_PCRIT 0x00010000
\r
542 #define PCONP_PCMCPWM 0x00020000
\r
543 #define PCONP_PCQEI 0x00040000
544 #define PCONP_PCI2C1 0x00080000
\r
545 #define PCONP_PCSSP0 0x00200000
\r
546 #define PCONP_PCTIM2 0x00400000
\r
547 #define PCONP_PCTIM3 0x00800000
\r
548 #define PCONP_PCUART2 0x01000000
\r
549 #define PCONP_PCUART3 0x02000000
\r
550 #define PCONP_PCI2C2 0x04000000
\r
551 #define PCONP_PCI2S 0x08000000
\r
552 #define PCONP_PCGPDMA 0x20000000
\r
553 #define PCONP_PCENET 0x40000000
\r
554 #define PCONP_PCUSB 0x80000000
\r
555 #define PCONP_MASK 0x801817BE
557 // Each peripheral clock source uses 2 bits
558 #define PCLK_25 0x0 // divide by 4
559 #define PCLK_100 0x1 // divide by 1
560 #define PCLK_50 0x2 // divide by 2
561 #define PCLK_RSVD 0x3 // divide by 8*
562 #define PCLK_MASK 0x3
564 #define EXTINT_EINT0 0x00000001
565 #define EXTINT_EINT1 0x00000002
566 #define EXTINT_EINT2 0x00000004
567 #define EXTINT_EINT3 0x00000008
568 #define EXTINT_MASK 0x0000000F
570 #define INTWAKE_EINT0 0x00000001
571 #define INTWAKE_EINT1 0x00000002
572 #define INTWAKE_EINT2 0x00000004
573 #define INTWAKE_EINT3 0x00000008
574 #define INTWAKE_USB 0x00000020
575 #define INTWAKE_BOD 0x00004000
576 #define INTWAKE_RTC 0x00008000
577 #define INTWAKE_MASK 0x0000C02F
579 #define EXTMODE_EINT0 0x00000001
580 #define EXTMODE_EINT1 0x00000002
581 #define EXTMODE_EINT2 0x00000004
582 #define EXTMODE_EINT3 0x00000008
583 #define EXTMODE_MASK 0x0000000F
585 #define EXTPOLAR_EINT0 0x00000001
586 #define EXTPOLAR_EINT1 0x00000002
587 #define EXTPOLAR_EINT2 0x00000004
588 #define EXTPOLAR_EINT3 0x00000008
589 #define EXTPOLAR_MASK 0x0000000F
591 #define RSIR_POR 0x00000001
592 #define RSIR_EXTR 0x00000002
593 #define RSIR_WDTR 0x00000004
594 #define RSIR_BODR 0x00000008
595 #define RSIR_MASK 0x0000000F
597 #define SCS_GPIO0M 0x00000001
598 #define SCS_GPIO1M 0x00000002
599 #define SCS_MASK 0x00000003
\r
601 /* Clock Divider */
\r
602 // #define APBDIV (*(volatile unsigned long *)(BASE_ADDR + 0x100))
\r
603 #define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))
\r
604 #define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))
\r
605 #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
\r
606 #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
\r
607 #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
\r
609 /* External Interrupts */
\r
610 #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
\r
611 #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
\r
612 #define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
\r
613 #define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
\r
615 /* Reset, reset source identification */
\r
616 #define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
\r
618 /* RSID, code security protection */
\r
619 #define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184))
\r
621 /* AHB configuration */
\r
622 #define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188))
\r
623 #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
\r
625 /* System Controls and Status */
\r
626 #define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
\r
628 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
\r
629 are for LPC24xx only. */
\r
630 #define STATIC_MEM0_BASE 0x80000000
\r
631 #define STATIC_MEM1_BASE 0x81000000
\r
632 #define STATIC_MEM2_BASE 0x82000000
\r
633 #define STATIC_MEM3_BASE 0x83000000
\r
635 #define DYNAMIC_MEM0_BASE 0xA0000000
\r
636 #define DYNAMIC_MEM1_BASE 0xB0000000
\r
637 #define DYNAMIC_MEM2_BASE 0xC0000000
\r
638 #define DYNAMIC_MEM3_BASE 0xD0000000
\r
640 /* External Memory Controller (EMC) */
\r
641 #define EMC_BASE_ADDR 0xFFE08000
\r
642 #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
\r
643 #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
\r
644 #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
\r
646 /* Dynamic RAM access registers */
\r
647 #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020))
\r
648 #define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024))
\r
649 #define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028))
\r
650 #define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030))
\r
651 #define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034))
\r
652 #define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038))
\r
653 #define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C))
\r
654 #define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040))
\r
655 #define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044))
\r
656 #define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048))
\r
657 #define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C))
\r
658 #define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050))
\r
659 #define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054))
\r
660 #define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058))
\r
662 #define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100))
\r
663 #define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104))
\r
664 #define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x120))
\r
665 #define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x124))
\r
666 #define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140))
\r
667 #define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144))
\r
668 #define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160))
\r
669 #define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164))
\r
671 /* static RAM access registers */
\r
672 #define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200))
\r
673 #define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204))
\r
674 #define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208))
\r
675 #define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C))
\r
676 #define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210))
\r
677 #define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214))
\r
678 #define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218))
\r
680 #define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220))
\r
681 #define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224))
\r
682 #define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228))
\r
683 #define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C))
\r
684 #define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230))
\r
685 #define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234))
\r
686 #define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238))
\r
688 #define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240))
\r
689 #define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244))
\r
690 #define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248))
\r
691 #define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C))
\r
692 #define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250))
\r
693 #define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254))
\r
694 #define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258))
\r
696 #define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260))
\r
697 #define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264))
\r
698 #define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268))
\r
699 #define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C))
\r
700 #define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270))
\r
701 #define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274))
\r
702 #define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278))
\r
704 #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
\r
707 #define TMR0_BASE_ADDR 0x40004000
\r
708 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
\r
709 #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
\r
710 #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
\r
711 #define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
\r
712 #define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
\r
713 #define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
\r
714 #define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
\r
715 #define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
\r
716 #define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
\r
717 #define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
\r
718 #define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
\r
719 #define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
\r
720 #define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
\r
721 #define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
\r
722 #define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
\r
723 #define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
\r
724 #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
\r
727 #define TMR1_BASE_ADDR 0x40008000
\r
728 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
\r
729 #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
\r
730 #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
\r
731 #define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
\r
732 #define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
\r
733 #define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
\r
734 #define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
\r
735 #define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
\r
736 #define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
\r
737 #define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
\r
738 #define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
\r
739 #define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
\r
740 #define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
\r
741 #define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
\r
742 #define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
\r
743 #define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
\r
744 #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
\r
747 #define TMR2_BASE_ADDR 0x40090000
\r
748 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
\r
749 #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
\r
750 #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
\r
751 #define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))
\r
752 #define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))
\r
753 #define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))
\r
754 #define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))
\r
755 #define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))
\r
756 #define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))
\r
757 #define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))
\r
758 #define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))
\r
759 #define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))
\r
760 #define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))
\r
761 #define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))
\r
762 #define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))
\r
763 #define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))
\r
764 #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
\r
767 #define TMR3_BASE_ADDR 0x40094000
\r
768 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
\r
769 #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
\r
770 #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
\r
771 #define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))
\r
772 #define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))
\r
773 #define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))
\r
774 #define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))
\r
775 #define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))
\r
776 #define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))
\r
777 #define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))
\r
778 #define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))
\r
779 #define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))
\r
780 #define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))
\r
781 #define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))
\r
782 #define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))
\r
783 #define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))
\r
784 #define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))
\r
786 #define T_IR_MR0 0x00000001
787 #define T_IR_MR1 0x00000002
788 #define T_IR_MR2 0x00000004
789 #define T_IR_MR3 0x00000008
790 #define T_IR_CR0 0x00000010
791 #define T_IR_CR1 0x00000020
792 #define T_IR_CR2 0x00000040
793 #define T_IR_CR3 0x00000080
794 #define T_IR_MASK 0x000000FF
796 #define T_TCR_CE 0x00000001
797 #define T_TCR_CR 0x00000002
799 #define T_CTCR_MODE_PCLK 0x00000000
800 #define T_CTCR_MODE_CAPRISE 0x00000001
801 #define T_CTCR_MODE_CAPFALL 0x00000002
802 #define T_CTCR_MODE_CAPBOTH 0x00000003
803 #define T_CTCR_MODE_MASK 0x00000003
804 #define T_CTCR_CIS_CAPN0 0x00000000
805 #define T_CTCR_CIS_CAPN1 0x00000004
806 #define T_CTCR_CIS_CAPN2 0x00000008
807 #define T_CTCR_CIS_CAPN3 0x0000000C
808 #define T_CTCR_CIS_MASK 0x0000000C
810 #define T_MCR_MR0I 0x00000001
811 #define T_MCR_MR0R 0x00000002
812 #define T_MCR_MR0S 0x00000004
813 #define T_MCR_MR1I 0x00000008
814 #define T_MCR_MR1R 0x00000010
815 #define T_MCR_MR1S 0x00000020
816 #define T_MCR_MR2I 0x00000040
817 #define T_MCR_MR2R 0x00000080
818 #define T_MCR_MR2S 0x00000100
819 #define T_MCR_MR3I 0x00000200
820 #define T_MCR_MR3R 0x00000400
821 #define T_MCR_MR3S 0x00000800
823 #define T_CCR_CAP0RE 0x00000001
824 #define T_CCR_CAP0FE 0x00000002
825 #define T_CCR_CAP0I 0x00000004
826 #define T_CCR_CAP1RE 0x00000008
827 #define T_CCR_CAP1FE 0x00000010
828 #define T_CCR_CAP1I 0x00000020
829 #define T_CCR_CAP2RE 0x00000040
830 #define T_CCR_CAP2FE 0x00000080
831 #define T_CCR_CAP2I 0x00000100
832 #define T_CCR_CAP3RE 0x00000200
833 #define T_CCR_CAP3FE 0x00000400
834 #define T_CCR_CAP3I 0x00000800
836 #define T_EMR_EM0 0x00000001
837 #define T_EMR_EM1 0x00000002
838 #define T_EMR_EM2 0x00000004
839 #define T_EMR_EM3 0x00000008
840 #define T_EMR_EMC0_NONE 0x00000000
841 #define T_EMR_EMC0_CLEAR 0x00000010
842 #define T_EMR_EMC0_SET 0x00000020
843 #define T_EMR_EMC0_TOGGLE 0x00000030
844 #define T_EMR_EMC0_MASK 0x00000030
845 #define T_EMR_EMC1_NONE 0x00000000
846 #define T_EMR_EMC1_CLEAR 0x00000040
847 #define T_EMR_EMC1_SET 0x00000080
848 #define T_EMR_EMC1_TOGGLE 0x000000C0
849 #define T_EMR_EMC1_MASK 0x000000C0
850 #define T_EMR_EMC2_NONE 0x00000000
851 #define T_EMR_EMC2_CLEAR 0x00000100
852 #define T_EMR_EMC2_SET 0x00000200
853 #define T_EMR_EMC2_TOGGLE 0x00000300
854 #define T_EMR_EMC2_MASK 0x00000300
855 #define T_EMR_EMC3_NONE 0x00000000
856 #define T_EMR_EMC3_CLEAR 0x00000400
857 #define T_EMR_EMC3_SET 0x00000800
858 #define T_EMR_EMC3_TOGGLE 0x00000C00
859 #define T_EMR_EMC3_MASK 0x00000C00
861 /* Pulse Width Modulator (PWM1) */
\r
862 #define PWM1_BASE_ADDR 0x40018000
\r
863 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
\r
864 #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
\r
865 #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
\r
866 #define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))
\r
867 #define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))
\r
868 #define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))
\r
869 #define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))
\r
870 #define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))
\r
871 #define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))
\r
872 #define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))
\r
873 #define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))
\r
874 #define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))
\r
875 #define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))
\r
876 #define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))
\r
877 #define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))
\r
878 #define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C))
\r
879 #define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))
\r
880 #define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))
\r
881 #define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))
\r
882 #define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))
\r
883 #define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))
\r
884 #define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))
\r
886 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
\r
887 #define UART0_BASE_ADDR 0x4000C000
\r
888 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
\r
889 #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
\r
890 #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
\r
891 #define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
\r
892 #define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
\r
893 #define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
\r
894 #define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
\r
895 #define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
\r
896 #define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
\r
897 #define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
\r
898 #define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
\r
899 #define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24))
\r
900 #define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
\r
901 #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
\r
903 #define UART0_RBR U0RBR
904 #define UART0_THR U0THR
905 #define UART0_IER U0IER
906 #define UART0_IIR U0IIR
907 #define UART0_FCR U0FCR
908 #define UART0_LCR U0LCR
909 #define UART0_LSR U0LSR
910 #define UART0_SCR U0SCR
911 #define UART0_ACR U0ACR
912 #define UART0_FDR U0FDR
913 #define UART0_TER U0TER
914 #define UART0_DLL U0DLL
915 #define UART0_DLM U0DLM
\r
917 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
\r
918 #define UART1_BASE_ADDR 0x40010000
\r
919 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
\r
920 #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
\r
921 #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
\r
922 #define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
\r
923 #define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
\r
924 #define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
\r
925 #define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
\r
926 #define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
\r
927 #define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
\r
928 #define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
\r
929 #define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
\r
930 #define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
\r
931 #define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
\r
932 #define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
\r
933 #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
\r
935 #define UART1_RBR U1RBR
936 #define UART1_THR U1THR
937 #define UART1_IER U1IER
938 #define UART1_IIR U1IIR
939 #define UART1_FCR U1FCR
940 #define UART1_LCR U1LCR
941 #define UART1_LSR U1LSR
942 #define UART1_SCR U1SCR
943 #define UART1_ACR U1ACR
944 #define UART1_FDR U1FDR
945 #define UART1_TER U1TER
946 #define UART1_DLL U1DLL
947 #define UART1_DLM U1DLM
948 #define UART1_MCR U1MCR
949 #define UART1_MSR U1MSR
\r
951 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
\r
952 #define UART2_BASE_ADDR 0x40098000
\r
953 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
\r
954 #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
\r
955 #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
\r
956 #define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
\r
957 #define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))
\r
958 #define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
\r
959 #define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))
\r
960 #define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))
\r
961 #define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))
\r
962 #define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))
\r
963 #define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))
\r
964 #define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24))
\r
965 #define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))
\r
966 #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
\r
968 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
\r
969 #define UART3_BASE_ADDR 0x4009C000
\r
970 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
\r
971 #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
\r
972 #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
\r
973 #define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
\r
974 #define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))
\r
975 #define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
\r
976 #define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))
\r
977 #define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))
\r
978 #define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))
\r
979 #define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))
\r
980 #define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))
\r
981 #define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))
\r
982 #define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))
\r
983 #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
\r
985 #define UART_LCR_DLAB 0x00000080
986 #define UART_LCR_NOPAR 0x00000000
987 #define UART_LCR_1STOP 0x00000000
988 #define UART_LCR_8BITS 0x00000003
989 #define UART_IER_EI 0x00000003
990 #define UART_FCR_EN 0x00000001
991 #define UART_FCR_CLR 0x00000006
\r
993 /* I2C Interface 0 */
\r
994 #define I2C0_BASE_ADDR 0x4001C000
\r
995 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
\r
996 #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
\r
997 #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
\r
998 #define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
\r
999 #define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
\r
1000 #define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
\r
1001 #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
\r
1003 /* I2C Interface 1 */
\r
1004 #define I2C1_BASE_ADDR 0x4005C000
\r
1005 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
\r
1006 #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
\r
1007 #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
\r
1008 #define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
\r
1009 #define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
\r
1010 #define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
\r
1011 #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
\r
1013 /* I2C Interface 2 */
\r
1014 #define I2C2_BASE_ADDR 0x400A000
\r
1015 #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
\r
1016 #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
\r
1017 #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
\r
1018 #define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))
\r
1019 #define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))
\r
1020 #define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))
\r
1021 #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
\r
1023 /* SPI0 (Serial Peripheral Interface 0) */
\r
1024 #define SPI0_BASE_ADDR 0x40020000
\r
1025 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
\r
1026 #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
\r
1027 #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
\r
1028 #define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
\r
1029 #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
\r
1031 /* SSP0 Controller */
\r
1032 #define SSP0_BASE_ADDR 0x40088000
\r
1033 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
\r
1034 #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
\r
1035 #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
\r
1036 #define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))
\r
1037 #define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))
\r
1038 #define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))
\r
1039 #define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))
\r
1040 #define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))
\r
1041 #define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))
\r
1042 #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
\r
1044 /* SSP1 Controller */
\r
1045 #define SSP1_BASE_ADDR 0x40030000
\r
1046 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
\r
1047 #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
\r
1048 #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
\r
1049 #define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))
\r
1050 #define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))
\r
1051 #define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))
\r
1052 #define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))
\r
1053 #define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))
\r
1054 #define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))
\r
1055 #define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))
\r
1057 /* Real Time Clock */
\r
1058 #define RTC_BASE_ADDR 0x40024000
\r
1059 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
\r
1060 #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
\r
1061 #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
\r
1062 #define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
\r
1063 #define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
\r
1064 #define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
\r
1065 #define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
\r
1066 #define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
\r
1068 #define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
\r
1069 #define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
\r
1070 #define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
\r
1071 #define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
\r
1072 #define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
\r
1073 #define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
\r
1074 #define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
\r
1075 #define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
\r
1077 #define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))
\r
1078 #define RTC_GPREG0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x44))
\r
1079 #define RTC_GPREG1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x48))
\r
1080 #define RTC_GPREG2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x4C))
\r
1081 #define RTC_GPREG3 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x50))
\r
1082 #define RTC_GPREG4 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x54))
\r
1083 #define RTC_WAKEUPDIS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x58))
\r
1084 #define RTC_PWRCTRL (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x5C))
\r
1086 #define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
\r
1087 #define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
\r
1088 #define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
\r
1089 #define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
\r
1090 #define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
\r
1091 #define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
\r
1092 #define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
\r
1093 #define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
\r
1094 #define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
\r
1095 #define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
\r
1097 #define RTC_ILR_RTCCIF 0x00000001
1098 #define RTC_ILR_RTCALF 0x00000002
1099 #define RTC_ILR_MASK 0x00000003
1101 #define RTC_CCR_CLKEN 0x00000001
1102 #define RTC_CCR_CTCRST 0x00000002
1103 #define RTC_CCR_TEST 0x0000000c
1104 #define RTC_CCR_CLKSRC 0x00000010
1106 #define RTC_CIIR_IMSEC 0x00000001
1107 #define RTC_CIIR_IMMIN 0x00000002
1108 #define RTC_CIIR_IMHOUR 0x00000004
1109 #define RTC_CIIR_IMDOM 0x00000008
1110 #define RTC_CIIR_IMDOW 0x00000010
1111 #define RTC_CIIR_IMDOY 0x00000020
1112 #define RTC_CIIR_IMMON 0x00000040
1113 #define RTC_CIIR_IMYEAR 0x00000080
1114 #define RTC_CIIR_IMMASK 0x000000FF
1116 #define RTC_AMR_AMRSEC 0x00000001
1117 #define RTC_AMR_AMRMIN 0x00000002
1118 #define RTC_AMR_AMRHOUR 0x00000004
1119 #define RTC_AMR_AMRDOM 0x00000008
1120 #define RTC_AMR_AMRDOW 0x00000010
1121 #define RTC_AMR_AMRDOY 0x00000020
1122 #define RTC_AMR_AMRMON 0x00000040
1123 #define RTC_AMR_AMRYEAR 0x00000080
1124 #define RTC_AMR_AMRMASK 0x000000FF
1126 typedef struct __attribute__ ((packed))
1132 unsigned int counter : 14;
1133 unsigned int rsvd15_31 : 18;
1141 typedef struct __attribute__ ((packed))
1147 unsigned int seconds : 6;
1148 unsigned int rsvd7_6 : 2;
1149 unsigned int minutes : 6;
1150 unsigned int rsvd14_15 : 2;
1151 unsigned int hours : 5;
1152 unsigned int rsvd21_23 : 3;
1153 unsigned int dow : 3;
1154 unsigned int rsvd27_31 : 5;
1162 typedef struct __attribute__ ((packed))
1168 unsigned int dom : 5;
1169 unsigned int rsvd5_7 : 3;
1170 unsigned int month : 4;
1171 unsigned int rsvd12_15 : 4;
1172 unsigned int year : 12;
1173 unsigned int rsvd28_31 : 4;
1181 typedef struct __attribute__ ((packed))
1187 unsigned int doy : 12;
1188 unsigned int rsvd12_31 : 20;
1196 /* A/D Converter 0 (AD0) */
\r
1197 #define AD0_BASE_ADDR 0x40034000
\r
1198 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
\r
1199 #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
\r
1200 #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
\r
1201 #define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
\r
1202 #define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
\r
1203 #define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
\r
1204 #define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
\r
1205 #define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
\r
1206 #define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
\r
1207 #define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
\r
1208 #define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
\r
1209 #define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
\r
1211 /* D/A Converter */
\r
1212 #define DAC_BASE_ADDR 0x4008C000
\r
1213 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
\r
1216 #define WDG_BASE_ADDR 0x40000000
\r
1217 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
\r
1218 #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
\r
1219 #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
\r
1220 #define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
\r
1221 #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
\r
1223 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
\r
1224 #define CAN_ACCEPT_BASE_ADDR 0x4003C000
\r
1225 #define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
\r
1226 #define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
\r
1227 #define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
\r
1228 #define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
\r
1229 #define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
\r
1230 #define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
\r
1231 #define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
\r
1232 #define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
\r
1234 #define CAN_CENTRAL_BASE_ADDR 0xE0040000
\r
1235 #define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
\r
1236 #define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
\r
1237 #define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
\r
1239 #define CAN1_BASE_ADDR 0x40044000
\r
1240 #define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
\r
1241 #define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
\r
1242 #define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
\r
1243 #define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
\r
1244 #define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
\r
1245 #define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
\r
1246 #define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
\r
1247 #define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
\r
1248 #define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
\r
1249 #define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
\r
1250 #define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
\r
1251 #define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
\r
1253 #define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
\r
1254 #define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
\r
1255 #define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
\r
1256 #define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
\r
1257 #define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
\r
1258 #define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
\r
1259 #define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
\r
1260 #define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
\r
1261 #define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
\r
1262 #define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
\r
1263 #define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
\r
1264 #define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
\r
1266 #define CAN2_BASE_ADDR 0x40048000
\r
1267 #define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
\r
1268 #define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
\r
1269 #define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
\r
1270 #define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
\r
1271 #define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
\r
1272 #define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
\r
1273 #define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
\r
1274 #define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
\r
1275 #define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
\r
1276 #define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
\r
1277 #define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
\r
1278 #define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
\r
1280 #define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
\r
1281 #define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
\r
1282 #define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
\r
1283 #define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
\r
1284 #define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
\r
1285 #define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
\r
1286 #define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
\r
1287 #define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
\r
1288 #define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
\r
1289 #define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
\r
1290 #define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
\r
1291 #define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
\r
1293 /* I2S Interface Controller (I2S) */
\r
1294 #define I2S_BASE_ADDR 0x400A8000
\r
1295 #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
\r
1296 #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
\r
1297 #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
\r
1298 #define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))
\r
1299 #define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))
\r
1300 #define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))
\r
1301 #define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))
\r
1302 #define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))
\r
1303 #define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))
\r
1304 #define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))
\r
1306 /* General-purpose DMA Controller */
\r
1307 #define DMA_BASE_ADDR 0x50004000
\r
1308 #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
\r
1309 #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
\r
1310 #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
\r
1311 #define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))
\r
1312 #define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))
\r
1313 #define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))
\r
1314 #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))
\r
1315 #define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))
\r
1316 #define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))
\r
1317 #define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))
\r
1318 #define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))
\r
1319 #define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))
\r
1320 #define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))
\r
1321 #define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))
\r
1323 /* DMA channel 0 registers */
\r
1324 #define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))
\r
1325 #define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))
\r
1326 #define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))
\r
1327 #define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))
\r
1328 #define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))
\r
1330 /* DMA channel 1 registers */
\r
1331 #define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))
\r
1332 #define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))
\r
1333 #define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))
\r
1334 #define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))
\r
1335 #define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))
\r
1338 /* USB Controller */
\r
1339 #define USB_INT_BASE_ADDR 0x400FC1C0
\r
1340 #define USB_BASE_ADDR 0x5000C200 /* USB Base Address */
\r
1342 #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
\r
1344 /* USB Device Interrupt Registers */
\r
1345 #define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
\r
1346 #define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
\r
1347 #define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
\r
1348 #define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
\r
1349 #define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
\r
1351 /* USB Device Endpoint Interrupt Registers */
\r
1352 #define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
\r
1353 #define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
\r
1354 #define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
\r
1355 #define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
\r
1356 #define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
\r
1358 /* USB Device Endpoint Realization Registers */
\r
1359 #define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
\r
1360 #define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
\r
1361 #define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
\r
1363 /* USB Device Command Reagisters */
\r
1364 #define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
\r
1365 #define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
\r
1367 /* USB Device Data Transfer Registers */
\r
1368 #define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
\r
1369 #define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
\r
1370 #define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
\r
1371 #define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
\r
1372 #define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
\r
1374 /* USB Device DMA Registers */
\r
1375 #define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50))
\r
1376 #define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54))
\r
1377 #define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58))
\r
1378 #define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80))
\r
1379 #define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84))
\r
1380 #define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88))
\r
1381 #define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C))
\r
1382 #define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90))
\r
1383 #define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94))
\r
1384 #define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0))
\r
1385 #define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4))
\r
1386 #define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8))
\r
1387 #define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC))
\r
1388 #define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0))
\r
1389 #define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4))
\r
1390 #define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8))
\r
1391 #define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC))
\r
1392 #define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0))
\r
1394 /* USB Host and OTG registers are for LPC24xx only */
\r
1395 /* USB Host Controller */
\r
1396 #define USBHC_BASE_ADDR 0x5000C000
\r
1397 #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
\r
1398 #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
\r
1399 #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
\r
1400 #define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C))
\r
1401 #define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10))
\r
1402 #define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14))
\r
1403 #define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18))
\r
1404 #define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C))
\r
1405 #define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20))
\r
1406 #define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24))
\r
1407 #define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28))
\r
1408 #define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C))
\r
1409 #define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30))
\r
1410 #define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34))
\r
1411 #define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38))
\r
1412 #define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C))
\r
1413 #define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40))
\r
1414 #define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44))
\r
1415 #define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48))
\r
1416 #define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C))
\r
1417 #define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50))
\r
1418 #define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54))
\r
1419 #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
\r
1421 /* USB OTG Controller */
\r
1422 #define USBOTG_BASE_ADDR 0x5000C100
\r
1423 #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
\r
1424 #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
\r
1425 #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
\r
1426 #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
\r
1427 /* On LPC17xx, the name is USBPortSel */
\r
1428 #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
\r
1429 #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
\r
1431 #define USBOTG_I2C_BASE_ADDR 0x5000C300
\r
1432 #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
\r
1433 #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
\r
1434 #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
\r
1435 #define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08))
\r
1436 #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
\r
1437 #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
\r
1439 /* On LPC17xx, the names are USBClkCtrl and USBClkSt */
\r
1440 #define USBOTG_CLK_BASE_ADDR 0x5000CFF0
\r
1441 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
\r
1442 #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
\r
1444 /* Note: below three register name convention is for LPC17xx USB device only, match
\r
1445 with the spec. update in USB Device Section. */
\r
1446 #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
\r
1447 #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
\r
1448 #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
\r
1450 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
\r
1451 #define MAC_BASE_ADDR 0x50000000
\r
1452 #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
\r
1453 #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
\r
1454 #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
\r
1455 #define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
\r
1456 #define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
\r
1457 #define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
\r
1458 #define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
\r
1459 #define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
\r
1460 #define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
\r
1461 #define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
\r
1462 #define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
\r
1463 #define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
\r
1464 #define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
\r
1465 #define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
\r
1467 #define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
\r
1468 #define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
\r
1469 #define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
\r
1471 #define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
\r
1472 #define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
\r
1473 #define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
\r
1474 #define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
\r
1475 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
\r
1476 #define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
\r
1477 #define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
\r
1478 #define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
\r
1479 #define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
\r
1480 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
\r
1481 #define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
\r
1482 #define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
\r
1484 #define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
\r
1485 #define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
\r
1486 #define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
\r
1488 #define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
\r
1489 #define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
\r
1491 #define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
\r
1492 #define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
\r
1493 #define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
\r
1495 #define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
\r
1496 #define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
\r
1498 #define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
\r
1499 #define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
\r
1500 #define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
\r
1501 #define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
\r
1503 #define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
\r
1504 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
\r
1507 #define FLASHCFG (*(volatile unsigned long * ) (0x400F C000))
\r
1509 #endif // __LPC17xx_H
\r
projects / freertos / blob