1 /******************************************************************************
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3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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5 * @date: 22. May 2009
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6 *----------------------------------------------------------------------------
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8 * Copyright (C) 2009 ARM Limited. All rights reserved.
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10 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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11 * processor based microcontrollers. This file can be freely distributed
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12 * within development tools that are supporting such ARM based processors.
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14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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17 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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18 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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20 ******************************************************************************/
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22 #ifndef __CM3_CORE_H__
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23 #define __CM3_CORE_H__
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29 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
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30 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
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31 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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33 #define __CORTEX_M (0x03) /*!< Cortex core */
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36 * Lint configuration \n
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37 * ----------------------- \n
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39 * The following Lint messages will be suppressed and not shown: \n
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41 * --- Error 10: --- \n
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42 * register uint32_t __regBasePri __asm("basepri"); \n
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43 * Error 10: Expecting ';' \n
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45 * --- Error 530: --- \n
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46 * return(__regBasePri); \n
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47 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
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49 * --- Error 550: --- \n
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50 * __regBasePri = (basePri & 0x1ff); \n
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52 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
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54 * --- Error 754: --- \n
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55 * uint32_t RESERVED0[24]; \n
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56 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
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58 * --- Error 750: --- \n
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59 * #define __CM3_CORE_H__ \n
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60 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
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62 * --- Error 528: --- \n
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63 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
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64 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
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66 * --- Error 751: --- \n
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67 * } InterruptType_Type; \n
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68 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
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71 * Note: To re-enable a Message, insert a space before 'lint' * \n
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85 #include <stdint.h> /* Include standard types */
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87 #if defined (__ICCARM__)
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88 #include <intrinsics.h> /* IAR Intrinsics */
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92 #ifndef __NVIC_PRIO_BITS
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93 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
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102 * define access restrictions to peripheral registers
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106 #define __I volatile /*!< defines 'read only' permissions */
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108 #define __I volatile const /*!< defines 'read only' permissions */
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110 #define __O volatile /*!< defines 'write only' permissions */
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111 #define __IO volatile /*!< defines 'read / write' permissions */
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115 /*******************************************************************************
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116 * Register Abstraction
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117 ******************************************************************************/
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121 #define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
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122 #define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
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123 #define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
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124 #define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
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127 #define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
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128 #define ITM_TCR_ITMENA 1 /*!< ITM enable */
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133 /* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
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136 __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
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137 uint32_t RESERVED0[24];
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138 __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
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139 uint32_t RSERVED1[24];
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140 __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
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141 uint32_t RESERVED2[24];
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142 __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
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143 uint32_t RESERVED3[24];
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144 __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
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145 uint32_t RESERVED4[56];
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146 __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
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147 uint32_t RESERVED5[644];
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148 __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
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152 /* memory mapping struct for System Control Block */
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155 __I uint32_t CPUID; /*!< CPU ID Base Register */
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156 __IO uint32_t ICSR; /*!< Interrupt Control State Register */
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157 __IO uint32_t VTOR; /*!< Vector Table Offset Register */
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158 __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
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159 __IO uint32_t SCR; /*!< System Control Register */
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160 __IO uint32_t CCR; /*!< Configuration Control Register */
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161 __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
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162 __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
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163 __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
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164 __IO uint32_t HFSR; /*!< Hard Fault Status Register */
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165 __IO uint32_t DFSR; /*!< Debug Fault Status Register */
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166 __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
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167 __IO uint32_t BFAR; /*!< Bus Fault Address Register */
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168 __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
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169 __I uint32_t PFR[2]; /*!< Processor Feature Register */
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170 __I uint32_t DFR; /*!< Debug Feature Register */
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171 __I uint32_t ADR; /*!< Auxiliary Feature Register */
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172 __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
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173 __I uint32_t ISAR[5]; /*!< ISA Feature Register */
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177 /* memory mapping struct for SysTick */
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180 __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
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181 __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
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182 __IO uint32_t VAL; /*!< SysTick Current Value Register */
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183 __I uint32_t CALIB; /*!< SysTick Calibration Register */
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187 /* memory mapping structur for ITM */
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192 __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
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193 __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
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194 __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
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195 } PORT [32]; /*!< ITM Stimulus Port Registers */
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196 uint32_t RESERVED0[864];
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197 __IO uint32_t TER; /*!< ITM Trace Enable Register */
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198 uint32_t RESERVED1[15];
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199 __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
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200 uint32_t RESERVED2[15];
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201 __IO uint32_t TCR; /*!< ITM Trace Control Register */
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202 uint32_t RESERVED3[29];
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203 __IO uint32_t IWR; /*!< ITM Integration Write Register */
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204 __IO uint32_t IRR; /*!< ITM Integration Read Register */
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205 __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
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206 uint32_t RESERVED4[43];
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207 __IO uint32_t LAR; /*!< ITM Lock Access Register */
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208 __IO uint32_t LSR; /*!< ITM Lock Status Register */
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209 uint32_t RESERVED5[6];
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210 __I uint32_t PID4; /*!< ITM Product ID Registers */
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225 /* memory mapped struct for Interrupt Type */
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228 uint32_t RESERVED0;
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229 __I uint32_t ICTR; /*!< Interrupt Control Type Register */
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230 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
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231 __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
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233 uint32_t RESERVED1;
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235 } InterruptType_Type;
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238 /* Memory Protection Unit */
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239 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
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242 __I uint32_t TYPE; /*!< MPU Type Register */
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243 __IO uint32_t CTRL; /*!< MPU Control Register */
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244 __IO uint32_t RNR; /*!< MPU Region RNRber Register */
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245 __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
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246 __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
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247 __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
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248 __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
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249 __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
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250 __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
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251 __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
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252 __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
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257 /* Core Debug Register */
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260 __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
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261 __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
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262 __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
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263 __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
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267 /* Memory mapping of Cortex-M3 Hardware */
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268 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
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269 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */
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270 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
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271 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
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272 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
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273 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
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275 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
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276 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
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277 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
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278 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
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279 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
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280 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
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282 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
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283 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
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284 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
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289 /*******************************************************************************
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290 * Hardware Abstraction Layer
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291 ******************************************************************************/
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294 #if defined ( __CC_ARM )
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295 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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296 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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298 #elif defined ( __ICCARM__ )
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299 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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300 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
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302 #elif defined ( __GNUC__ )
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303 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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304 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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306 #elif defined ( __TASKING__ )
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307 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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308 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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313 /* ################### Compiler specific Intrinsics ########################### */
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315 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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316 /* ARM armcc specific functions */
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318 #define __enable_fault_irq __enable_fiq
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319 #define __disable_fault_irq __disable_fiq
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321 #define __NOP __nop
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322 #define __WFI __wfi
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323 #define __WFE __wfe
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324 #define __SEV __sev
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325 #define __ISB() __isb(0)
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326 #define __DSB() __dsb(0)
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327 #define __DMB() __dmb(0)
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328 #define __REV __rev
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329 #define __RBIT __rbit
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330 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
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331 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
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332 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
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333 #define __STREXB(value, ptr) __strex(value, ptr)
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334 #define __STREXH(value, ptr) __strex(value, ptr)
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335 #define __STREXW(value, ptr) __strex(value, ptr)
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338 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
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339 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
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340 /* intrinsic void __enable_irq(); */
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341 /* intrinsic void __disable_irq(); */
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345 * @brief Return the Process Stack Pointer
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348 * @return uint32_t ProcessStackPointer
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350 * Return the actual process stack pointer
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352 extern uint32_t __get_PSP(void);
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355 * @brief Set the Process Stack Pointer
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357 * @param uint32_t Process Stack Pointer
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360 * Assign the value ProcessStackPointer to the MSP
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361 * (process stack pointer) Cortex processor register
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363 extern void __set_PSP(uint32_t topOfProcStack);
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366 * @brief Return the Main Stack Pointer
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369 * @return uint32_t Main Stack Pointer
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371 * Return the current value of the MSP (main stack pointer)
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372 * Cortex processor register
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374 extern uint32_t __get_MSP(void);
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377 * @brief Set the Main Stack Pointer
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379 * @param uint32_t Main Stack Pointer
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382 * Assign the value mainStackPointer to the MSP
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383 * (main stack pointer) Cortex processor register
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385 extern void __set_MSP(uint32_t topOfMainStack);
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388 * @brief Reverse byte order in unsigned short value
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390 * @param uint16_t value to reverse
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391 * @return uint32_t reversed value
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393 * Reverse byte order in unsigned short value
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395 extern uint32_t __REV16(uint16_t value);
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398 * @brief Reverse byte order in signed short value with sign extension to integer
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400 * @param int16_t value to reverse
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401 * @return int32_t reversed value
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403 * Reverse byte order in signed short value with sign extension to integer
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405 extern int32_t __REVSH(int16_t value);
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408 #if (__ARMCC_VERSION < 400000)
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411 * @brief Remove the exclusive lock created by ldrex
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416 * Removes the exclusive lock which is created by ldrex.
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418 extern void __CLREX(void);
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421 * @brief Return the Base Priority value
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424 * @return uint32_t BasePriority
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426 * Return the content of the base priority register
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428 extern uint32_t __get_BASEPRI(void);
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431 * @brief Set the Base Priority value
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433 * @param uint32_t BasePriority
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436 * Set the base priority register
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438 extern void __set_BASEPRI(uint32_t basePri);
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441 * @brief Return the Priority Mask value
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444 * @return uint32_t PriMask
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446 * Return the state of the priority mask bit from the priority mask
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449 extern uint32_t __get_PRIMASK(void);
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452 * @brief Set the Priority Mask value
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454 * @param uint32_t PriMask
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457 * Set the priority mask bit in the priority mask register
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459 extern void __set_PRIMASK(uint32_t priMask);
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462 * @brief Return the Fault Mask value
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465 * @return uint32_t FaultMask
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467 * Return the content of the fault mask register
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469 extern uint32_t __get_FAULTMASK(void);
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472 * @brief Set the Fault Mask value
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474 * @param uint32_t faultMask value
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477 * Set the fault mask register
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479 extern void __set_FAULTMASK(uint32_t faultMask);
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482 * @brief Return the Control Register value
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485 * @return uint32_t Control value
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487 * Return the content of the control register
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489 extern uint32_t __get_CONTROL(void);
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492 * @brief Set the Control Register value
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494 * @param uint32_t Control value
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497 * Set the control register
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499 extern void __set_CONTROL(uint32_t control);
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501 #else /* (__ARMCC_VERSION >= 400000) */
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505 * @brief Remove the exclusive lock created by ldrex
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510 * Removes the exclusive lock which is created by ldrex.
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512 #define __CLREX __clrex
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515 * @brief Return the Base Priority value
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518 * @return uint32_t BasePriority
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520 * Return the content of the base priority register
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522 static __INLINE uint32_t __get_BASEPRI(void)
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524 register uint32_t __regBasePri __ASM("basepri");
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525 return(__regBasePri);
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529 * @brief Set the Base Priority value
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531 * @param uint32_t BasePriority
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534 * Set the base priority register
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536 static __INLINE void __set_BASEPRI(uint32_t basePri)
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538 register uint32_t __regBasePri __ASM("basepri");
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539 __regBasePri = (basePri & 0x1ff);
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543 * @brief Return the Priority Mask value
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546 * @return uint32_t PriMask
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548 * Return the state of the priority mask bit from the priority mask
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551 static __INLINE uint32_t __get_PRIMASK(void)
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553 register uint32_t __regPriMask __ASM("primask");
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554 return(__regPriMask);
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558 * @brief Set the Priority Mask value
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560 * @param uint32_t PriMask
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563 * Set the priority mask bit in the priority mask register
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565 static __INLINE void __set_PRIMASK(uint32_t priMask)
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567 register uint32_t __regPriMask __ASM("primask");
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568 __regPriMask = (priMask);
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572 * @brief Return the Fault Mask value
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575 * @return uint32_t FaultMask
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577 * Return the content of the fault mask register
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579 static __INLINE uint32_t __get_FAULTMASK(void)
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581 register uint32_t __regFaultMask __ASM("faultmask");
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582 return(__regFaultMask);
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586 * @brief Set the Fault Mask value
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588 * @param uint32_t faultMask value
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591 * Set the fault mask register
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593 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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595 register uint32_t __regFaultMask __ASM("faultmask");
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596 __regFaultMask = (faultMask & 1);
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600 * @brief Return the Control Register value
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603 * @return uint32_t Control value
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605 * Return the content of the control register
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607 static __INLINE uint32_t __get_CONTROL(void)
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609 register uint32_t __regControl __ASM("control");
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610 return(__regControl);
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614 * @brief Set the Control Register value
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616 * @param uint32_t Control value
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619 * Set the control register
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621 static __INLINE void __set_CONTROL(uint32_t control)
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623 register uint32_t __regControl __ASM("control");
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624 __regControl = control;
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627 #endif /* __ARMCC_VERSION */
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631 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
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632 /* IAR iccarm specific functions */
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634 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
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635 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
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637 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
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638 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
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640 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
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641 static __INLINE void __WFI() { __ASM ("wfi"); }
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642 static __INLINE void __WFE() { __ASM ("wfe"); }
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643 static __INLINE void __SEV() { __ASM ("sev"); }
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644 static __INLINE void __CLREX() { __ASM ("clrex"); }
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646 /* intrinsic void __ISB(void) */
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647 /* intrinsic void __DSB(void) */
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648 /* intrinsic void __DMB(void) */
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649 /* intrinsic void __set_PRIMASK(); */
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650 /* intrinsic void __get_PRIMASK(); */
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651 /* intrinsic void __set_FAULTMASK(); */
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652 /* intrinsic void __get_FAULTMASK(); */
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653 /* intrinsic uint32_t __REV(uint32_t value); */
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654 /* intrinsic uint32_t __REVSH(uint32_t value); */
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655 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
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656 /* intrinsic unsigned long __LDREX(unsigned long *); */
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660 * @brief Return the Process Stack Pointer
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663 * @return uint32_t ProcessStackPointer
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665 * Return the actual process stack pointer
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667 extern uint32_t __get_PSP(void);
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670 * @brief Set the Process Stack Pointer
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672 * @param uint32_t Process Stack Pointer
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675 * Assign the value ProcessStackPointer to the MSP
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676 * (process stack pointer) Cortex processor register
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678 extern void __set_PSP(uint32_t topOfProcStack);
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681 * @brief Return the Main Stack Pointer
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684 * @return uint32_t Main Stack Pointer
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686 * Return the current value of the MSP (main stack pointer)
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687 * Cortex processor register
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689 extern uint32_t __get_MSP(void);
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692 * @brief Set the Main Stack Pointer
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694 * @param uint32_t Main Stack Pointer
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697 * Assign the value mainStackPointer to the MSP
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698 * (main stack pointer) Cortex processor register
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700 extern void __set_MSP(uint32_t topOfMainStack);
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703 * @brief Reverse byte order in unsigned short value
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705 * @param uint16_t value to reverse
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706 * @return uint32_t reversed value
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708 * Reverse byte order in unsigned short value
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710 extern uint32_t __REV16(uint16_t value);
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713 * @brief Reverse bit order of value
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715 * @param uint32_t value to reverse
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716 * @return uint32_t reversed value
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718 * Reverse bit order of value
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720 extern uint32_t __RBIT(uint32_t value);
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723 * @brief LDR Exclusive
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725 * @param uint8_t* address
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726 * @return uint8_t value of (*address)
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728 * Exclusive LDR command
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730 extern uint8_t __LDREXB(uint8_t *addr);
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733 * @brief LDR Exclusive
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735 * @param uint16_t* address
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736 * @return uint16_t value of (*address)
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738 * Exclusive LDR command
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740 extern uint16_t __LDREXH(uint16_t *addr);
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743 * @brief LDR Exclusive
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745 * @param uint32_t* address
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746 * @return uint32_t value of (*address)
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748 * Exclusive LDR command
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750 extern uint32_t __LDREXW(uint32_t *addr);
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753 * @brief STR Exclusive
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755 * @param uint8_t *address
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756 * @param uint8_t value to store
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757 * @return uint32_t successful / failed
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759 * Exclusive STR command
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761 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
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764 * @brief STR Exclusive
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766 * @param uint16_t *address
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767 * @param uint16_t value to store
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768 * @return uint32_t successful / failed
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770 * Exclusive STR command
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772 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
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775 * @brief STR Exclusive
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777 * @param uint32_t *address
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778 * @param uint32_t value to store
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779 * @return uint32_t successful / failed
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781 * Exclusive STR command
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783 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
\r
787 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
\r
788 /* GNU gcc specific functions */
\r
790 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
\r
791 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
\r
793 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
\r
794 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
\r
796 static __INLINE void __NOP() { __ASM volatile ("nop"); }
\r
797 static __INLINE void __WFI() { __ASM volatile ("wfi"); }
\r
798 static __INLINE void __WFE() { __ASM volatile ("wfe"); }
\r
799 static __INLINE void __SEV() { __ASM volatile ("sev"); }
\r
800 static __INLINE void __ISB() { __ASM volatile ("isb"); }
\r
801 static __INLINE void __DSB() { __ASM volatile ("dsb"); }
\r
802 static __INLINE void __DMB() { __ASM volatile ("dmb"); }
\r
803 static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
\r
807 * @brief Return the Process Stack Pointer
\r
810 * @return uint32_t ProcessStackPointer
\r
812 * Return the actual process stack pointer
\r
814 extern uint32_t __get_PSP(void);
\r
817 * @brief Set the Process Stack Pointer
\r
819 * @param uint32_t Process Stack Pointer
\r
822 * Assign the value ProcessStackPointer to the MSP
\r
823 * (process stack pointer) Cortex processor register
\r
825 extern void __set_PSP(uint32_t topOfProcStack);
\r
828 * @brief Return the Main Stack Pointer
\r
831 * @return uint32_t Main Stack Pointer
\r
833 * Return the current value of the MSP (main stack pointer)
\r
834 * Cortex processor register
\r
836 extern uint32_t __get_MSP(void);
\r
839 * @brief Set the Main Stack Pointer
\r
841 * @param uint32_t Main Stack Pointer
\r
844 * Assign the value mainStackPointer to the MSP
\r
845 * (main stack pointer) Cortex processor register
\r
847 extern void __set_MSP(uint32_t topOfMainStack);
\r
850 * @brief Return the Base Priority value
\r
853 * @return uint32_t BasePriority
\r
855 * Return the content of the base priority register
\r
857 extern uint32_t __get_BASEPRI(void);
\r
860 * @brief Set the Base Priority value
\r
862 * @param uint32_t BasePriority
\r
865 * Set the base priority register
\r
867 extern void __set_BASEPRI(uint32_t basePri);
\r
870 * @brief Return the Priority Mask value
\r
873 * @return uint32_t PriMask
\r
875 * Return the state of the priority mask bit from the priority mask
\r
878 extern uint32_t __get_PRIMASK(void);
\r
881 * @brief Set the Priority Mask value
\r
883 * @param uint32_t PriMask
\r
886 * Set the priority mask bit in the priority mask register
\r
888 extern void __set_PRIMASK(uint32_t priMask);
\r
891 * @brief Return the Fault Mask value
\r
894 * @return uint32_t FaultMask
\r
896 * Return the content of the fault mask register
\r
898 extern uint32_t __get_FAULTMASK(void);
\r
901 * @brief Set the Fault Mask value
\r
903 * @param uint32_t faultMask value
\r
906 * Set the fault mask register
\r
908 extern void __set_FAULTMASK(uint32_t faultMask);
\r
911 * @brief Return the Control Register value
\r
914 * @return uint32_t Control value
\r
916 * Return the content of the control register
\r
918 extern uint32_t __get_CONTROL(void);
\r
921 * @brief Set the Control Register value
\r
923 * @param uint32_t Control value
\r
926 * Set the control register
\r
928 extern void __set_CONTROL(uint32_t control);
\r
931 * @brief Reverse byte order in integer value
\r
933 * @param uint32_t value to reverse
\r
934 * @return uint32_t reversed value
\r
936 * Reverse byte order in integer value
\r
938 extern uint32_t __REV(uint32_t value);
\r
941 * @brief Reverse byte order in unsigned short value
\r
943 * @param uint16_t value to reverse
\r
944 * @return uint32_t reversed value
\r
946 * Reverse byte order in unsigned short value
\r
948 extern uint32_t __REV16(uint16_t value);
\r
951 * Reverse byte order in signed short value with sign extension to integer
\r
953 * @param int16_t value to reverse
\r
954 * @return int32_t reversed value
\r
956 * @brief Reverse byte order in signed short value with sign extension to integer
\r
958 extern int32_t __REVSH(int16_t value);
\r
961 * @brief Reverse bit order of value
\r
963 * @param uint32_t value to reverse
\r
964 * @return uint32_t reversed value
\r
966 * Reverse bit order of value
\r
968 extern uint32_t __RBIT(uint32_t value);
\r
971 * @brief LDR Exclusive
\r
973 * @param uint8_t* address
\r
974 * @return uint8_t value of (*address)
\r
976 * Exclusive LDR command
\r
978 extern uint8_t __LDREXB(uint8_t *addr);
\r
981 * @brief LDR Exclusive
\r
983 * @param uint16_t* address
\r
984 * @return uint16_t value of (*address)
\r
986 * Exclusive LDR command
\r
988 extern uint16_t __LDREXH(uint16_t *addr);
\r
991 * @brief LDR Exclusive
\r
993 * @param uint32_t* address
\r
994 * @return uint32_t value of (*address)
\r
996 * Exclusive LDR command
\r
998 extern uint32_t __LDREXW(uint32_t *addr);
\r
1001 * @brief STR Exclusive
\r
1003 * @param uint8_t *address
\r
1004 * @param uint8_t value to store
\r
1005 * @return uint32_t successful / failed
\r
1007 * Exclusive STR command
\r
1009 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
\r
1012 * @brief STR Exclusive
\r
1014 * @param uint16_t *address
\r
1015 * @param uint16_t value to store
\r
1016 * @return uint32_t successful / failed
\r
1018 * Exclusive STR command
\r
1020 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
\r
1023 * @brief STR Exclusive
\r
1025 * @param uint32_t *address
\r
1026 * @param uint32_t value to store
\r
1027 * @return uint32_t successful / failed
\r
1029 * Exclusive STR command
\r
1031 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
\r
1034 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
\r
1035 /* TASKING carm specific functions */
\r
1038 * The CMSIS functions have been implemented as intrinsics in the compiler.
\r
1039 * Please use "carm -?i" to get an up to date list of all instrinsics,
\r
1040 * Including the CMSIS ones.
\r
1047 /* ########################## NVIC functions #################################### */
\r
1051 * @brief Set the Priority Grouping in NVIC Interrupt Controller
\r
1053 * @param uint32_t priority_grouping is priority grouping field
\r
1056 * Set the priority grouping field using the required unlock sequence.
\r
1057 * The parameter priority_grouping is assigned to the field
\r
1058 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
\r
1059 * In case of a conflict between priority grouping and available
\r
1060 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\r
1062 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\r
1064 uint32_t reg_value;
\r
1065 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1067 reg_value = SCB->AIRCR; /* read old register configuration */
\r
1068 reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
\r
1069 reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
\r
1070 SCB->AIRCR = reg_value;
\r
1074 * @brief Get the Priority Grouping from NVIC Interrupt Controller
\r
1077 * @return uint32_t priority grouping field
\r
1079 * Get the priority grouping from NVIC Interrupt Controller.
\r
1080 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
\r
1082 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
\r
1084 return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
\r
1088 * @brief Enable Interrupt in NVIC Interrupt Controller
\r
1090 * @param IRQn_Type IRQn specifies the interrupt number
\r
1093 * Enable a device specific interupt in the NVIC interrupt controller.
\r
1094 * The interrupt number cannot be a negative value.
\r
1096 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\r
1098 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
\r
1102 * @brief Disable the interrupt line for external interrupt specified
\r
1104 * @param IRQn_Type IRQn is the positive number of the external interrupt
\r
1107 * Disable a device specific interupt in the NVIC interrupt controller.
\r
1108 * The interrupt number cannot be a negative value.
\r
1110 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\r
1112 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
\r
1116 * @brief Read the interrupt pending bit for a device specific interrupt source
\r
1118 * @param IRQn_Type IRQn is the number of the device specifc interrupt
\r
1119 * @return uint32_t 1 if pending interrupt else 0
\r
1121 * Read the pending register in NVIC and return 1 if its status is pending,
\r
1122 * otherwise it returns 0
\r
1124 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\r
1126 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
\r
1130 * @brief Set the pending bit for an external interrupt
\r
1132 * @param IRQn_Type IRQn is the Number of the interrupt
\r
1135 * Set the pending bit for the specified interrupt.
\r
1136 * The interrupt number cannot be a negative value.
\r
1138 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\r
1140 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
\r
1144 * @brief Clear the pending bit for an external interrupt
\r
1146 * @param IRQn_Type IRQn is the Number of the interrupt
\r
1149 * Clear the pending bit for the specified interrupt.
\r
1150 * The interrupt number cannot be a negative value.
\r
1152 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\r
1154 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
\r
1158 * @brief Read the active bit for an external interrupt
\r
1160 * @param IRQn_Type IRQn is the Number of the interrupt
\r
1161 * @return uint32_t 1 if active else 0
\r
1163 * Read the active register in NVIC and returns 1 if its status is active,
\r
1164 * otherwise it returns 0.
\r
1166 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\r
1168 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
\r
1172 * @brief Set the priority for an interrupt
\r
1174 * @param IRQn_Type IRQn is the Number of the interrupt
\r
1175 * @param priority is the priority for the interrupt
\r
1178 * Set the priority for the specified interrupt. The interrupt
\r
1179 * number can be positive to specify an external (device specific)
\r
1180 * interrupt, or negative to specify an internal (core) interrupt. \n
\r
1182 * Note: The priority cannot be set for every core interrupt.
\r
1184 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\r
1187 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
\r
1189 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
\r
1193 * @brief Read the priority for an interrupt
\r
1195 * @param IRQn_Type IRQn is the Number of the interrupt
\r
1196 * @return uint32_t priority is the priority for the interrupt
\r
1198 * Read the priority for the specified interrupt. The interrupt
\r
1199 * number can be positive to specify an external (device specific)
\r
1200 * interrupt, or negative to specify an internal (core) interrupt.
\r
1202 * The returned priority value is automatically aligned to the implemented
\r
1203 * priority bits of the microcontroller.
\r
1205 * Note: The priority cannot be set for every core interrupt.
\r
1207 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\r
1211 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
\r
1213 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
\r
1218 * @brief Encode the priority for an interrupt
\r
1220 * @param uint32_t PriorityGroup is the used priority group
\r
1221 * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
\r
1222 * @param uint32_t SubPriority is the sub priority value (starting from 0)
\r
1223 * @return uint32_t the priority for the interrupt
\r
1225 * Encode the priority for an interrupt with the given priority group,
\r
1226 * preemptive priority value and sub priority value.
\r
1227 * In case of a conflict between priority grouping and available
\r
1228 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
\r
1230 * The returned priority value can be used for NVIC_SetPriority(...) function
\r
1232 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
\r
1234 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1235 uint32_t PreemptPriorityBits;
\r
1236 uint32_t SubPriorityBits;
\r
1238 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
\r
1239 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
\r
1242 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
\r
1243 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
\r
1249 * @brief Decode the priority of an interrupt
\r
1251 * @param uint32_t Priority the priority for the interrupt
\r
1252 * @param uint32_t PrioGroup is the used priority group
\r
1253 * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
\r
1254 * @param uint32_t* pSubPrio is the sub priority value (starting from 0)
\r
1257 * Decode an interrupt priority value with the given priority group to
\r
1258 * preemptive priority value and sub priority value.
\r
1259 * In case of a conflict between priority grouping and available
\r
1260 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
\r
1262 * The priority value can be retrieved with NVIC_GetPriority(...) function
\r
1264 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
\r
1266 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
\r
1267 uint32_t PreemptPriorityBits;
\r
1268 uint32_t SubPriorityBits;
\r
1270 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
\r
1271 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
\r
1273 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
\r
1274 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
\r
1279 /* ################################## SysTick function ############################################ */
\r
1281 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
\r
1283 /* SysTick constants */
\r
1284 #define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
\r
1285 #define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
\r
1286 #define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
\r
1287 #define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
\r
1290 * @brief Initialize and start the SysTick counter and its interrupt.
\r
1292 * @param uint32_t ticks is the number of ticks between two interrupts
\r
1295 * Initialise the system tick timer and its interrupt and start the
\r
1296 * system tick timer / counter in free running mode to generate
\r
1297 * periodical interrupts.
\r
1299 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
\r
1301 if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
\r
1303 SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
\r
1304 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
\r
1305 SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
\r
1306 SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
\r
1307 return (0); /* Function successful */
\r
1316 /* ################################## Reset function ############################################ */
\r
1319 * @brief Initiate a system reset request.
\r
1324 * Initialize a system reset request to reset the MCU
\r
1326 static __INLINE void NVIC_SystemReset(void)
\r
1328 SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
\r
1329 __DSB(); /* Ensure completion of memory access */
\r
1330 while(1); /* wait until reset */
\r
1334 /* ################################## Debug Output function ############################################ */
\r
1338 * @brief Outputs a character via the ITM channel 0
\r
1340 * @param uint32_t character to output
\r
1341 * @return uint32_t input character
\r
1343 * The function outputs a character via the ITM channel 0.
\r
1344 * The function returns when no debugger is connected that has booked the output.
\r
1345 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
\r
1347 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
\r
1349 if (ch == '\n') ITM_SendChar('\r');
\r
1351 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
\r
1352 (ITM->TCR & ITM_TCR_ITMENA) &&
\r
1353 (ITM->TER & (1UL << 0)) )
\r
1355 while (ITM->PORT[0].u32 == 0);
\r
1356 ITM->PORT[0].u8 = (uint8_t) ch;
\r
1361 #ifdef __cplusplus
\r
1365 #endif /* __CM3_CORE_H__ */
\r
1367 /*lint -restore */
\r