2 FreeRTOS.org V5.4.0 - Copyright (C) 2003-2009 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify it
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7 under the terms of the GNU General Public License (version 2) as published
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8 by the Free Software Foundation and modified by the FreeRTOS exception.
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9 **NOTE** The exception to the GPL is included to allow you to distribute a
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10 combined work that includes FreeRTOS.org without being obliged to provide
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11 the source code for any proprietary components. Alternative commercial
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12 license and support terms are also available upon request. See the
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13 licensing section of http://www.FreeRTOS.org for full details.
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15 FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
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16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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20 You should have received a copy of the GNU General Public License along
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21 with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
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22 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 ***************************************************************************
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27 * Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
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29 * This is a concise, step by step, 'hands on' guide that describes both *
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30 * general multitasking concepts and FreeRTOS specifics. It presents and *
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31 * explains numerous examples that are written using the FreeRTOS API. *
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32 * Full source code for all the examples is provided in an accompanying *
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35 ***************************************************************************
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39 Please ensure to read the configuration and relevant port sections of the
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40 online documentation.
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42 http://www.FreeRTOS.org - Documentation, latest information, license and
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45 http://www.SafeRTOS.com - A version that is certified for use in safety
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48 http://www.OpenRTOS.com - Commercial support, development, porting,
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49 licensing and training services.
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52 /* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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54 /* Kernel includes. */
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55 #include "FreeRTOS.h"
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59 /* Hardware specific includes. */
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60 #include "LPC17xx_defs.h"
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61 #include "EthDev_LPC17xx.h"
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63 /* Time to wait between each inspection of the link status. */
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64 #define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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66 /* Short delay used in several places during the initialisation process. */
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67 #define emacSHORT_DELAY ( 2 )
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69 /* Hardware specific bit definitions. */
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70 #define emacLINK_ESTABLISHED ( 0x0001 )
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71 #define emacFULL_DUPLEX_ENABLED ( 0x0004 )
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72 #define emac10BASE_T_MODE ( 0x0002 )
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73 #define emacPINSEL2_VALUE 0x50150105
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75 /* If no buffers are available, then wait this long before looking again.... */
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76 #define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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78 /* ...and don't look more than this many times. */
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79 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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81 /* Index to the Tx descriptor that is always used first for every Tx. The second
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82 descriptor is then used to re-send in order to speed up the uIP Tx process. */
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83 #define emacTX_DESC_INDEX ( 0 )
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85 /*-----------------------------------------------------------*/
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88 * Configure both the Rx and Tx descriptors during the init process.
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90 static void prvInitDescriptors( void );
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93 * Setup the IO and peripherals required for Ethernet communication.
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95 static void prvSetupEMACHardware( void );
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98 * Control the auto negotiate process.
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100 static void prvConfigurePHY( void );
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103 * Wait for a link to be established, then setup the PHY according to the link
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106 static long prvSetupLinkStatus( void );
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109 * Search the pool of buffers to find one that is free. If a buffer is found
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110 * mark it as in use before returning its address.
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112 static unsigned char *prvGetNextBuffer( void );
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115 * Return an allocated buffer to the pool of free buffers.
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117 static void prvReturnBuffer( unsigned char *pucBuffer );
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120 * Send lValue to the lPhyReg within the PHY.
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122 static long prvWritePHY( long lPhyReg, long lValue );
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125 * Read a value from ucPhyReg within the PHY. *plStatus will be set to
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126 * pdFALSE if there is an error.
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128 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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130 /*-----------------------------------------------------------*/
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132 /* The semaphore used to wake the uIP task when data arrives. */
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133 extern xSemaphoreHandle xEMACSemaphore;
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135 /* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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136 If the index contains a 1 then the buffer within pool is in use, if it
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137 contains a 0 then the buffer is free. */
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138 static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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140 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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141 allocated within this file. */
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142 unsigned char * uip_buf;
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144 /* Store the length of the data being sent so the data can be sent twice. The
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145 value will be set back to 0 once the data has been sent twice. */
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146 static unsigned short usSendLen = 0;
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148 /*-----------------------------------------------------------*/
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150 long lEMACInit( void )
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152 long lReturn = pdPASS;
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153 volatile unsigned long regv, tout;
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154 unsigned long ulID1, ulID2;
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156 /* Reset peripherals, configure port pins and registers. */
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157 prvSetupEMACHardware();
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159 /* Check the PHY part number is as expected. */
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160 ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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161 ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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162 if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )
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164 /* Set the Ethernet MAC Address registers */
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165 MAC_SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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166 MAC_SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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167 MAC_SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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169 /* Initialize Tx and Rx DMA Descriptors */
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170 prvInitDescriptors();
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172 /* Receive broadcast and perfect match packets */
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173 MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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175 /* Setup the PHY. */
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183 /* Check the link status. */
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184 if( lReturn == pdPASS )
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186 lReturn = prvSetupLinkStatus();
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189 if( lReturn == pdPASS )
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191 /* Initialise uip_buf to ensure it points somewhere valid. */
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192 uip_buf = prvGetNextBuffer();
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194 /* Reset all interrupts */
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195 MAC_INTCLEAR = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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197 /* Enable receive and transmit mode of MAC Ethernet core */
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198 MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
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199 MAC_MAC1 |= MAC1_REC_EN;
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204 /*-----------------------------------------------------------*/
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206 static unsigned char *prvGetNextBuffer( void )
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209 unsigned char *pucReturn = NULL;
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210 unsigned long ulAttempts = 0;
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212 while( pucReturn == NULL )
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214 /* Look through the buffers to find one that is not in use by
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216 for( x = 0; x < ETH_NUM_BUFFERS; x++ )
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218 if( ucBufferInUse[ x ] == pdFALSE )
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220 ucBufferInUse[ x ] = pdTRUE;
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221 pucReturn = ( unsigned char * ) ETH_BUF( x );
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226 /* Was a buffer found? */
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227 if( pucReturn == NULL )
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231 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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236 /* Wait then look again. */
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237 vTaskDelay( emacBUFFER_WAIT_DELAY );
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243 /*-----------------------------------------------------------*/
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245 static void prvInitDescriptors( void )
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247 long x, lNextBuffer = 0;
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249 for( x = 0; x < NUM_RX_FRAG; x++ )
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251 /* Allocate the next Ethernet buffer to this descriptor. */
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252 RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
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253 RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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254 RX_STAT_INFO( x ) = 0;
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255 RX_STAT_HASHCRC( x ) = 0;
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257 /* The Ethernet buffer is now in use. */
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258 ucBufferInUse[ lNextBuffer ] = pdTRUE;
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262 /* Set EMAC Receive Descriptor Registers. */
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263 MAC_RXDESCRIPTOR = RX_DESC_BASE;
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264 MAC_RXSTATUS = RX_STAT_BASE;
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265 MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;
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267 /* Rx Descriptors Point to 0 */
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268 MAC_RXCONSUMEINDEX = 0;
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270 /* A buffer is not allocated to the Tx descriptors until they are actually
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272 for( x = 0; x < NUM_TX_FRAG; x++ )
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274 TX_DESC_PACKET( x ) = NULL;
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275 TX_DESC_CTRL( x ) = 0;
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276 TX_STAT_INFO( x ) = 0;
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279 /* Set EMAC Transmit Descriptor Registers. */
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280 MAC_TXDESCRIPTOR = TX_DESC_BASE;
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281 MAC_TXSTATUS = TX_STAT_BASE;
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282 MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;
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284 /* Tx Descriptors Point to 0 */
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285 MAC_TXPRODUCEINDEX = 0;
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287 /*-----------------------------------------------------------*/
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289 static void prvSetupEMACHardware( void )
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294 /* Enable P1 Ethernet Pins. */
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295 PINSEL2 = emacPINSEL2_VALUE;
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296 PINSEL3 = ( PINSEL3 & ~0x0000000F ) | 0x00000005;
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298 /* Power Up the EMAC controller. */
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299 PCONP |= PCONP_PCENET;
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300 vTaskDelay( emacSHORT_DELAY );
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302 /* Reset all EMAC internal modules. */
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303 MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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304 MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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306 /* A short delay after reset. */
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307 vTaskDelay( emacSHORT_DELAY );
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309 /* Initialize MAC control registers. */
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310 MAC_MAC1 = MAC1_PASS_ALL;
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311 MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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312 MAC_MAXF = ETH_MAX_FLEN;
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313 MAC_CLRT = CLRT_DEF;
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314 MAC_IPGR = IPGR_DEF;
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316 /* Enable Reduced MII interface. */
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317 MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
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319 /* Reset Reduced MII Logic. */
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320 MAC_SUPP = SUPP_RES_RMII;
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321 vTaskDelay( emacSHORT_DELAY );
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324 /* Put the PHY in reset mode */
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325 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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326 prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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328 /* Wait for hardware reset to end. */
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329 for( x = 0; x < 100; x++ )
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331 vTaskDelay( emacSHORT_DELAY * 5 );
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332 us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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333 if( !( us & MCFG_RES_MII ) )
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335 /* Reset complete */
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340 /*-----------------------------------------------------------*/
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342 static void prvConfigurePHY( void )
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347 /* Auto negotiate the configuration. */
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348 if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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350 vTaskDelay( emacSHORT_DELAY * 5 );
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352 for( x = 0; x < 10; x++ )
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354 us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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356 if( us & PHY_AUTO_NEG_COMPLETE )
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361 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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365 /*-----------------------------------------------------------*/
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367 static long prvSetupLinkStatus( void )
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369 long lReturn = pdFAIL, x;
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370 unsigned short usLinkStatus;
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372 /* Wait with timeout for the link to be established. */
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373 for( x = 0; x < 10; x++ )
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375 usLinkStatus = prvReadPHY( PHY_REG_STS, &lReturn );
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376 if( usLinkStatus & emacLINK_ESTABLISHED )
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378 /* Link is established. */
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383 vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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386 if( lReturn == pdPASS )
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388 /* Configure Full/Half Duplex mode. */
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389 if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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391 /* Full duplex is enabled. */
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392 MAC_MAC2 |= MAC2_FULL_DUP;
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393 MAC_COMMAND |= CR_FULL_DUP;
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394 MAC_IPGT = IPGT_FULL_DUP;
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398 /* Half duplex mode. */
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399 MAC_IPGT = IPGT_HALF_DUP;
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402 /* Configure 100MBit/10MBit mode. */
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403 if( usLinkStatus & emac10BASE_T_MODE )
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410 /* 100MBit mode. */
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411 MAC_SUPP = SUPP_SPEED;
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417 /*-----------------------------------------------------------*/
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419 static void prvReturnBuffer( unsigned char *pucBuffer )
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423 /* Mark a buffer as free for use. */
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424 for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
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426 if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
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428 ucBufferInUse[ ul ] = pdFALSE;
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433 /*-----------------------------------------------------------*/
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435 unsigned long ulGetEMACRxData( void )
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437 unsigned long ulLen = 0;
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440 if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
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442 /* Mark the current buffer as free as uip_buf is going to be set to
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443 the buffer that contains the received data. */
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444 prvReturnBuffer( uip_buf );
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446 ulLen = ( RX_STAT_INFO( MAC_RXCONSUMEINDEX ) & RINFO_SIZE ) - 3;
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447 uip_buf = ( unsigned char * ) RX_DESC_PACKET( MAC_RXCONSUMEINDEX );
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449 /* Allocate a new buffer to the descriptor. */
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450 RX_DESC_PACKET( MAC_RXCONSUMEINDEX ) = ( unsigned long ) prvGetNextBuffer();
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452 /* Move the consume index onto the next position, ensuring it wraps to
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453 the beginning at the appropriate place. */
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454 lIndex = MAC_RXCONSUMEINDEX;
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457 if( lIndex >= NUM_RX_FRAG )
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462 MAC_RXCONSUMEINDEX = lIndex;
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467 /*-----------------------------------------------------------*/
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469 void vSendEMACTxData( unsigned short usTxDataLen )
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471 unsigned long ulAttempts = 0UL;
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473 /* Check to see if the Tx descriptor is free, indicated by its buffer being
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475 while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != NULL )
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477 /* Wait for the Tx descriptor to become available. */
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478 vTaskDelay( emacBUFFER_WAIT_DELAY );
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481 if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
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483 /* Something has gone wrong as the Tx descriptor is still in use.
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484 Clear it down manually, the data it was sending will probably be
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486 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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491 /* Setup the Tx descriptor for transmission. Remember the length of the
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492 data being sent so the second descriptor can be used to send it again from
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494 usSendLen = usTxDataLen;
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495 TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
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496 TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
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497 MAC_TXPRODUCEINDEX = ( emacTX_DESC_INDEX + 1 );
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499 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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500 uip_buf = prvGetNextBuffer();
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502 /*-----------------------------------------------------------*/
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504 static long prvWritePHY( long lPhyReg, long lValue )
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506 const long lMaxTime = 10;
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509 MAC_MADR = DP83848C_DEF_ADR | lPhyReg;
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513 for( x = 0; x < lMaxTime; x++ )
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515 if( ( MAC_MIND & MIND_BUSY ) == 0 )
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517 /* Operation has finished. */
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521 vTaskDelay( emacSHORT_DELAY );
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533 /*-----------------------------------------------------------*/
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535 static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
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538 const long lMaxTime = 10;
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540 MAC_MADR = DP83848C_DEF_ADR | ucPhyReg;
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541 MAC_MCMD = MCMD_READ;
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543 for( x = 0; x < lMaxTime; x++ )
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545 /* Operation has finished. */
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546 if( ( MAC_MIND & MIND_BUSY ) == 0 )
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551 vTaskDelay( emacSHORT_DELAY );
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556 if( x >= lMaxTime )
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558 *plStatus = pdFAIL;
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561 return( MAC_MRDD );
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563 /*-----------------------------------------------------------*/
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565 void vEMAC_ISR( void )
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567 unsigned long ulStatus;
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568 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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570 ulStatus = MAC_INTSTATUS;
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572 /* Clear the interrupt. */
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573 MAC_INTCLEAR = ulStatus;
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575 if( ulStatus & INT_RX_DONE )
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577 /* Ensure the uIP task is not blocked as data has arrived. */
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578 xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
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581 if( ulStatus & INT_TX_DONE )
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583 if( usSendLen > 0 )
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585 /* Send the data again, using the second descriptor. As there are
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586 only two descriptors the index is set back to 0. */
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587 TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
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588 TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
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589 MAC_TXPRODUCEINDEX = ( emacTX_DESC_INDEX );
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591 /* This is the second Tx so set usSendLen to 0 to indicate that the
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592 Tx descriptors will be free again. */
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597 /* The Tx buffer is no longer required. */
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598 prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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599 TX_DESC_PACKET( emacTX_DESC_INDEX ) = NULL;
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603 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
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